[Qemu-devel] [PATCH v1 20/22] RISC-V: vectored traps are optional

Vectored traps for asynchrounous interrupts are optional. The mtvec/stvec mode field is WARL and hence does not trap if an illegal value is written. Illegal values are ignored. Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt ---

[Qemu-devel] [PATCH v1 20/22] RISC-V: vectored traps are optional

Vectored traps for asynchrounous interrupts are optional. The mtvec/stvec mode field is WARL and hence does not trap if an illegal value is written. Illegal values are ignored. Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt ---