Re: [Qemu-devel] [PATCH v1 20/30] RISC-V: Add misa to DisasContext

2018-05-23 Thread Philippe Mathieu-Daudé 
On 05/22/2018 09:15 PM, Michael Clark wrote:
> gen methods should access state from DisasContext. Add misa
> field to the DisasContext struct and remove CPURISCVState
> argument from all gen methods.
> 
> Cc: Palmer Dabbelt 
> Cc: Sagar Karandikar 
> Cc: Bastian Koppelmann 
> Cc: Alistair Francis 
> Cc: Emilio G. Cota 
> Signed-off-by: Michael Clark 
> Reviewed-by: Richard Henderson 

I already reviewed this one:
http://lists.nongnu.org/archive/html/qemu-devel/2018-05/msg02255.html

Reviewed-by: Philippe Mathieu-Daudé 

> ---
>  target/riscv/translate.c | 78 
> ++--
>  1 file changed, 42 insertions(+), 36 deletions(-)
> 
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index a980611eb611..fd21b133a5a4 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -45,6 +45,7 @@ typedef struct DisasContext {
>  target_ulong pc_succ_insn;
>  uint32_t opcode;
>  uint32_t mstatus_fs;
> +uint32_t misa;
>  uint32_t mem_idx;
>  /* Remember the rounding mode encoded in the previous fp instruction,
> which we have already installed into env->fp_status.  Or -1 for
> @@ -74,6 +75,11 @@ static const int tcg_memop_lookup[8] = {
>  #define CASE_OP_32_64(X) case X
>  #endif
>  
> +static inline bool has_ext(DisasContext *ctx, uint32_t ext)
> +{
> +return ctx->misa & ext;
> +}
> +
>  static void generate_exception(DisasContext *ctx, int excp)
>  {
>  tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
> @@ -505,14 +511,13 @@ static void gen_arith_imm(DisasContext *ctx, uint32_t 
> opc, int rd,
>  tcg_temp_free(source1);
>  }
>  
> -static void gen_jal(CPURISCVState *env, DisasContext *ctx, int rd,
> -target_ulong imm)
> +static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
>  {
>  target_ulong next_pc;
>  
>  /* check misaligned: */
>  next_pc = ctx->base.pc_next + imm;
> -if (!riscv_has_ext(env, RVC)) {
> +if (!has_ext(ctx, RVC)) {
>  if ((next_pc & 0x3) != 0) {
>  gen_exception_inst_addr_mis(ctx);
>  return;
> @@ -526,8 +531,8 @@ static void gen_jal(CPURISCVState *env, DisasContext 
> *ctx, int rd,
>  ctx->base.is_jmp = DISAS_NORETURN;
>  }
>  
> -static void gen_jalr(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
> - int rd, int rs1, target_long imm)
> +static void gen_jalr(DisasContext *ctx, uint32_t opc, int rd, int rs1,
> + target_long imm)
>  {
>  /* no chaining with JALR */
>  TCGLabel *misaligned = NULL;
> @@ -539,7 +544,7 @@ static void gen_jalr(CPURISCVState *env, DisasContext 
> *ctx, uint32_t opc,
>  tcg_gen_addi_tl(cpu_pc, cpu_pc, imm);
>  tcg_gen_andi_tl(cpu_pc, cpu_pc, (target_ulong)-2);
>  
> -if (!riscv_has_ext(env, RVC)) {
> +if (!has_ext(ctx, RVC)) {
>  misaligned = gen_new_label();
>  tcg_gen_andi_tl(t0, cpu_pc, 0x2);
>  tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0x0, misaligned);
> @@ -564,8 +569,8 @@ static void gen_jalr(CPURISCVState *env, DisasContext 
> *ctx, uint32_t opc,
>  tcg_temp_free(t0);
>  }
>  
> -static void gen_branch(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
> -   int rs1, int rs2, target_long bimm)
> +static void gen_branch(DisasContext *ctx, uint32_t opc, int rs1, int rs2,
> +   target_long bimm)
>  {
>  TCGLabel *l = gen_new_label();
>  TCGv source1, source2;
> @@ -602,7 +607,7 @@ static void gen_branch(CPURISCVState *env, DisasContext 
> *ctx, uint32_t opc,
>  
>  gen_goto_tb(ctx, 1, ctx->pc_succ_insn);
>  gen_set_label(l); /* branch taken */
> -if (!riscv_has_ext(env, RVC) && ((ctx->base.pc_next + bimm) & 0x3)) {
> +if (!has_ext(ctx, RVC) && ((ctx->base.pc_next + bimm) & 0x3)) {
>  /* misaligned */
>  gen_exception_inst_addr_mis(ctx);
>  } else {
> @@ -1311,8 +1316,8 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t 
> opc, int rd,
>  }
>  }
>  
> -static void gen_system(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
> -  int rd, int rs1, int csr)
> +static void gen_system(DisasContext *ctx, uint32_t opc, int rd, int rs1,
> +   int csr)
>  {
>  TCGv source1, csr_store, dest, rs1_pass, imm_rs1;
>  source1 = tcg_temp_new();
> @@ -1354,7 +1359,7 @@ static void gen_system(CPURISCVState *env, DisasContext 
> *ctx, uint32_t opc,
>  gen_exception_illegal(ctx);
>  break;
>  case 0x102: /* SRET */
> -if (riscv_has_ext(env, RVS)) {
> +if (has_ext(ctx, RVS)) {
>  gen_helper_sret(cpu_pc, cpu_env, cpu_pc);
>  tcg_gen_exit_tb(0); /* no chaining */
>

[Qemu-devel] [PATCH v1 20/30] RISC-V: Add misa to DisasContext

2018-05-22 Thread Michael Clark 
gen methods should access state from DisasContext. Add misa
field to the DisasContext struct and remove CPURISCVState
argument from all gen methods.

Cc: Palmer Dabbelt 
Cc: Sagar Karandikar 
Cc: Bastian Koppelmann 
Cc: Alistair Francis 
Cc: Emilio G. Cota 
Signed-off-by: Michael Clark 
Reviewed-by: Richard Henderson 
---
 target/riscv/translate.c | 78 ++--
 1 file changed, 42 insertions(+), 36 deletions(-)

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index a980611eb611..fd21b133a5a4 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -45,6 +45,7 @@ typedef struct DisasContext {
 target_ulong pc_succ_insn;
 uint32_t opcode;
 uint32_t mstatus_fs;
+uint32_t misa;
 uint32_t mem_idx;
 /* Remember the rounding mode encoded in the previous fp instruction,
which we have already installed into env->fp_status.  Or -1 for
@@ -74,6 +75,11 @@ static const int tcg_memop_lookup[8] = {
 #define CASE_OP_32_64(X) case X
 #endif
 
+static inline bool has_ext(DisasContext *ctx, uint32_t ext)
+{
+return ctx->misa & ext;
+}
+
 static void generate_exception(DisasContext *ctx, int excp)
 {
 tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
@@ -505,14 +511,13 @@ static void gen_arith_imm(DisasContext *ctx, uint32_t 
opc, int rd,
 tcg_temp_free(source1);
 }
 
-static void gen_jal(CPURISCVState *env, DisasContext *ctx, int rd,
-target_ulong imm)
+static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
 {
 target_ulong next_pc;
 
 /* check misaligned: */
 next_pc = ctx->base.pc_next + imm;
-if (!riscv_has_ext(env, RVC)) {
+if (!has_ext(ctx, RVC)) {
 if ((next_pc & 0x3) != 0) {
 gen_exception_inst_addr_mis(ctx);
 return;
@@ -526,8 +531,8 @@ static void gen_jal(CPURISCVState *env, DisasContext *ctx, 
int rd,
 ctx->base.is_jmp = DISAS_NORETURN;
 }
 
-static void gen_jalr(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
- int rd, int rs1, target_long imm)
+static void gen_jalr(DisasContext *ctx, uint32_t opc, int rd, int rs1,
+ target_long imm)
 {
 /* no chaining with JALR */
 TCGLabel *misaligned = NULL;
@@ -539,7 +544,7 @@ static void gen_jalr(CPURISCVState *env, DisasContext *ctx, 
uint32_t opc,
 tcg_gen_addi_tl(cpu_pc, cpu_pc, imm);
 tcg_gen_andi_tl(cpu_pc, cpu_pc, (target_ulong)-2);
 
-if (!riscv_has_ext(env, RVC)) {
+if (!has_ext(ctx, RVC)) {
 misaligned = gen_new_label();
 tcg_gen_andi_tl(t0, cpu_pc, 0x2);
 tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0x0, misaligned);
@@ -564,8 +569,8 @@ static void gen_jalr(CPURISCVState *env, DisasContext *ctx, 
uint32_t opc,
 tcg_temp_free(t0);
 }
 
-static void gen_branch(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
-   int rs1, int rs2, target_long bimm)
+static void gen_branch(DisasContext *ctx, uint32_t opc, int rs1, int rs2,
+   target_long bimm)
 {
 TCGLabel *l = gen_new_label();
 TCGv source1, source2;
@@ -602,7 +607,7 @@ static void gen_branch(CPURISCVState *env, DisasContext 
*ctx, uint32_t opc,
 
 gen_goto_tb(ctx, 1, ctx->pc_succ_insn);
 gen_set_label(l); /* branch taken */
-if (!riscv_has_ext(env, RVC) && ((ctx->base.pc_next + bimm) & 0x3)) {
+if (!has_ext(ctx, RVC) && ((ctx->base.pc_next + bimm) & 0x3)) {
 /* misaligned */
 gen_exception_inst_addr_mis(ctx);
 } else {
@@ -1311,8 +1316,8 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, 
int rd,
 }
 }
 
-static void gen_system(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
-  int rd, int rs1, int csr)
+static void gen_system(DisasContext *ctx, uint32_t opc, int rd, int rs1,
+   int csr)
 {
 TCGv source1, csr_store, dest, rs1_pass, imm_rs1;
 source1 = tcg_temp_new();
@@ -1354,7 +1359,7 @@ static void gen_system(CPURISCVState *env, DisasContext 
*ctx, uint32_t opc,
 gen_exception_illegal(ctx);
 break;
 case 0x102: /* SRET */
-if (riscv_has_ext(env, RVS)) {
+if (has_ext(ctx, RVS)) {
 gen_helper_sret(cpu_pc, cpu_env, cpu_pc);
 tcg_gen_exit_tb(0); /* no chaining */
 ctx->base.is_jmp = DISAS_NORETURN;
@@ -1495,7 +1500,7 @@ static void decode_RV32_64C0(DisasContext *ctx)
 }
 }
 
-static void decode_RV32_64C1(CPURISCVState *env, DisasContext *ctx)
+static void decode_RV32_64C1(DisasContext *ctx)
 {
 uint8_t funct3 = extract32(ctx->opcode, 13, 3);
 uint8_t rd_rs1 = GET_C_RS1(ctx->opcode);
@@ -1515,7 +1520,7 @@ static void decode_RV32_64C1(CPURISCVState *env, 
DisasContext *ctx)