Re: [Qemu-devel] [PATCH v2] target/arm: Conditionalize some asserts on aarch32 support
On 2 November 2018 at 12:32, Alex Bennée wrote: > > Richard Henderson writes: > >> When populating id registers from kvm, on a host that doesn't support >> aarch32 mode at all, neither arm_div nor jazelle will be supported either. >> >> Signed-off-by: Richard Henderson >> --- >> >> v2: Test aa64pfr.el0 >= 2; rename to isar_feature_aa64_aa32. >> Pull out realizefn test to no_aa32 bool; use it for jazelle as well. >> >> Alex, can you give this a test please? > > Reviewed-by: Alex Bennée > Tested-by: Alex Bennée Applied to target-arm.next, thanks. -- PMM
Re: [Qemu-devel] [PATCH v2] target/arm: Conditionalize some asserts on aarch32 support
Richard Henderson writes:
> When populating id registers from kvm, on a host that doesn't support
> aarch32 mode at all, neither arm_div nor jazelle will be supported either.
>
> Signed-off-by: Richard Henderson
> ---
>
> v2: Test aa64pfr.el0 >= 2; rename to isar_feature_aa64_aa32.
> Pull out realizefn test to no_aa32 bool; use it for jazelle as well.
>
> Alex, can you give this a test please?
Reviewed-by: Alex Bennée
Tested-by: Alex Bennée
>
>
> r~
>
> ---
> target/arm/cpu.h | 5 +
> target/arm/cpu.c | 15 +--
> 2 files changed, 18 insertions(+), 2 deletions(-)
>
> diff --git a/target/arm/cpu.h b/target/arm/cpu.h
> index 895f9909d8..5c2c77c31d 100644
> --- a/target/arm/cpu.h
> +++ b/target/arm/cpu.h
> @@ -3300,6 +3300,11 @@ static inline bool isar_feature_aa64_fp16(const
> ARMISARegisters *id)
> return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1;
> }
>
> +static inline bool isar_feature_aa64_aa32(const ARMISARegisters *id)
> +{
> +return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL0) >= 2;
> +}
> +
> static inline bool isar_feature_aa64_sve(const ARMISARegisters *id)
> {
> return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) != 0;
> diff --git a/target/arm/cpu.c b/target/arm/cpu.c
> index e08a2d2d79..d4dc0bc225 100644
> --- a/target/arm/cpu.c
> +++ b/target/arm/cpu.c
> @@ -774,6 +774,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error
> **errp)
> CPUARMState *env = >env;
> int pagebits;
> Error *local_err = NULL;
> +bool no_aa32 = false;
>
> /* If we needed to query the host kernel for the CPU features
> * then it's possible that might have failed in the initfn, but
> @@ -820,6 +821,16 @@ static void arm_cpu_realizefn(DeviceState *dev, Error
> **errp)
> set_feature(env, ARM_FEATURE_V7VE);
> }
> }
> +
> +/*
> + * There exist AArch64 cpus without AArch32 support. When KVM
> + * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN.
> + * Similarly, we cannot check ID_AA64PFR0 without AArch64 support.
> + */
> +if (arm_feature(>env, ARM_FEATURE_AARCH64)) {
> +no_aa32 = !cpu_isar_feature(aa64_aa32, cpu);
> +}
> +
> if (arm_feature(env, ARM_FEATURE_V7VE)) {
> /* v7 Virtualization Extensions. In real hardware this implies
> * EL2 and also the presence of the Security Extensions.
> @@ -829,7 +840,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error
> **errp)
> * Presence of EL2 itself is ARM_FEATURE_EL2, and of the
> * Security Extensions is ARM_FEATURE_EL3.
> */
> -assert(cpu_isar_feature(arm_div, cpu));
> +assert(no_aa32 || cpu_isar_feature(arm_div, cpu));
> set_feature(env, ARM_FEATURE_LPAE);
> set_feature(env, ARM_FEATURE_V7);
> }
> @@ -855,7 +866,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error
> **errp)
> if (arm_feature(env, ARM_FEATURE_V6)) {
> set_feature(env, ARM_FEATURE_V5);
> if (!arm_feature(env, ARM_FEATURE_M)) {
> -assert(cpu_isar_feature(jazelle, cpu));
> +assert(no_aa32 || cpu_isar_feature(jazelle, cpu));
> set_feature(env, ARM_FEATURE_AUXCR);
> }
> }
--
Alex Bennée
[Qemu-devel] [PATCH v2] target/arm: Conditionalize some asserts on aarch32 support
When populating id registers from kvm, on a host that doesn't support
aarch32 mode at all, neither arm_div nor jazelle will be supported either.
Signed-off-by: Richard Henderson
---
v2: Test aa64pfr.el0 >= 2; rename to isar_feature_aa64_aa32.
Pull out realizefn test to no_aa32 bool; use it for jazelle as well.
Alex, can you give this a test please?
r~
---
target/arm/cpu.h | 5 +
target/arm/cpu.c | 15 +--
2 files changed, 18 insertions(+), 2 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 895f9909d8..5c2c77c31d 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3300,6 +3300,11 @@ static inline bool isar_feature_aa64_fp16(const
ARMISARegisters *id)
return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1;
}
+static inline bool isar_feature_aa64_aa32(const ARMISARegisters *id)
+{
+return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL0) >= 2;
+}
+
static inline bool isar_feature_aa64_sve(const ARMISARegisters *id)
{
return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) != 0;
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index e08a2d2d79..d4dc0bc225 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -774,6 +774,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error
**errp)
CPUARMState *env = >env;
int pagebits;
Error *local_err = NULL;
+bool no_aa32 = false;
/* If we needed to query the host kernel for the CPU features
* then it's possible that might have failed in the initfn, but
@@ -820,6 +821,16 @@ static void arm_cpu_realizefn(DeviceState *dev, Error
**errp)
set_feature(env, ARM_FEATURE_V7VE);
}
}
+
+/*
+ * There exist AArch64 cpus without AArch32 support. When KVM
+ * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN.
+ * Similarly, we cannot check ID_AA64PFR0 without AArch64 support.
+ */
+if (arm_feature(>env, ARM_FEATURE_AARCH64)) {
+no_aa32 = !cpu_isar_feature(aa64_aa32, cpu);
+}
+
if (arm_feature(env, ARM_FEATURE_V7VE)) {
/* v7 Virtualization Extensions. In real hardware this implies
* EL2 and also the presence of the Security Extensions.
@@ -829,7 +840,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error
**errp)
* Presence of EL2 itself is ARM_FEATURE_EL2, and of the
* Security Extensions is ARM_FEATURE_EL3.
*/
-assert(cpu_isar_feature(arm_div, cpu));
+assert(no_aa32 || cpu_isar_feature(arm_div, cpu));
set_feature(env, ARM_FEATURE_LPAE);
set_feature(env, ARM_FEATURE_V7);
}
@@ -855,7 +866,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error
**errp)
if (arm_feature(env, ARM_FEATURE_V6)) {
set_feature(env, ARM_FEATURE_V5);
if (!arm_feature(env, ARM_FEATURE_M)) {
-assert(cpu_isar_feature(jazelle, cpu));
+assert(no_aa32 || cpu_isar_feature(jazelle, cpu));
set_feature(env, ARM_FEATURE_AUXCR);
}
}
--
2.17.2
