Re: [Qemu-devel] [PATCH v2 0/2] POWER9 TCG enablements - part6

2016-10-19 Thread David Gibson 
On Wed, Oct 19, 2016 at 11:36:45AM +0530, Nikunj A Dadhania wrote:
> This series contains 6 new instructions for POWER9 ISA3.0
>Vector Integer Negate 
>Vector Byte-Reverse
> 
> Patches:
> 02:
> vnegw: Vector Negate Word
> vnegd: Vector Negate Doubleword
> 03:
> xxbrh: VSX Vector Byte-Reverse Halfword
> xxbrw: VSX Vector Byte-Reverse Word
> xxbrd: VSX Vector Byte-Reverse Doubleword
> xxbrq: VSX Vector Byte-Reverse Quadword

Applied to ppc-for-2.8, thanks.

> 
> Changelog:
> v1:
> * Remove unused 'mask' in the define
> * Fix bug in xxbrq: should have used move as the last
>   translate operation instead of bswap.
> 
> v0:
> * Added temporary in xxbrq
> * Use negate directly in place for computing 2's compliment
> * Use int8_t instead for char
> * Dropped "VSX Scalar Compare" as fpu_helper needs change 
>   with regard to exception flag handling
> 
> Nikunj A Dadhania (2):
>   target-ppc: implement vnegw/d instructions
>   target-ppc: implement xxbr[qdwh] instruction
> 
>  target-ppc/helper.h |  2 +
>  target-ppc/int_helper.c | 12 ++
>  target-ppc/translate.c  | 32 +++
>  target-ppc/translate/vmx-impl.inc.c |  2 +
>  target-ppc/translate/vmx-ops.inc.c  |  2 +
>  target-ppc/translate/vsx-impl.inc.c | 77 
> +
>  target-ppc/translate/vsx-ops.inc.c  |  8 
>  7 files changed, 135 insertions(+)
> 

-- 
David Gibson| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au  | minimalist, thank you.  NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson


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Re: [Qemu-devel] [PATCH v2 0/2] POWER9 TCG enablements - part6

2016-10-18 Thread no-reply 
Hi,

Your series seems to have some coding style problems. See output below for
more information:

Type: series
Message-id: 1476857207-10091-1-git-send-email-nik...@linux.vnet.ibm.com
Subject: [Qemu-devel] [PATCH v2 0/2] POWER9 TCG enablements - part6

=== TEST SCRIPT BEGIN ===
#!/bin/bash

BASE=base
n=1
total=$(git log --oneline $BASE.. | wc -l)
failed=0

# Useful git options
git config --local diff.renamelimit 0
git config --local diff.renames True

commits="$(git log --format=%H --reverse $BASE..)"
for c in $commits; do
echo "Checking PATCH $n/$total: $(git show --no-patch --format=%s $c)..."
if ! git show $c --format=email | ./scripts/checkpatch.pl --mailback -; then
failed=1
echo
fi
n=$((n+1))
done

exit $failed
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
Switched to a new branch 'test'
1854ac2 target-ppc: implement xxbr[qdwh] instruction
39ffa81 target-ppc: implement vnegw/d instructions

=== OUTPUT BEGIN ===
Checking PATCH 1/2: target-ppc: implement vnegw/d instructions...
Checking PATCH 2/2: target-ppc: implement xxbr[qdwh] instruction...
ERROR: Macros with complex values should be enclosed in parenthesis
#176: FILE: target-ppc/translate/vsx-ops.inc.c:42:
+#define GEN_XX2FORM_EO(name, opc2, opc3, opc4, fl2)  \
+GEN_HANDLER2_E_2(name, #name, 0x3C, opc2 | 0, opc3, opc4, 0, PPC_NONE, fl2), \
+GEN_HANDLER2_E_2(name, #name, 0x3C, opc2 | 1, opc3, opc4, 0, PPC_NONE, fl2)

total: 1 errors, 0 warnings, 159 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

=== OUTPUT END ===

Test command exited with code: 1


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[Qemu-devel] [PATCH v2 0/2] POWER9 TCG enablements - part6

2016-10-18 Thread Nikunj A Dadhania 
This series contains 6 new instructions for POWER9 ISA3.0
   Vector Integer Negate 
   Vector Byte-Reverse

Patches:
02:
vnegw: Vector Negate Word
vnegd: Vector Negate Doubleword
03:
xxbrh: VSX Vector Byte-Reverse Halfword
xxbrw: VSX Vector Byte-Reverse Word
xxbrd: VSX Vector Byte-Reverse Doubleword
xxbrq: VSX Vector Byte-Reverse Quadword

Changelog:
v1:
* Remove unused 'mask' in the define
* Fix bug in xxbrq: should have used move as the last
  translate operation instead of bswap.

v0:
* Added temporary in xxbrq
* Use negate directly in place for computing 2's compliment
* Use int8_t instead for char
* Dropped "VSX Scalar Compare" as fpu_helper needs change 
  with regard to exception flag handling

Nikunj A Dadhania (2):
  target-ppc: implement vnegw/d instructions
  target-ppc: implement xxbr[qdwh] instruction

 target-ppc/helper.h |  2 +
 target-ppc/int_helper.c | 12 ++
 target-ppc/translate.c  | 32 +++
 target-ppc/translate/vmx-impl.inc.c |  2 +
 target-ppc/translate/vmx-ops.inc.c  |  2 +
 target-ppc/translate/vsx-impl.inc.c | 77 +
 target-ppc/translate/vsx-ops.inc.c  |  8 
 7 files changed, 135 insertions(+)

-- 
2.7.4