Re: [Qemu-devel] [PATCH v3 26/32] ahci: MSI capability should be at 0x80, not 0x50.

2014-08-14 Thread Michael S. Tsirkin
On Wed, Aug 13, 2014 at 05:56:09PM -0400, John Snow wrote: In the Intel ICH9 data sheet, the MSI capability offset in the PCI configuration space for ICH9 AHCI devices is specified to be 0x80. Further, the PCI capability pointer should always point to 0x80 in ICH9 devices, despite the fact

Re: [Qemu-devel] [PATCH v3 26/32] ahci: MSI capability should be at 0x80, not 0x50.

2014-08-14 Thread Michael S. Tsirkin
On Wed, Aug 13, 2014 at 05:56:09PM -0400, John Snow wrote: In the Intel ICH9 data sheet, the MSI capability offset in the PCI configuration space for ICH9 AHCI devices is specified to be 0x80. Further, the PCI capability pointer should always point to 0x80 in ICH9 devices, despite the fact

[Qemu-devel] [PATCH v3 26/32] ahci: MSI capability should be at 0x80, not 0x50.

2014-08-13 Thread John Snow
In the Intel ICH9 data sheet, the MSI capability offset in the PCI configuration space for ICH9 AHCI devices is specified to be 0x80. Further, the PCI capability pointer should always point to 0x80 in ICH9 devices, despite the fact that AHCI 1.3 specifies that it should be pointing to PMCAP