On Fri, Jun 08, 2018 at 11:46:55AM +0200, Greg Kurz wrote:
> From: luporl
>
> According to PowerISA, the PIR register should be readable in privileged
> mode also, not only in hypervisor privileged mode.
>
> PowerISA 3.0 - 4.3.3 Processor Identification Register
>
> "Read access to the PIR is
From: luporl
According to PowerISA, the PIR register should be readable in privileged
mode also, not only in hypervisor privileged mode.
PowerISA 3.0 - 4.3.3 Processor Identification Register
"Read access to the PIR is privileged; write access is not provided."
Figure 18 in section 4.4.4
