Re: [Qemu-devel] [PATCH v8 23/23] RISC-V Build Infrastructure
On 03/02/2018 02:51 PM, Michael Clark wrote: > This adds RISC-V into the build system enabling the following targets: > > - riscv32-softmmu > - riscv64-softmmu > - riscv32-linux-user > - riscv64-linux-user > > This adds defaults configs for RISC-V, enables the build for the RISC-V > CPU core, hardware, and Linux User Emulation. The 'qemu-binfmt-conf.sh' > script is updated to add the RISC-V ELF magic. > > Expected checkpatch errors for consistency reasons: > > ERROR: line over 90 characters > FILE: scripts/qemu-binfmt-conf.sh > > Reviewed-by: Richard Henderson > Signed-off-by: Sagar Karandikar > Signed-off-by: Michael Clark > --- > arch_init.c| 2 ++ > configure | 13 + > cpus.c | 6 ++ > default-configs/riscv32-linux-user.mak | 1 + > default-configs/riscv32-softmmu.mak| 4 > default-configs/riscv64-linux-user.mak | 1 + > default-configs/riscv64-softmmu.mak| 4 > hw/riscv/Makefile.objs | 11 +++ > include/sysemu/arch_init.h | 1 + > qapi-schema.json | 17 - > scripts/qemu-binfmt-conf.sh| 13 - > target/riscv/Makefile.objs | 1 + > 12 files changed, 72 insertions(+), 2 deletions(-) > create mode 100644 default-configs/riscv32-linux-user.mak > create mode 100644 default-configs/riscv32-softmmu.mak > create mode 100644 default-configs/riscv64-linux-user.mak > create mode 100644 default-configs/riscv64-softmmu.mak > create mode 100644 hw/riscv/Makefile.objs > create mode 100644 target/riscv/Makefile.objs > > diff --git a/arch_init.c b/arch_init.c > index 4c36f2b..e157619 100644 > --- a/arch_init.c > +++ b/arch_init.c > @@ -71,6 +71,8 @@ int graphic_depth = 32; > #define QEMU_ARCH QEMU_ARCH_OPENRISC > #elif defined(TARGET_PPC) > #define QEMU_ARCH QEMU_ARCH_PPC > +#elif defined(TARGET_RISCV) > +#define QEMU_ARCH QEMU_ARCH_RISCV > #elif defined(TARGET_S390X) > #define QEMU_ARCH QEMU_ARCH_S390X > #elif defined(TARGET_SH4) > diff --git a/configure b/configure > index 00c4b63..a3240a8 100755 > --- a/configure > +++ b/configure > @@ -6801,6 +6801,16 @@ case "$target_name" in > echo "TARGET_ABI32=y" >> $config_target_mak > gdb_xml_files="power64-core.xml power-fpu.xml power-altivec.xml > power-spe.xml power-vsx.xml" >;; > + riscv32) > +TARGET_BASE_ARCH=riscv > +TARGET_ABI_DIR=riscv > +mttcg=yes > + ;; > + riscv64) > +TARGET_BASE_ARCH=riscv > +TARGET_ABI_DIR=riscv > +mttcg=yes > + ;; >sh4|sh4eb) > TARGET_ARCH=sh4 > bflt="yes" > @@ -6970,6 +6980,9 @@ for i in $ARCH $TARGET_BASE_ARCH ; do >ppc*) > disas_config "PPC" >;; > + riscv) > +disas_config "RISCV" > + ;; >s390*) > disas_config "S390" >;; > diff --git a/cpus.c b/cpus.c > index af67826..407c3f8 100644 > --- a/cpus.c > +++ b/cpus.c > @@ -2094,6 +2094,9 @@ CpuInfoList *qmp_query_cpus(Error **errp) > #elif defined(TARGET_SPARC) > SPARCCPU *sparc_cpu = SPARC_CPU(cpu); > CPUSPARCState *env = &sparc_cpu->env; > +#elif defined(TARGET_RISCV) > +RISCVCPU *riscv_cpu = RISCV_CPU(cpu); > +CPURISCVState *env = &riscv_cpu->env; > #elif defined(TARGET_MIPS) > MIPSCPU *mips_cpu = MIPS_CPU(cpu); > CPUMIPSState *env = &mips_cpu->env; > @@ -2133,6 +2136,9 @@ CpuInfoList *qmp_query_cpus(Error **errp) > #elif defined(TARGET_S390X) > info->value->arch = CPU_INFO_ARCH_S390; > info->value->u.s390.cpu_state = env->cpu_state; > +#elif defined(TARGET_RISCV) > +info->value->arch = CPU_INFO_ARCH_RISCV; > +info->value->u.riscv.pc = env->pc; > #else > info->value->arch = CPU_INFO_ARCH_OTHER; > #endif > diff --git a/default-configs/riscv32-linux-user.mak > b/default-configs/riscv32-linux-user.mak > new file mode 100644 > index 000..865b362 > --- /dev/null > +++ b/default-configs/riscv32-linux-user.mak > @@ -0,0 +1 @@ > +# Default configuration for riscv-linux-user > diff --git a/default-configs/riscv32-softmmu.mak > b/default-configs/riscv32-softmmu.mak > new file mode 100644 > index 000..f9e7421 > --- /dev/null > +++ b/default-configs/riscv32-softmmu.mak > @@ -0,0 +1,4 @@ > +# Default configuration for riscv-softmmu > + > +CONFIG_SERIAL=y > +CONFIG_VIRTIO=y > diff --git a/default-configs/riscv64-linux-user.mak > b/default-configs/riscv64-linux-user.mak > new file mode 100644 > index 000..865b362 > --- /dev/null > +++ b/default-configs/riscv64-linux-user.mak > @@ -0,0 +1 @@ > +# Default configuration for riscv-linux-user > diff --git a/default-configs/riscv64-softmmu.mak > b/default-configs/riscv64-softmmu.mak > new file mode 100644 > index 000..f9e7421 > --- /dev/null > +++ b/default-configs/riscv64-softmmu.mak > @@ -0,0 +1,4 @@ > +# Default configuration for riscv-softmmu > + > +CONFIG_SERIAL=y > +CONFIG_VIRTIO=y > diff --git a/hw
Re: [Qemu-devel] [PATCH v8 23/23] RISC-V Build Infrastructure
On 03/02/2018 08:37 PM, Michael Clark wrote: Let me know if you have a branch for me to pull and rebase against. http://repo.or.cz/qemu/ericb.git qapi But that has landed in master now. We are passing all build and make check tests in travis (except for a couple of build timeouts because we are hitting the default 50 minute timeout) https://travis-ci.org/riscv/riscv-qemu/builds/348234736 Also, top-posting makes it a bit harder to see what you are replying to. qapi-schema.json | 17 - Will need rebasing to modify qapi/misc.json if my pending PULL request issues get resolved first: https://lists.gnu.org/archive/html/qemu-devel/2018-03/msg00469.html -- Eric Blake, Principal Software Engineer Red Hat, Inc. +1-919-301-3266 Virtualization: qemu.org | libvirt.org
Re: [Qemu-devel] [PATCH v8 23/23] RISC-V Build Infrastructure
Let me know if you have a branch for me to pull and rebase against. We are passing all build and make check tests in travis (except for a couple of build timeouts because we are hitting the default 50 minute timeout) https://travis-ci.org/riscv/riscv-qemu/builds/348234736 On Sat, Mar 3, 2018 at 3:33 AM, Eric Blake wrote: > On 03/02/2018 07:51 AM, Michael Clark wrote: > >> This adds RISC-V into the build system enabling the following targets: >> >> - riscv32-softmmu >> - riscv64-softmmu >> - riscv32-linux-user >> - riscv64-linux-user >> >> This adds defaults configs for RISC-V, enables the build for the RISC-V >> CPU core, hardware, and Linux User Emulation. The 'qemu-binfmt-conf.sh' >> script is updated to add the RISC-V ELF magic. >> >> Expected checkpatch errors for consistency reasons: >> >> ERROR: line over 90 characters >> FILE: scripts/qemu-binfmt-conf.sh >> >> Reviewed-by: Richard Henderson >> Signed-off-by: Sagar Karandikar >> Signed-off-by: Michael Clark >> --- >> arch_init.c| 2 ++ >> configure | 13 + >> cpus.c | 6 ++ >> default-configs/riscv32-linux-user.mak | 1 + >> default-configs/riscv32-softmmu.mak| 4 >> default-configs/riscv64-linux-user.mak | 1 + >> default-configs/riscv64-softmmu.mak| 4 >> hw/riscv/Makefile.objs | 11 +++ >> include/sysemu/arch_init.h | 1 + >> qapi-schema.json | 17 - >> > > Will need rebasing to modify qapi/misc.json if my pending PULL request > issues get resolved first: > > https://lists.gnu.org/archive/html/qemu-devel/2018-03/msg00469.html > > -- > Eric Blake, Principal Software Engineer > Red Hat, Inc. +1-919-301-3266 > Virtualization: qemu.org | libvirt.org >
Re: [Qemu-devel] [PATCH v8 23/23] RISC-V Build Infrastructure
On 03/02/2018 07:51 AM, Michael Clark wrote: This adds RISC-V into the build system enabling the following targets: - riscv32-softmmu - riscv64-softmmu - riscv32-linux-user - riscv64-linux-user This adds defaults configs for RISC-V, enables the build for the RISC-V CPU core, hardware, and Linux User Emulation. The 'qemu-binfmt-conf.sh' script is updated to add the RISC-V ELF magic. Expected checkpatch errors for consistency reasons: ERROR: line over 90 characters FILE: scripts/qemu-binfmt-conf.sh Reviewed-by: Richard Henderson Signed-off-by: Sagar Karandikar Signed-off-by: Michael Clark --- arch_init.c| 2 ++ configure | 13 + cpus.c | 6 ++ default-configs/riscv32-linux-user.mak | 1 + default-configs/riscv32-softmmu.mak| 4 default-configs/riscv64-linux-user.mak | 1 + default-configs/riscv64-softmmu.mak| 4 hw/riscv/Makefile.objs | 11 +++ include/sysemu/arch_init.h | 1 + qapi-schema.json | 17 - Will need rebasing to modify qapi/misc.json if my pending PULL request issues get resolved first: https://lists.gnu.org/archive/html/qemu-devel/2018-03/msg00469.html -- Eric Blake, Principal Software Engineer Red Hat, Inc. +1-919-301-3266 Virtualization: qemu.org | libvirt.org
[Qemu-devel] [PATCH v8 23/23] RISC-V Build Infrastructure
This adds RISC-V into the build system enabling the following targets: - riscv32-softmmu - riscv64-softmmu - riscv32-linux-user - riscv64-linux-user This adds defaults configs for RISC-V, enables the build for the RISC-V CPU core, hardware, and Linux User Emulation. The 'qemu-binfmt-conf.sh' script is updated to add the RISC-V ELF magic. Expected checkpatch errors for consistency reasons: ERROR: line over 90 characters FILE: scripts/qemu-binfmt-conf.sh Reviewed-by: Richard Henderson Signed-off-by: Sagar Karandikar Signed-off-by: Michael Clark --- arch_init.c| 2 ++ configure | 13 + cpus.c | 6 ++ default-configs/riscv32-linux-user.mak | 1 + default-configs/riscv32-softmmu.mak| 4 default-configs/riscv64-linux-user.mak | 1 + default-configs/riscv64-softmmu.mak| 4 hw/riscv/Makefile.objs | 11 +++ include/sysemu/arch_init.h | 1 + qapi-schema.json | 17 - scripts/qemu-binfmt-conf.sh| 13 - target/riscv/Makefile.objs | 1 + 12 files changed, 72 insertions(+), 2 deletions(-) create mode 100644 default-configs/riscv32-linux-user.mak create mode 100644 default-configs/riscv32-softmmu.mak create mode 100644 default-configs/riscv64-linux-user.mak create mode 100644 default-configs/riscv64-softmmu.mak create mode 100644 hw/riscv/Makefile.objs create mode 100644 target/riscv/Makefile.objs diff --git a/arch_init.c b/arch_init.c index 4c36f2b..e157619 100644 --- a/arch_init.c +++ b/arch_init.c @@ -71,6 +71,8 @@ int graphic_depth = 32; #define QEMU_ARCH QEMU_ARCH_OPENRISC #elif defined(TARGET_PPC) #define QEMU_ARCH QEMU_ARCH_PPC +#elif defined(TARGET_RISCV) +#define QEMU_ARCH QEMU_ARCH_RISCV #elif defined(TARGET_S390X) #define QEMU_ARCH QEMU_ARCH_S390X #elif defined(TARGET_SH4) diff --git a/configure b/configure index 00c4b63..a3240a8 100755 --- a/configure +++ b/configure @@ -6801,6 +6801,16 @@ case "$target_name" in echo "TARGET_ABI32=y" >> $config_target_mak gdb_xml_files="power64-core.xml power-fpu.xml power-altivec.xml power-spe.xml power-vsx.xml" ;; + riscv32) +TARGET_BASE_ARCH=riscv +TARGET_ABI_DIR=riscv +mttcg=yes + ;; + riscv64) +TARGET_BASE_ARCH=riscv +TARGET_ABI_DIR=riscv +mttcg=yes + ;; sh4|sh4eb) TARGET_ARCH=sh4 bflt="yes" @@ -6970,6 +6980,9 @@ for i in $ARCH $TARGET_BASE_ARCH ; do ppc*) disas_config "PPC" ;; + riscv) +disas_config "RISCV" + ;; s390*) disas_config "S390" ;; diff --git a/cpus.c b/cpus.c index af67826..407c3f8 100644 --- a/cpus.c +++ b/cpus.c @@ -2094,6 +2094,9 @@ CpuInfoList *qmp_query_cpus(Error **errp) #elif defined(TARGET_SPARC) SPARCCPU *sparc_cpu = SPARC_CPU(cpu); CPUSPARCState *env = &sparc_cpu->env; +#elif defined(TARGET_RISCV) +RISCVCPU *riscv_cpu = RISCV_CPU(cpu); +CPURISCVState *env = &riscv_cpu->env; #elif defined(TARGET_MIPS) MIPSCPU *mips_cpu = MIPS_CPU(cpu); CPUMIPSState *env = &mips_cpu->env; @@ -2133,6 +2136,9 @@ CpuInfoList *qmp_query_cpus(Error **errp) #elif defined(TARGET_S390X) info->value->arch = CPU_INFO_ARCH_S390; info->value->u.s390.cpu_state = env->cpu_state; +#elif defined(TARGET_RISCV) +info->value->arch = CPU_INFO_ARCH_RISCV; +info->value->u.riscv.pc = env->pc; #else info->value->arch = CPU_INFO_ARCH_OTHER; #endif diff --git a/default-configs/riscv32-linux-user.mak b/default-configs/riscv32-linux-user.mak new file mode 100644 index 000..865b362 --- /dev/null +++ b/default-configs/riscv32-linux-user.mak @@ -0,0 +1 @@ +# Default configuration for riscv-linux-user diff --git a/default-configs/riscv32-softmmu.mak b/default-configs/riscv32-softmmu.mak new file mode 100644 index 000..f9e7421 --- /dev/null +++ b/default-configs/riscv32-softmmu.mak @@ -0,0 +1,4 @@ +# Default configuration for riscv-softmmu + +CONFIG_SERIAL=y +CONFIG_VIRTIO=y diff --git a/default-configs/riscv64-linux-user.mak b/default-configs/riscv64-linux-user.mak new file mode 100644 index 000..865b362 --- /dev/null +++ b/default-configs/riscv64-linux-user.mak @@ -0,0 +1 @@ +# Default configuration for riscv-linux-user diff --git a/default-configs/riscv64-softmmu.mak b/default-configs/riscv64-softmmu.mak new file mode 100644 index 000..f9e7421 --- /dev/null +++ b/default-configs/riscv64-softmmu.mak @@ -0,0 +1,4 @@ +# Default configuration for riscv-softmmu + +CONFIG_SERIAL=y +CONFIG_VIRTIO=y diff --git a/hw/riscv/Makefile.objs b/hw/riscv/Makefile.objs new file mode 100644 index 000..1dde01d --- /dev/null +++ b/hw/riscv/Makefile.objs @@ -0,0 +1,11 @@ +obj-y += riscv_htif.o +obj-y += riscv_hart.o +obj-y += sifive_e.o +obj-y += sifive_clint.o +obj-y += sifive_prci.o +obj-y += sifive_plic.o +obj-y += sifive_test.o +obj-y += sifive_u.o +obj-y