Re: [Qemu-devel] [v2 02/13] Add lxsdx

2013-10-22 Thread Paolo Bonzini 
Il 11/10/2013 13:57, Tom Musta ha scritto:
 This patch adds the Load VSX Scalar Doubleowrd Indexed (lxsdx)
 instruction.
 
 The lower 8 bytes of the target register are undefined; this
 implementation leaves those bytes unaltered.
 
 Signed-off-by: Tom Musta tommu...@gmail.com
 ---
  target-ppc/translate.c |   16 
  1 files changed, 16 insertions(+), 0 deletions(-)
 
 diff --git a/target-ppc/translate.c b/target-ppc/translate.c
 index bd5e89d..6ee0d80 100644
 --- a/target-ppc/translate.c
 +++ b/target-ppc/translate.c
 @@ -7007,6 +7007,21 @@ static inline TCGv_i64 cpu_vsrl(int n)
  }
  }
 
 +static void gen_lxsdx(DisasContext *ctx)
 +{
 +TCGv EA;
 +if (unlikely(!ctx-vsx_enabled)) {
 +gen_exception(ctx, POWERPC_EXCP_VSXU);
 +return;
 +}
 +gen_set_access_type(ctx, ACCESS_INT);
 +EA = tcg_temp_new();
 +gen_addr_reg_index(ctx, EA);
 +gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx-opcode)), EA);
 +/* NOTE: cpu_vsrl is undefined */
 +tcg_temp_free(EA);
 +}
 +
  static void gen_lxvd2x(DisasContext *ctx)
  {
  TCGv EA;
 @@ -9518,6 +9533,7 @@ GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20),
  GEN_VAFORM_PAIRED(vsel, vperm, 21),
  GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
 
 +GEN_HANDLER_E(lxsdx, 0x1F, 0x0C, 0x12, 0, PPC_NONE, PPC2_VSX),
  GEN_HANDLER_E(lxvd2x, 0x1F, 0x0C, 0x1A, 0, PPC_NONE, PPC2_VSX),
 
  GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX),

Reviewed-by: Paolo Bonzini pbonz...@redhat.com

[Qemu-devel] [v2 02/13] Add lxsdx

2013-10-11 Thread Tom Musta 

This patch adds the Load VSX Scalar Doubleowrd Indexed (lxsdx)
instruction.

The lower 8 bytes of the target register are undefined; this
implementation leaves those bytes unaltered.

Signed-off-by: Tom Musta tommu...@gmail.com
---
 target-ppc/translate.c |   16 
 1 files changed, 16 insertions(+), 0 deletions(-)

diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index bd5e89d..6ee0d80 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7007,6 +7007,21 @@ static inline TCGv_i64 cpu_vsrl(int n)
 }
 }

+static void gen_lxsdx(DisasContext *ctx)
+{
+TCGv EA;
+if (unlikely(!ctx-vsx_enabled)) {
+gen_exception(ctx, POWERPC_EXCP_VSXU);
+return;
+}
+gen_set_access_type(ctx, ACCESS_INT);
+EA = tcg_temp_new();
+gen_addr_reg_index(ctx, EA);
+gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx-opcode)), EA);
+/* NOTE: cpu_vsrl is undefined */
+tcg_temp_free(EA);
+}
+
 static void gen_lxvd2x(DisasContext *ctx)
 {
 TCGv EA;
@@ -9518,6 +9533,7 @@ GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20),
 GEN_VAFORM_PAIRED(vsel, vperm, 21),
 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),

+GEN_HANDLER_E(lxsdx, 0x1F, 0x0C, 0x12, 0, PPC_NONE, PPC2_VSX),
 GEN_HANDLER_E(lxvd2x, 0x1F, 0x0C, 0x1A, 0, PPC_NONE, PPC2_VSX),

 GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX),
--
1.7.1