[Qemu-devel] Re: [PATCH 2/3] target-ppc: fix default qNaN

2011-01-06 Thread Aurelien Jarno
On Wed, Jan 05, 2011 at 06:09:34PM +0100, Alexander Graf wrote:
> 
> On 02.01.2011, at 15:39, Aurelien Jarno wrote:
> 
> > On PPC the default qNaN doesn't have the sign bit set.
> 
> The spec says "don't care" for the sign bit. Did you extract the value 
> empirically? I'm not saying it's wrong - the default 32 Bit value seems to be 
> 0x7FC0_ (2.06 ISA 6.6.2.2).

"don't care" is for detecting a qNaN which can be represented by
thousands of different values. It's different from the default qNaN.

2.06 ISA 6.6.2.2 is for vector operations, which are always 32-bit. We 
are also using this value, this time through softfloat-specialize.h 
(look at float32_default_nan).

For 64-bit values, the default value is defined in 4.3. For the long
term, we should remove the default qNaN value from
target-ppc/op_helper.c and only use the one in softfloat-specialize.h.
However it needs reworking of part of the softfloat library first.

> Hrm ... reading section 5.4.2:
> 
> A special QNaN is sometimes supplied as the default QNaN for a disabled 
> invalid-operation exception; it has a plus sign, the leftmost 6 bits of the 
> combination field set to 0b10 and remaining bits in the combination field 
> and the trailing significand field set to zero.
> 

That's for decimal floating point, and not binary floating point,
however it seems they use the same convention.

Thanks for the review.

-- 
Aurelien Jarno  GPG: 1024D/F1BCDB73
[email protected] http://www.aurel32.net



[Qemu-devel] Re: [PATCH 2/3] target-ppc: fix default qNaN

2011-01-05 Thread Alexander Graf

On 02.01.2011, at 15:39, Aurelien Jarno wrote:

> On PPC the default qNaN doesn't have the sign bit set.

The spec says "don't care" for the sign bit. Did you extract the value 
empirically? I'm not saying it's wrong - the default 32 Bit value seems to be 
0x7FC0_ (2.06 ISA 6.6.2.2).

Hrm ... reading section 5.4.2:

A special QNaN is sometimes supplied as the default QNaN for a disabled 
invalid-operation exception; it has a plus sign, the leftmost 6 bits of the 
combination field set to 0b10 and remaining bits in the combination field 
and the trailing significand field set to zero.

So I guess you're right.


Acked-by: Alexander Graf 


Alex