Re: [RFC PATCH v2 16/30] hw/loongarch: Add a virt LoongArch 3A5000 board support
On 11/11/2021 01:35, Xiaojuan Yang wrote:
LoongArch is a new RISC ISA, support 32bit mode
or 64bit mode. Now we only add 64bit support.
More detailed info you can see
https://github.com/loongson/LoongArch-Documentation
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
.../devices/loongarch64-softmmu/default.mak | 3 +
configs/targets/loongarch64-softmmu.mak | 3 +
hw/Kconfig| 1 +
hw/loongarch/Kconfig | 3 +
hw/loongarch/ls3a5000_virt.c | 210 ++
hw/loongarch/meson.build | 4 +
hw/meson.build| 1 +
include/exec/poison.h | 2 +
include/hw/loongarch/loongarch.h | 46
include/sysemu/arch_init.h| 1 +
qapi/machine.json | 2 +-
target/Kconfig| 1 +
target/loongarch/Kconfig | 2 +
target/loongarch/cpu.c| 8 +
target/loongarch/cpu.h| 4 +
15 files changed, 290 insertions(+), 1 deletion(-)
create mode 100644 configs/devices/loongarch64-softmmu/default.mak
create mode 100644 hw/loongarch/Kconfig
create mode 100644 hw/loongarch/ls3a5000_virt.c
create mode 100644 hw/loongarch/meson.build
create mode 100644 include/hw/loongarch/loongarch.h
create mode 100644 target/loongarch/Kconfig
diff --git a/configs/devices/loongarch64-softmmu/default.mak
b/configs/devices/loongarch64-softmmu/default.mak
new file mode 100644
index 00..a6705b9e4a
--- /dev/null
+++ b/configs/devices/loongarch64-softmmu/default.mak
@@ -0,0 +1,3 @@
+# Default configuration for loongarch64-softmmu
+
+CONFIG_LOONGSON_3A5000=y
diff --git a/configs/targets/loongarch64-softmmu.mak
b/configs/targets/loongarch64-softmmu.mak
index f33fa1590b..7bc06c850c 100644
--- a/configs/targets/loongarch64-softmmu.mak
+++ b/configs/targets/loongarch64-softmmu.mak
@@ -1 +1,4 @@
+TARGET_ARCH=loongarch64
+TARGET_BASE_ARCH=loongarch
+TARGET_SUPPORTS_MTTCG=y
TARGET_XML_FILES= gdb-xml/loongarch-base64.xml gdb-xml/loongarch-fpu64.xml
diff --git a/hw/Kconfig b/hw/Kconfig
index ad20cce0a9..f71b2155ed 100644
--- a/hw/Kconfig
+++ b/hw/Kconfig
@@ -49,6 +49,7 @@ source avr/Kconfig
source cris/Kconfig
source hppa/Kconfig
source i386/Kconfig
+source loongarch/Kconfig
source m68k/Kconfig
source microblaze/Kconfig
source mips/Kconfig
diff --git a/hw/loongarch/Kconfig b/hw/loongarch/Kconfig
new file mode 100644
index 00..720822f32c
--- /dev/null
+++ b/hw/loongarch/Kconfig
@@ -0,0 +1,3 @@
+config LOONGSON_3A5000
+bool
+select PCI_EXPRESS_7A
diff --git a/hw/loongarch/ls3a5000_virt.c b/hw/loongarch/ls3a5000_virt.c
new file mode 100644
index 00..7c88d64795
--- /dev/null
+++ b/hw/loongarch/ls3a5000_virt.c
@@ -0,0 +1,210 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * QEMU loongson 3a5000 develop board emulation
+ *
+ * Copyright (c) 2021 Loongson Technology Corporation Limited
+ */
+#include "qemu/osdep.h"
+#include "qemu-common.h"
+#include "qemu/units.h"
+#include "qemu/datadir.h"
+#include "qapi/error.h"
+#include "hw/boards.h"
+#include "sysemu/sysemu.h"
+#include "sysemu/qtest.h"
+#include "sysemu/runstate.h"
+#include "sysemu/reset.h"
+#include "hw/loongarch/loongarch.h"
+#include "hw/pci-host/ls7a.h"
+
+CPULoongArchState *cpu_states[LOONGARCH_MAX_VCPUS];
This doesn't look right - shouldn't this be in LoongArchMachineState?
+static void main_cpu_reset(void *opaque)
+{
+LoongArchCPU *cpu = opaque;
+
+cpu_reset(CPU(cpu));
+}
+
+static uint64_t loongarch_pm_mem_read(void *opaque, hwaddr addr, unsigned size)
+{
+return 0;
+}
+
+static void loongarch_pm_mem_write(void *opaque, hwaddr addr,
+ uint64_t val, unsigned size)
+{
+
+if (addr != PM_CNT_MODE) {
+return;
+}
+
+switch (val) {
+case 0x00:
+qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
+return;
+case 0xff:
+qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
+return;
+default:
+return;
+}
+}
+
+static const MemoryRegionOps loongarch_pm_ops = {
+.read = loongarch_pm_mem_read,
+.write = loongarch_pm_mem_write,
+.endianness = DEVICE_NATIVE_ENDIAN,
This should likely be DEVICE_LITTLE_ENDIAN or DEVICE_BIG_ENDIAN.
+};
+
+#define LOONGARCH_SIMPLE_MMIO_OPS(ADDR, NAME, SIZE) \
+({\
+ MemoryRegion *iomem = g_new(MemoryRegion, 1);\
+ memory_region_init_io(iomem, NULL, _qemu_ops,\
+ (void *)ADDR, NAME, SIZE);\
+ memory_region_add_subregion(lams->system_iocsr, ADDR, iomem);\
+})
+
+static void loongarch_qemu_write(void *opaque, hwaddr addr,
+ uint64_t val, unsigned size)
+{
+}
+
+static uint64_t loongarch_qemu_read(void *opaque, hwaddr addr, unsigned size)
[RFC PATCH v2 16/30] hw/loongarch: Add a virt LoongArch 3A5000 board support
LoongArch is a new RISC ISA, support 32bit mode
or 64bit mode. Now we only add 64bit support.
More detailed info you can see
https://github.com/loongson/LoongArch-Documentation
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
.../devices/loongarch64-softmmu/default.mak | 3 +
configs/targets/loongarch64-softmmu.mak | 3 +
hw/Kconfig| 1 +
hw/loongarch/Kconfig | 3 +
hw/loongarch/ls3a5000_virt.c | 210 ++
hw/loongarch/meson.build | 4 +
hw/meson.build| 1 +
include/exec/poison.h | 2 +
include/hw/loongarch/loongarch.h | 46
include/sysemu/arch_init.h| 1 +
qapi/machine.json | 2 +-
target/Kconfig| 1 +
target/loongarch/Kconfig | 2 +
target/loongarch/cpu.c| 8 +
target/loongarch/cpu.h| 4 +
15 files changed, 290 insertions(+), 1 deletion(-)
create mode 100644 configs/devices/loongarch64-softmmu/default.mak
create mode 100644 hw/loongarch/Kconfig
create mode 100644 hw/loongarch/ls3a5000_virt.c
create mode 100644 hw/loongarch/meson.build
create mode 100644 include/hw/loongarch/loongarch.h
create mode 100644 target/loongarch/Kconfig
diff --git a/configs/devices/loongarch64-softmmu/default.mak
b/configs/devices/loongarch64-softmmu/default.mak
new file mode 100644
index 00..a6705b9e4a
--- /dev/null
+++ b/configs/devices/loongarch64-softmmu/default.mak
@@ -0,0 +1,3 @@
+# Default configuration for loongarch64-softmmu
+
+CONFIG_LOONGSON_3A5000=y
diff --git a/configs/targets/loongarch64-softmmu.mak
b/configs/targets/loongarch64-softmmu.mak
index f33fa1590b..7bc06c850c 100644
--- a/configs/targets/loongarch64-softmmu.mak
+++ b/configs/targets/loongarch64-softmmu.mak
@@ -1 +1,4 @@
+TARGET_ARCH=loongarch64
+TARGET_BASE_ARCH=loongarch
+TARGET_SUPPORTS_MTTCG=y
TARGET_XML_FILES= gdb-xml/loongarch-base64.xml gdb-xml/loongarch-fpu64.xml
diff --git a/hw/Kconfig b/hw/Kconfig
index ad20cce0a9..f71b2155ed 100644
--- a/hw/Kconfig
+++ b/hw/Kconfig
@@ -49,6 +49,7 @@ source avr/Kconfig
source cris/Kconfig
source hppa/Kconfig
source i386/Kconfig
+source loongarch/Kconfig
source m68k/Kconfig
source microblaze/Kconfig
source mips/Kconfig
diff --git a/hw/loongarch/Kconfig b/hw/loongarch/Kconfig
new file mode 100644
index 00..720822f32c
--- /dev/null
+++ b/hw/loongarch/Kconfig
@@ -0,0 +1,3 @@
+config LOONGSON_3A5000
+bool
+select PCI_EXPRESS_7A
diff --git a/hw/loongarch/ls3a5000_virt.c b/hw/loongarch/ls3a5000_virt.c
new file mode 100644
index 00..7c88d64795
--- /dev/null
+++ b/hw/loongarch/ls3a5000_virt.c
@@ -0,0 +1,210 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * QEMU loongson 3a5000 develop board emulation
+ *
+ * Copyright (c) 2021 Loongson Technology Corporation Limited
+ */
+#include "qemu/osdep.h"
+#include "qemu-common.h"
+#include "qemu/units.h"
+#include "qemu/datadir.h"
+#include "qapi/error.h"
+#include "hw/boards.h"
+#include "sysemu/sysemu.h"
+#include "sysemu/qtest.h"
+#include "sysemu/runstate.h"
+#include "sysemu/reset.h"
+#include "hw/loongarch/loongarch.h"
+#include "hw/pci-host/ls7a.h"
+
+CPULoongArchState *cpu_states[LOONGARCH_MAX_VCPUS];
+
+static void main_cpu_reset(void *opaque)
+{
+LoongArchCPU *cpu = opaque;
+
+cpu_reset(CPU(cpu));
+}
+
+static uint64_t loongarch_pm_mem_read(void *opaque, hwaddr addr, unsigned size)
+{
+return 0;
+}
+
+static void loongarch_pm_mem_write(void *opaque, hwaddr addr,
+ uint64_t val, unsigned size)
+{
+
+if (addr != PM_CNT_MODE) {
+return;
+}
+
+switch (val) {
+case 0x00:
+qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
+return;
+case 0xff:
+qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
+return;
+default:
+return;
+}
+}
+
+static const MemoryRegionOps loongarch_pm_ops = {
+.read = loongarch_pm_mem_read,
+.write = loongarch_pm_mem_write,
+.endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+#define LOONGARCH_SIMPLE_MMIO_OPS(ADDR, NAME, SIZE) \
+({\
+ MemoryRegion *iomem = g_new(MemoryRegion, 1);\
+ memory_region_init_io(iomem, NULL, _qemu_ops,\
+ (void *)ADDR, NAME, SIZE);\
+ memory_region_add_subregion(lams->system_iocsr, ADDR, iomem);\
+})
+
+static void loongarch_qemu_write(void *opaque, hwaddr addr,
+ uint64_t val, unsigned size)
+{
+}
+
+static uint64_t loongarch_qemu_read(void *opaque, hwaddr addr, unsigned size)
+{
+uint64_t feature = 0UL;
+addr = ((hwaddr)(long)opaque) + addr;
+
+switch (addr) {
+case FEATURE_REG:
+feature |= 1UL << IOCSRF_MSI | 1UL << IOCSRF_EXTIOI |
+ 1UL <<
