Re: [PULL 00/63] riscv-to-apply queue

2020-08-03 Thread Thomas Huth
On 03/08/2020 20.00, Philippe Mathieu-Daudé wrote:
> On 8/3/20 7:53 PM, Thomas Huth wrote:
>> On 30/06/2020 10.44, LIU Zhiwei wrote:
>>>
>>>
>>> On 2020/6/30 16:11, Thomas Huth wrote:
 On 30/06/2020 08.56, LIU Zhiwei wrote:
>
>
> On 2020/6/29 6:51, Alistair Francis wrote:
>> On Sun, Jun 28, 2020 at 7:30 AM Peter Maydell
>>  wrote:
>>> On Fri, 26 Jun 2020 at 22:53, Alistair Francis
>>>  wrote:
 The following changes since commit
 553cf5d7c47bee05a3dec9461c1f8430316d516b:

    Merge remote-tracking branch
 'remotes/pmaydell/tags/pull-target-arm-20200626' into staging
 (2020-06-26 18:22:36 +0100)

 are available in the Git repository at:

    g...@github.com:alistair23/qemu.git
 tags/pull-riscv-to-apply-20200626-1

 for you to fetch changes up to
 b39d59434ea10649fdb9e0a339c30c76e38c5e17:

    target/riscv: configure and turn on vector extension from
 command line (2020-06-26 14:22:15 -0700)

 
 This PR contains two patches to improve PLIC support in QEMU.

 The rest of the PR is adding support for the v0.7.1 RISC-V vector
 extensions. This is experimental support as the vector extensions are
 still in a draft state.

>>> Hi; I'm afraid this fails to build on PPC64 and s390x (ie
>>> our big-endian hosts):
> Hi Peter,
>
> Do you mean you built the patch set on PPC64 or s390x and got errors
> in the list? Or just a worry?
>
> I have built the patch set on Ubuntu 18.04 X86-64. I don't know which
> compile option
> will fails the compilation. If you compiled on Ubuntu x86-64, could
> you show me the
> compile option?

 The related code in your patch "target/riscv: add vector stride load
 and store instructions" is in a "#ifdef HOST_WORDS_BIGENDIAN" section,
 so of course this bug does not trigger on a x86 host. You could
 temporarily turn the "#ifdef HOST_WORDS_BIGENDIAN" into a "#if 1" to
 see whether you can then also reproduce the error on x86.

>>> Yes. I can reproduce it in this way.
> As a note: I try to find a PPC64 for test, but I'm afraid it will be
> too later.
> Is there an available  PPC64  machine in the community?

 Maybe the easiest way to test your code on a big endian machine, too,
 is to get a github account, clone the QEMU repository there, and
 enable Travis for that repo. Then your code gets built on some non-x86
 architectures (including a big-endian s390x) as soon as you push it to
 the repo (see .travis.yml for details).

>>> Thanks very much. I will have a try.
>>> /home/ubuntu/qemu/target/riscv/vector_helper.c: In function
>>> ‘vext_clear’:
>>> /home/ubuntu/qemu/target/riscv/vector_helper.c: In function
>>> ‘vext_clear’:
>>> /home/ubuntu/qemu/target/riscv/vector_helper.c:154:21: error: invalid
>>> operands to binary & (have ‘void *’ and ‘long long unsigned int’)
>>>   memset(tail & ~(7ULL), 0, part1);

 You obviously must not use "&" with a pointer. I guess you have to
 cast to "uintptr_t" and back, or think of some other smart way to fix
 this.

>>> Yes. That's the error. It  build successfully after the cast.
>>
>> I'm sorry, but the new code fails to compile on big endian 32-bit
>> targets, see https://gitlab.com/huth/qemu/-/jobs/667762754#L3434 :
>>
>> /builds/huth/qemu/target/riscv/vector_helper.c: In function 'vext_clear':
>> /builds/huth/qemu/target/riscv/vector_helper.c:154:16: error: cast to
>> pointer from integer of different size [-Werror=int-to-pointer-cast]
>>  memset((void *)((uintptr_t)tail & ~(7ULL)), 0, part1);
>> ^
>> /builds/huth/qemu/target/riscv/vector_helper.c:155:16: error: cast to
>> pointer from integer of different size [-Werror=int-to-pointer-cast]
>> memset((void *)(((uintptr_t)tail + 8) & ~(7ULL)), 0, part2);
>> ^
>> cc1: all warnings being treated as errors
>>
>> A quick work-around is maybe to replace "ULL" with simply "UL" ?
> 
> Or use QEMU_ALIGN_PTR_DOWN?

Sounds like a good idea! I'll give it a try and send a patch ...

 Thomas




Re: [PULL 00/63] riscv-to-apply queue

2020-08-03 Thread Philippe Mathieu-Daudé
On 8/3/20 7:53 PM, Thomas Huth wrote:
> On 30/06/2020 10.44, LIU Zhiwei wrote:
>>
>>
>> On 2020/6/30 16:11, Thomas Huth wrote:
>>> On 30/06/2020 08.56, LIU Zhiwei wrote:


 On 2020/6/29 6:51, Alistair Francis wrote:
> On Sun, Jun 28, 2020 at 7:30 AM Peter Maydell
>  wrote:
>> On Fri, 26 Jun 2020 at 22:53, Alistair Francis
>>  wrote:
>>> The following changes since commit
>>> 553cf5d7c47bee05a3dec9461c1f8430316d516b:
>>>
>>>    Merge remote-tracking branch
>>> 'remotes/pmaydell/tags/pull-target-arm-20200626' into staging
>>> (2020-06-26 18:22:36 +0100)
>>>
>>> are available in the Git repository at:
>>>
>>>    g...@github.com:alistair23/qemu.git
>>> tags/pull-riscv-to-apply-20200626-1
>>>
>>> for you to fetch changes up to
>>> b39d59434ea10649fdb9e0a339c30c76e38c5e17:
>>>
>>>    target/riscv: configure and turn on vector extension from
>>> command line (2020-06-26 14:22:15 -0700)
>>>
>>> 
>>> This PR contains two patches to improve PLIC support in QEMU.
>>>
>>> The rest of the PR is adding support for the v0.7.1 RISC-V vector
>>> extensions. This is experimental support as the vector extensions are
>>> still in a draft state.
>>>
>> Hi; I'm afraid this fails to build on PPC64 and s390x (ie
>> our big-endian hosts):
 Hi Peter,

 Do you mean you built the patch set on PPC64 or s390x and got errors
 in the list? Or just a worry?

 I have built the patch set on Ubuntu 18.04 X86-64. I don't know which
 compile option
 will fails the compilation. If you compiled on Ubuntu x86-64, could
 you show me the
 compile option?
>>>
>>> The related code in your patch "target/riscv: add vector stride load
>>> and store instructions" is in a "#ifdef HOST_WORDS_BIGENDIAN" section,
>>> so of course this bug does not trigger on a x86 host. You could
>>> temporarily turn the "#ifdef HOST_WORDS_BIGENDIAN" into a "#if 1" to
>>> see whether you can then also reproduce the error on x86.
>>>
>> Yes. I can reproduce it in this way.
 As a note: I try to find a PPC64 for test, but I'm afraid it will be
 too later.
 Is there an available  PPC64  machine in the community?
>>>
>>> Maybe the easiest way to test your code on a big endian machine, too,
>>> is to get a github account, clone the QEMU repository there, and
>>> enable Travis for that repo. Then your code gets built on some non-x86
>>> architectures (including a big-endian s390x) as soon as you push it to
>>> the repo (see .travis.yml for details).
>>>
>> Thanks very much. I will have a try.
>> /home/ubuntu/qemu/target/riscv/vector_helper.c: In function
>> ‘vext_clear’:
>> /home/ubuntu/qemu/target/riscv/vector_helper.c: In function
>> ‘vext_clear’:
>> /home/ubuntu/qemu/target/riscv/vector_helper.c:154:21: error: invalid
>> operands to binary & (have ‘void *’ and ‘long long unsigned int’)
>>   memset(tail & ~(7ULL), 0, part1);
>>>
>>> You obviously must not use "&" with a pointer. I guess you have to
>>> cast to "uintptr_t" and back, or think of some other smart way to fix
>>> this.
>>>
>> Yes. That's the error. It  build successfully after the cast.
> 
> I'm sorry, but the new code fails to compile on big endian 32-bit
> targets, see https://gitlab.com/huth/qemu/-/jobs/667762754#L3434 :
> 
> /builds/huth/qemu/target/riscv/vector_helper.c: In function 'vext_clear':
> /builds/huth/qemu/target/riscv/vector_helper.c:154:16: error: cast to
> pointer from integer of different size [-Werror=int-to-pointer-cast]
>  memset((void *)((uintptr_t)tail & ~(7ULL)), 0, part1);
> ^
> /builds/huth/qemu/target/riscv/vector_helper.c:155:16: error: cast to
> pointer from integer of different size [-Werror=int-to-pointer-cast]
> memset((void *)(((uintptr_t)tail + 8) & ~(7ULL)), 0, part2);
> ^
> cc1: all warnings being treated as errors
> 
> A quick work-around is maybe to replace "ULL" with simply "UL" ?

Or use QEMU_ALIGN_PTR_DOWN?

> 
>  Thomas
> 
> 




Re: [PULL 00/63] riscv-to-apply queue

2020-08-03 Thread Thomas Huth
On 30/06/2020 10.44, LIU Zhiwei wrote:
> 
> 
> On 2020/6/30 16:11, Thomas Huth wrote:
>> On 30/06/2020 08.56, LIU Zhiwei wrote:
>>>
>>>
>>> On 2020/6/29 6:51, Alistair Francis wrote:
 On Sun, Jun 28, 2020 at 7:30 AM Peter Maydell
  wrote:
> On Fri, 26 Jun 2020 at 22:53, Alistair Francis
>  wrote:
>> The following changes since commit
>> 553cf5d7c47bee05a3dec9461c1f8430316d516b:
>>
>>    Merge remote-tracking branch
>> 'remotes/pmaydell/tags/pull-target-arm-20200626' into staging
>> (2020-06-26 18:22:36 +0100)
>>
>> are available in the Git repository at:
>>
>>    g...@github.com:alistair23/qemu.git
>> tags/pull-riscv-to-apply-20200626-1
>>
>> for you to fetch changes up to
>> b39d59434ea10649fdb9e0a339c30c76e38c5e17:
>>
>>    target/riscv: configure and turn on vector extension from
>> command line (2020-06-26 14:22:15 -0700)
>>
>> 
>> This PR contains two patches to improve PLIC support in QEMU.
>>
>> The rest of the PR is adding support for the v0.7.1 RISC-V vector
>> extensions. This is experimental support as the vector extensions are
>> still in a draft state.
>>
> Hi; I'm afraid this fails to build on PPC64 and s390x (ie
> our big-endian hosts):
>>> Hi Peter,
>>>
>>> Do you mean you built the patch set on PPC64 or s390x and got errors
>>> in the list? Or just a worry?
>> >
>>> I have built the patch set on Ubuntu 18.04 X86-64. I don't know which
>>> compile option
>>> will fails the compilation. If you compiled on Ubuntu x86-64, could
>>> you show me the
>>> compile option?
>>
>> The related code in your patch "target/riscv: add vector stride load
>> and store instructions" is in a "#ifdef HOST_WORDS_BIGENDIAN" section,
>> so of course this bug does not trigger on a x86 host. You could
>> temporarily turn the "#ifdef HOST_WORDS_BIGENDIAN" into a "#if 1" to
>> see whether you can then also reproduce the error on x86.
>>
> Yes. I can reproduce it in this way.
>>> As a note: I try to find a PPC64 for test, but I'm afraid it will be
>>> too later.
>>> Is there an available  PPC64  machine in the community?
>>
>> Maybe the easiest way to test your code on a big endian machine, too,
>> is to get a github account, clone the QEMU repository there, and
>> enable Travis for that repo. Then your code gets built on some non-x86
>> architectures (including a big-endian s390x) as soon as you push it to
>> the repo (see .travis.yml for details).
>>
> Thanks very much. I will have a try.
> /home/ubuntu/qemu/target/riscv/vector_helper.c: In function
> ‘vext_clear’:
> /home/ubuntu/qemu/target/riscv/vector_helper.c: In function
> ‘vext_clear’:
> /home/ubuntu/qemu/target/riscv/vector_helper.c:154:21: error: invalid
> operands to binary & (have ‘void *’ and ‘long long unsigned int’)
>   memset(tail & ~(7ULL), 0, part1);
>>
>> You obviously must not use "&" with a pointer. I guess you have to
>> cast to "uintptr_t" and back, or think of some other smart way to fix
>> this.
>>
> Yes. That's the error. It  build successfully after the cast.

I'm sorry, but the new code fails to compile on big endian 32-bit
targets, see https://gitlab.com/huth/qemu/-/jobs/667762754#L3434 :

/builds/huth/qemu/target/riscv/vector_helper.c: In function 'vext_clear':
/builds/huth/qemu/target/riscv/vector_helper.c:154:16: error: cast to
pointer from integer of different size [-Werror=int-to-pointer-cast]
 memset((void *)((uintptr_t)tail & ~(7ULL)), 0, part1);
^
/builds/huth/qemu/target/riscv/vector_helper.c:155:16: error: cast to
pointer from integer of different size [-Werror=int-to-pointer-cast]
memset((void *)(((uintptr_t)tail + 8) & ~(7ULL)), 0, part2);
^
cc1: all warnings being treated as errors

A quick work-around is maybe to replace "ULL" with simply "UL" ?

 Thomas




Re: [PULL 00/63] riscv-to-apply queue

2020-06-30 Thread LIU Zhiwei




On 2020/6/30 16:11, Thomas Huth wrote:

On 30/06/2020 08.56, LIU Zhiwei wrote:



On 2020/6/29 6:51, Alistair Francis wrote:
On Sun, Jun 28, 2020 at 7:30 AM Peter Maydell 
 wrote:
On Fri, 26 Jun 2020 at 22:53, Alistair Francis 
 wrote:
The following changes since commit 
553cf5d7c47bee05a3dec9461c1f8430316d516b:


   Merge remote-tracking branch 
'remotes/pmaydell/tags/pull-target-arm-20200626' into staging 
(2020-06-26 18:22:36 +0100)


are available in the Git repository at:

   g...@github.com:alistair23/qemu.git 
tags/pull-riscv-to-apply-20200626-1


for you to fetch changes up to 
b39d59434ea10649fdb9e0a339c30c76e38c5e17:


   target/riscv: configure and turn on vector extension from 
command line (2020-06-26 14:22:15 -0700)



This PR contains two patches to improve PLIC support in QEMU.

The rest of the PR is adding support for the v0.7.1 RISC-V vector
extensions. This is experimental support as the vector extensions are
still in a draft state.


Hi; I'm afraid this fails to build on PPC64 and s390x (ie
our big-endian hosts):

Hi Peter,

Do you mean you built the patch set on PPC64 or s390x and got errors 
in the list? Or just a worry?

>
I have built the patch set on Ubuntu 18.04 X86-64. I don't know which 
compile option
will fails the compilation. If you compiled on Ubuntu x86-64, could 
you show me the

compile option?


The related code in your patch "target/riscv: add vector stride load 
and store instructions" is in a "#ifdef HOST_WORDS_BIGENDIAN" section, 
so of course this bug does not trigger on a x86 host. You could 
temporarily turn the "#ifdef HOST_WORDS_BIGENDIAN" into a "#if 1" to 
see whether you can then also reproduce the error on x86.



Yes. I can reproduce it in this way.
As a note: I try to find a PPC64 for test, but I'm afraid it will be 
too later.

Is there an available  PPC64  machine in the community?


Maybe the easiest way to test your code on a big endian machine, too, 
is to get a github account, clone the QEMU repository there, and 
enable Travis for that repo. Then your code gets built on some non-x86 
architectures (including a big-endian s390x) as soon as you push it to 
the repo (see .travis.yml for details).



Thanks very much. I will have a try.
/home/ubuntu/qemu/target/riscv/vector_helper.c: In function 
‘vext_clear’:
/home/ubuntu/qemu/target/riscv/vector_helper.c: In function 
‘vext_clear’:

/home/ubuntu/qemu/target/riscv/vector_helper.c:154:21: error: invalid
operands to binary & (have ‘void *’ and ‘long long unsigned int’)
  memset(tail & ~(7ULL), 0, part1);


You obviously must not use "&" with a pointer. I guess you have to 
cast to "uintptr_t" and back, or think of some other smart way to fix 
this.



Yes. That's the error. It  build successfully after the cast.

Best Regards,
Zhiwei

 Thomas





Re: [PULL 00/63] riscv-to-apply queue

2020-06-30 Thread Thomas Huth

On 30/06/2020 08.56, LIU Zhiwei wrote:



On 2020/6/29 6:51, Alistair Francis wrote:
On Sun, Jun 28, 2020 at 7:30 AM Peter Maydell 
 wrote:
On Fri, 26 Jun 2020 at 22:53, Alistair Francis 
 wrote:
The following changes since commit 
553cf5d7c47bee05a3dec9461c1f8430316d516b:


   Merge remote-tracking branch 
'remotes/pmaydell/tags/pull-target-arm-20200626' into staging 
(2020-06-26 18:22:36 +0100)


are available in the Git repository at:

   g...@github.com:alistair23/qemu.git 
tags/pull-riscv-to-apply-20200626-1


for you to fetch changes up to 
b39d59434ea10649fdb9e0a339c30c76e38c5e17:


   target/riscv: configure and turn on vector extension from command 
line (2020-06-26 14:22:15 -0700)



This PR contains two patches to improve PLIC support in QEMU.

The rest of the PR is adding support for the v0.7.1 RISC-V vector
extensions. This is experimental support as the vector extensions are
still in a draft state.


Hi; I'm afraid this fails to build on PPC64 and s390x (ie
our big-endian hosts):

Hi Peter,

Do you mean you built the patch set on PPC64 or s390x and got errors in 
the list? Or just a worry?

>
I have built the patch set on Ubuntu 18.04 X86-64. I don't know which 
compile option
will fails the compilation. If you compiled on Ubuntu x86-64, could you 
show me the

compile option?


The related code in your patch "target/riscv: add vector stride load and 
store instructions" is in a "#ifdef HOST_WORDS_BIGENDIAN" section, so of 
course this bug does not trigger on a x86 host. You could temporarily 
turn the "#ifdef HOST_WORDS_BIGENDIAN" into a "#if 1" to see whether you 
can then also reproduce the error on x86.


As a note: I try to find a PPC64 for test, but I'm afraid it will be too 
later.

Is there an available  PPC64  machine in the community?


Maybe the easiest way to test your code on a big endian machine, too, is 
to get a github account, clone the QEMU repository there, and enable 
Travis for that repo. Then your code gets built on some non-x86 
architectures (including a big-endian s390x) as soon as you push it to 
the repo (see .travis.yml for details).


/home/ubuntu/qemu/target/riscv/vector_helper.c: In function 
‘vext_clear’:
/home/ubuntu/qemu/target/riscv/vector_helper.c: In function 
‘vext_clear’:

/home/ubuntu/qemu/target/riscv/vector_helper.c:154:21: error: invalid
operands to binary & (have ‘void *’ and ‘long long unsigned int’)
  memset(tail & ~(7ULL), 0, part1);


You obviously must not use "&" with a pointer. I guess you have to cast 
to "uintptr_t" and back, or think of some other smart way to fix this.


 Thomas




Re: [PULL 00/63] riscv-to-apply queue

2020-06-30 Thread LIU Zhiwei




On 2020/6/29 6:51, Alistair Francis wrote:

On Sun, Jun 28, 2020 at 7:30 AM Peter Maydell  wrote:

On Fri, 26 Jun 2020 at 22:53, Alistair Francis  wrote:

The following changes since commit 553cf5d7c47bee05a3dec9461c1f8430316d516b:

   Merge remote-tracking branch 
'remotes/pmaydell/tags/pull-target-arm-20200626' into staging (2020-06-26 
18:22:36 +0100)

are available in the Git repository at:

   g...@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20200626-1

for you to fetch changes up to b39d59434ea10649fdb9e0a339c30c76e38c5e17:

   target/riscv: configure and turn on vector extension from command line 
(2020-06-26 14:22:15 -0700)


This PR contains two patches to improve PLIC support in QEMU.

The rest of the PR is adding support for the v0.7.1 RISC-V vector
extensions. This is experimental support as the vector extensions are
still in a draft state.


Hi; I'm afraid this fails to build on PPC64 and s390x (ie
our big-endian hosts):

Hi Peter,

Do you mean you built the patch set on PPC64 or s390x and got errors in 
the list? Or just a worry?


I have built the patch set on Ubuntu 18.04 X86-64. I don't know which 
compile option
will fails the compilation. If you compiled on Ubuntu x86-64, could you 
show me the

compile option?

As a note: I try to find a PPC64 for test, but I'm afraid it will be too 
later.

Is there an available  PPC64  machine in the community?

Thanks very much.

Zhiwei

LIU Zhiwei do you mind looking into this?

Alistair


/home/ubuntu/qemu/target/riscv/vector_helper.c: In function ‘vext_clear’:
/home/ubuntu/qemu/target/riscv/vector_helper.c: In function ‘vext_clear’:
/home/ubuntu/qemu/target/riscv/vector_helper.c:154:21: error: invalid
operands to binary & (have ‘void *’ and ‘long long unsigned int’)
  memset(tail & ~(7ULL), 0, part1);
  ^
/home/ubuntu/qemu/target/riscv/vector_helper.c:155:27: error: invalid
operands to binary & (have ‘void *’ and ‘long long unsigned int’)
  memset((tail + 8) & ~(7ULL), 0, part2);
 ~~ ^
/home/ubuntu/qemu/target/riscv/vector_helper.c:154:21: error: invalid
operands to binary & (have ‘void *’ and ‘long long unsigned int’)
  memset(tail & ~(7ULL), 0, part1);
  ^
/home/ubuntu/qemu/target/riscv/vector_helper.c:155:27: error: invalid
operands to binary & (have ‘void *’ and ‘long long unsigned int’)
  memset((tail + 8) & ~(7ULL), 0, part2);
 ~~ ^
/home/ubuntu/qemu/rules.mak:69: recipe for target
'target/riscv/vector_helper.o' failed


thanks
-- PMM





Re: [PULL 00/63] riscv-to-apply queue

2020-06-28 Thread LIU Zhiwei




On 2020/6/29 6:51, Alistair Francis wrote:

On Sun, Jun 28, 2020 at 7:30 AM Peter Maydell  wrote:

On Fri, 26 Jun 2020 at 22:53, Alistair Francis  wrote:

The following changes since commit 553cf5d7c47bee05a3dec9461c1f8430316d516b:

   Merge remote-tracking branch 
'remotes/pmaydell/tags/pull-target-arm-20200626' into staging (2020-06-26 
18:22:36 +0100)

are available in the Git repository at:

   g...@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20200626-1

for you to fetch changes up to b39d59434ea10649fdb9e0a339c30c76e38c5e17:

   target/riscv: configure and turn on vector extension from command line 
(2020-06-26 14:22:15 -0700)


This PR contains two patches to improve PLIC support in QEMU.

The rest of the PR is adding support for the v0.7.1 RISC-V vector
extensions. This is experimental support as the vector extensions are
still in a draft state.


Hi; I'm afraid this fails to build on PPC64 and s390x (ie
our big-endian hosts):

LIU Zhiwei do you mind looking into this?

Sure, I will.
I have applied for a gcc compile farm account today, but it maybe a few 
days later before I can login.

Please accept my apologies for my oversight.

Zhiwei


Alistair


/home/ubuntu/qemu/target/riscv/vector_helper.c: In function ‘vext_clear’:
/home/ubuntu/qemu/target/riscv/vector_helper.c: In function ‘vext_clear’:
/home/ubuntu/qemu/target/riscv/vector_helper.c:154:21: error: invalid
operands to binary & (have ‘void *’ and ‘long long unsigned int’)
  memset(tail & ~(7ULL), 0, part1);
  ^
/home/ubuntu/qemu/target/riscv/vector_helper.c:155:27: error: invalid
operands to binary & (have ‘void *’ and ‘long long unsigned int’)
  memset((tail + 8) & ~(7ULL), 0, part2);
 ~~ ^
/home/ubuntu/qemu/target/riscv/vector_helper.c:154:21: error: invalid
operands to binary & (have ‘void *’ and ‘long long unsigned int’)
  memset(tail & ~(7ULL), 0, part1);
  ^
/home/ubuntu/qemu/target/riscv/vector_helper.c:155:27: error: invalid
operands to binary & (have ‘void *’ and ‘long long unsigned int’)
  memset((tail + 8) & ~(7ULL), 0, part2);
 ~~ ^
/home/ubuntu/qemu/rules.mak:69: recipe for target
'target/riscv/vector_helper.o' failed


thanks
-- PMM





Re: [PULL 00/63] riscv-to-apply queue

2020-06-28 Thread Alistair Francis
On Sun, Jun 28, 2020 at 7:30 AM Peter Maydell  wrote:
>
> On Fri, 26 Jun 2020 at 22:53, Alistair Francis  
> wrote:
> >
> > The following changes since commit 553cf5d7c47bee05a3dec9461c1f8430316d516b:
> >
> >   Merge remote-tracking branch 
> > 'remotes/pmaydell/tags/pull-target-arm-20200626' into staging (2020-06-26 
> > 18:22:36 +0100)
> >
> > are available in the Git repository at:
> >
> >   g...@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20200626-1
> >
> > for you to fetch changes up to b39d59434ea10649fdb9e0a339c30c76e38c5e17:
> >
> >   target/riscv: configure and turn on vector extension from command line 
> > (2020-06-26 14:22:15 -0700)
> >
> > 
> > This PR contains two patches to improve PLIC support in QEMU.
> >
> > The rest of the PR is adding support for the v0.7.1 RISC-V vector
> > extensions. This is experimental support as the vector extensions are
> > still in a draft state.
> >
>
> Hi; I'm afraid this fails to build on PPC64 and s390x (ie
> our big-endian hosts):

LIU Zhiwei do you mind looking into this?

Alistair

>
> /home/ubuntu/qemu/target/riscv/vector_helper.c: In function ‘vext_clear’:
> /home/ubuntu/qemu/target/riscv/vector_helper.c: In function ‘vext_clear’:
> /home/ubuntu/qemu/target/riscv/vector_helper.c:154:21: error: invalid
> operands to binary & (have ‘void *’ and ‘long long unsigned int’)
>  memset(tail & ~(7ULL), 0, part1);
>  ^
> /home/ubuntu/qemu/target/riscv/vector_helper.c:155:27: error: invalid
> operands to binary & (have ‘void *’ and ‘long long unsigned int’)
>  memset((tail + 8) & ~(7ULL), 0, part2);
> ~~ ^
> /home/ubuntu/qemu/target/riscv/vector_helper.c:154:21: error: invalid
> operands to binary & (have ‘void *’ and ‘long long unsigned int’)
>  memset(tail & ~(7ULL), 0, part1);
>  ^
> /home/ubuntu/qemu/target/riscv/vector_helper.c:155:27: error: invalid
> operands to binary & (have ‘void *’ and ‘long long unsigned int’)
>  memset((tail + 8) & ~(7ULL), 0, part2);
> ~~ ^
> /home/ubuntu/qemu/rules.mak:69: recipe for target
> 'target/riscv/vector_helper.o' failed
>
>
> thanks
> -- PMM



Re: [PULL 00/63] riscv-to-apply queue

2020-06-28 Thread Peter Maydell
On Fri, 26 Jun 2020 at 22:53, Alistair Francis  wrote:
>
> The following changes since commit 553cf5d7c47bee05a3dec9461c1f8430316d516b:
>
>   Merge remote-tracking branch 
> 'remotes/pmaydell/tags/pull-target-arm-20200626' into staging (2020-06-26 
> 18:22:36 +0100)
>
> are available in the Git repository at:
>
>   g...@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20200626-1
>
> for you to fetch changes up to b39d59434ea10649fdb9e0a339c30c76e38c5e17:
>
>   target/riscv: configure and turn on vector extension from command line 
> (2020-06-26 14:22:15 -0700)
>
> 
> This PR contains two patches to improve PLIC support in QEMU.
>
> The rest of the PR is adding support for the v0.7.1 RISC-V vector
> extensions. This is experimental support as the vector extensions are
> still in a draft state.
>

Hi; I'm afraid this fails to build on PPC64 and s390x (ie
our big-endian hosts):

/home/ubuntu/qemu/target/riscv/vector_helper.c: In function ‘vext_clear’:
/home/ubuntu/qemu/target/riscv/vector_helper.c: In function ‘vext_clear’:
/home/ubuntu/qemu/target/riscv/vector_helper.c:154:21: error: invalid
operands to binary & (have ‘void *’ and ‘long long unsigned int’)
 memset(tail & ~(7ULL), 0, part1);
 ^
/home/ubuntu/qemu/target/riscv/vector_helper.c:155:27: error: invalid
operands to binary & (have ‘void *’ and ‘long long unsigned int’)
 memset((tail + 8) & ~(7ULL), 0, part2);
~~ ^
/home/ubuntu/qemu/target/riscv/vector_helper.c:154:21: error: invalid
operands to binary & (have ‘void *’ and ‘long long unsigned int’)
 memset(tail & ~(7ULL), 0, part1);
 ^
/home/ubuntu/qemu/target/riscv/vector_helper.c:155:27: error: invalid
operands to binary & (have ‘void *’ and ‘long long unsigned int’)
 memset((tail + 8) & ~(7ULL), 0, part2);
~~ ^
/home/ubuntu/qemu/rules.mak:69: recipe for target
'target/riscv/vector_helper.o' failed


thanks
-- PMM



Re: [PULL 00/63] riscv-to-apply queue

2020-06-26 Thread no-reply
Patchew URL: 
https://patchew.org/QEMU/20200626214410.3613258-1-alistair.fran...@wdc.com/



Hi,

This series failed the docker-mingw@fedora build test. Please find the testing 
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.

=== TEST SCRIPT BEGIN ===
#! /bin/bash
export ARCH=x86_64
make docker-image-fedora V=1 NETWORK=1
time make docker-test-mingw@fedora J=14 NETWORK=1
=== TEST SCRIPT END ===

raise CalledProcessError(retcode, cmd)
subprocess.CalledProcessError: Command '['sudo', '-n', 'docker', 'run', 
'--label', 'com.qemu.instance.uuid=3227ad66ddf54e91801ba30034f49d0d', '-u', 
'1001', '--security-opt', 'seccomp=unconfined', '--rm', '-e', 'TARGET_LIST=', 
'-e', 'EXTRA_CONFIGURE_OPTS=', '-e', 'V=', '-e', 'J=14', '-e', 'DEBUG=', '-e', 
'SHOW_ENV=', '-e', 'CCACHE_DIR=/var/tmp/ccache', '-v', 
'/home/patchew/.cache/qemu-docker-ccache:/var/tmp/ccache:z', '-v', 
'/var/tmp/patchew-tester-tmp-nymx7cv5/src/docker-src.2020-06-26-18.37.24.5231:/var/tmp/qemu:z,ro',
 'qemu:fedora', '/var/tmp/qemu/run', 'test-mingw']' returned non-zero exit 
status 2.
filter=--filter=label=com.qemu.instance.uuid=3227ad66ddf54e91801ba30034f49d0d
make[1]: *** [docker-run] Error 1
make[1]: Leaving directory `/var/tmp/patchew-tester-tmp-nymx7cv5/src'
make: *** [docker-run-test-mingw@fedora] Error 2

real6m37.447s
user0m9.016s


The full log is available at
http://patchew.org/logs/20200626214410.3613258-1-alistair.fran...@wdc.com/testing.docker-mingw@fedora/?type=message.
---
Email generated automatically by Patchew [https://patchew.org/].
Please send your feedback to patchew-de...@redhat.com

Re: [PULL 00/63] riscv-to-apply queue

2020-06-26 Thread no-reply
Patchew URL: 
https://patchew.org/QEMU/20200626214410.3613258-1-alistair.fran...@wdc.com/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Subject: [PULL 00/63] riscv-to-apply queue
Type: series
Message-id: 20200626214410.3613258-1-alistair.fran...@wdc.com

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

From https://github.com/patchew-project/qemu
 * [new tag] patchew/20200626214410.3613258-1-alistair.fran...@wdc.com 
-> patchew/20200626214410.3613258-1-alistair.fran...@wdc.com
Auto packing the repository for optimum performance. You may also
run "git gc" manually. See "git help gc" for more information.
Switched to a new branch 'test'
cd5b7c4 target/riscv: configure and turn on vector extension from command line
c58857c target/riscv: vector compress instruction
dfd9589 target/riscv: vector register gather instruction
f686a11 target/riscv: vector slide instructions
cbaef7d target/riscv: floating-point scalar move instructions
869e2ea target/riscv: integer scalar move instruction
cc89401 target/riscv: integer extract instruction
80ff8d1 target/riscv: vector element index instruction
7b77a67 target/riscv: vector iota instruction
2401535 target/riscv: set-X-first mask bit
3b818e7 target/riscv: vmfirst find-first-set mask bit
2b926a8 target/riscv: vector mask population count vmpopc
a188474 target/riscv: vector mask-register logical instructions
89e4b56 target/riscv: vector widening floating-point reduction instructions
a9d5e44 target/riscv: vector single-width floating-point reduction instructions
f0313f4 target/riscv: vector wideing integer reduction instructions
3ad6c50 target/riscv: vector single-width integer reduction instructions
3ea3f11 target/riscv: narrowing floating-point/integer type-convert instructions
583cb8d target/riscv: widening floating-point/integer type-convert instructions
f233822 target/riscv: vector floating-point/integer type-convert instructions
82c1888 target/riscv: vector floating-point merge instructions
08c2fe7 target/riscv: vector floating-point classify instructions
81c1632 target/riscv: vector floating-point compare instructions
e34823e target/riscv: vector floating-point sign-injection instructions
8d5d4eb target/riscv: vector floating-point min/max instructions
11148eb target/riscv: vector floating-point square-root instruction
fb66a6a target/riscv: vector widening floating-point fused multiply-add 
instructions
23781ba target/riscv: vector single-width floating-point fused multiply-add 
instructions
f543e1d target/riscv: vector widening floating-point multiply
77558b0 target/riscv: vector single-width floating-point multiply/divide 
instructions
644657b target/riscv: vector widening floating-point add/subtract instructions
737c4ae target/riscv: vector single-width floating-point add/subtract 
instructions
e5365b3 target/riscv: vector narrowing fixed-point clip instructions
9948ef4 target/riscv: vector single-width scaling shift instructions
f9763c2 target/riscv: vector widening saturating scaled multiply-add
651cee5 target/riscv: vector single-width fractional multiply with rounding and 
saturation
02c1db1 target/riscv: vector single-width averaging add and subtract
0240b96 target/riscv: vector single-width saturating add and subtract
13da6db target/riscv: vector integer merge and move instructions
817d651 target/riscv: vector widening integer multiply-add instructions
55dbb3d target/riscv: vector single-width integer multiply-add instructions
caa7cd7 target/riscv: vector widening integer multiply instructions
6ee55f1 target/riscv: vector integer divide instructions
53dac4b target/riscv: vector single-width integer multiply instructions
e105f4a target/riscv: vector integer min/max instructions
555b7eb target/riscv: vector integer comparison instructions
041ad12 target/riscv: vector narrowing integer right shift instructions
1ee9221 target/riscv: vector single-width bit shift instructions
60d2872 target/riscv: vector bitwise logical instructions
1b4efd2 target/riscv: vector integer add-with-carry / subtract-with-borrow 
instructions
42cd1fc target/riscv: vector widening integer add and subtract
bfb10da target/riscv: vector single-width integer add and subtract
c3da998 target/riscv: add vector amo operations
f7d8b4f target/riscv: add fault-only-first unit stride load
404b17c target/riscv: add vector index load and store instructions
ee691fd target/riscv: add vector stride load and store instructions
f2ab6d0 target/riscv: add an internals.h header
3e9d956 target/riscv: add vector configure instruction
560561b target/riscv: support vector extension csr
4eac3b3 target/riscv: implementation-defined constant parameters
bf4f637 target/riscv: add vector extension field in CPURISCVState
b5a0bb5 riscv: plic: