Re: [Qemu-devel] [PATCH] pnv: add a physical mapping array describing MMIO ranges in each chip
On 05/23/2018 04:04 PM, Greg Kurz wrote:
> On Wed, 23 May 2018 14:37:30 +0200
> Cédric Le Goater wrote:
>
>> On 05/18/2018 11:00 AM, Greg Kurz wrote:
>>> On Thu, 17 May 2018 15:18:14 +0200
>>> Cédric Le Goater wrote:
>>>
Based on previous work done in skiboot, the physical mapping array
helps in calculating the MMIO ranges of each controller depending on
the chip id and the chip type. This is will be particularly useful for
the P9 models which use less the XSCOM bus and rely more on MMIOs.
A link on the chip is now necessary to calculate MMIO BARs and
sizes. This is why such a link is introduced in the PSIHB model.
Signed-off-by: Cédric Le Goater
---
hw/ppc/pnv.c | 32 +
hw/ppc/pnv_psi.c | 11 +-
hw/ppc/pnv_xscom.c | 8
include/hw/ppc/pnv.h | 58
+---
4 files changed, 80 insertions(+), 29 deletions(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 031488131629..330bf6f74810 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -712,6 +712,16 @@ static uint32_t pnv_chip_core_pir_p9(PnvChip *chip,
uint32_t core_id)
*/
#define POWER9_CORE_MASK (0xffull)
+/*
+ * POWER8 MMIOs
+ */
+static const PnvPhysMapEntry pnv_chip_power8_phys_map[] = {
+[PNV_MAP_XSCOM] = { 0x0003fc00ull, 0x0008ull
},
+[PNV_MAP_ICP] = { 0x00038000ull, 0x0010ull
},
+[PNV_MAP_PSIHB] = { 0x0003fffe8000ull, 0x0010ull
},
+[PNV_MAP_PSIHB_FSP] = { 0x0003ffe0ull, 0x0001ull
},
+};
+
static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
@@ -721,7 +731,7 @@ static void pnv_chip_power8e_class_init(ObjectClass
*klass, void *data)
k->chip_cfam_id = 0x221ef0498000ull; /* P8 Murano DD2.1 */
k->cores_mask = POWER8E_CORE_MASK;
k->core_pir = pnv_chip_core_pir_p8;
-k->xscom_base = 0x003fc00ull;
+k->phys_map = pnv_chip_power8_phys_map;
dc->desc = "PowerNV Chip POWER8E";
}
@@ -734,7 +744,7 @@ static void pnv_chip_power8_class_init(ObjectClass
*klass, void *data)
k->chip_cfam_id = 0x220ea0498000ull; /* P8 Venice DD2.0 */
k->cores_mask = POWER8_CORE_MASK;
k->core_pir = pnv_chip_core_pir_p8;
-k->xscom_base = 0x003fc00ull;
+k->phys_map = pnv_chip_power8_phys_map;
dc->desc = "PowerNV Chip POWER8";
}
@@ -747,10 +757,17 @@ static void
pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data)
k->chip_cfam_id = 0x120d30498000ull; /* P8 Naples DD1.0 */
k->cores_mask = POWER8_CORE_MASK;
k->core_pir = pnv_chip_core_pir_p8;
-k->xscom_base = 0x003fc00ull;
+k->phys_map = pnv_chip_power8_phys_map;
dc->desc = "PowerNV Chip POWER8NVL";
}
+/*
+ * POWER9 MMIOs
+ */
+static const PnvPhysMapEntry pnv_chip_power9_phys_map[] = {
+[PNV_MAP_XSCOM] = { 0x000603fcull, 0x0400ull
},
+};
+
static void pnv_chip_power9_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
@@ -760,7 +777,7 @@ static void pnv_chip_power9_class_init(ObjectClass
*klass, void *data)
k->chip_cfam_id = 0x220d10498000ull; /* P9 Nimbus DD2.0 */
k->cores_mask = POWER9_CORE_MASK;
k->core_pir = pnv_chip_core_pir_p9;
-k->xscom_base = 0x00603fcull;
+k->phys_map = pnv_chip_power9_phys_map;
dc->desc = "PowerNV Chip POWER9";
}
@@ -797,15 +814,14 @@ static void pnv_chip_core_sanitize(PnvChip *chip,
Error **errp)
static void pnv_chip_init(Object *obj)
{
PnvChip *chip = PNV_CHIP(obj);
-PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
-
-chip->xscom_base = pcc->xscom_base;
object_initialize(&chip->lpc, sizeof(chip->lpc), TYPE_PNV_LPC);
object_property_add_child(obj, "lpc", OBJECT(&chip->lpc), NULL);
object_initialize(&chip->psi, sizeof(chip->psi), TYPE_PNV_PSI);
object_property_add_child(obj, "psi", OBJECT(&chip->psi), NULL);
+object_property_add_const_link(OBJECT(&chip->psi), "chip", obj,
+ &error_abort);
object_property_add_const_link(OBJECT(&chip->psi), "xics",
OBJECT(qdev_get_machine()),
&error_abort);
@@ -829,7 +845,7 @@ static void pnv_chip_icp_realize(PnvChip *chip, Error
**errp)
XICS
Re: [Qemu-devel] [PATCH] pnv: add a physical mapping array describing MMIO ranges in each chip
On Wed, 23 May 2018 14:37:30 +0200
Cédric Le Goater wrote:
> On 05/18/2018 11:00 AM, Greg Kurz wrote:
> > On Thu, 17 May 2018 15:18:14 +0200
> > Cédric Le Goater wrote:
> >
> >> Based on previous work done in skiboot, the physical mapping array
> >> helps in calculating the MMIO ranges of each controller depending on
> >> the chip id and the chip type. This is will be particularly useful for
> >> the P9 models which use less the XSCOM bus and rely more on MMIOs.
> >>
> >> A link on the chip is now necessary to calculate MMIO BARs and
> >> sizes. This is why such a link is introduced in the PSIHB model.
> >>
> >> Signed-off-by: Cédric Le Goater
> >> ---
> >> hw/ppc/pnv.c | 32 +
> >> hw/ppc/pnv_psi.c | 11 +-
> >> hw/ppc/pnv_xscom.c | 8
> >> include/hw/ppc/pnv.h | 58
> >> +---
> >> 4 files changed, 80 insertions(+), 29 deletions(-)
> >>
> >> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
> >> index 031488131629..330bf6f74810 100644
> >> --- a/hw/ppc/pnv.c
> >> +++ b/hw/ppc/pnv.c
> >> @@ -712,6 +712,16 @@ static uint32_t pnv_chip_core_pir_p9(PnvChip *chip,
> >> uint32_t core_id)
> >> */
> >> #define POWER9_CORE_MASK (0xffull)
> >>
> >> +/*
> >> + * POWER8 MMIOs
> >> + */
> >> +static const PnvPhysMapEntry pnv_chip_power8_phys_map[] = {
> >> +[PNV_MAP_XSCOM] = { 0x0003fc00ull, 0x0008ull
> >> },
> >> +[PNV_MAP_ICP] = { 0x00038000ull, 0x0010ull
> >> },
> >> +[PNV_MAP_PSIHB] = { 0x0003fffe8000ull, 0x0010ull
> >> },
> >> +[PNV_MAP_PSIHB_FSP] = { 0x0003ffe0ull, 0x0001ull
> >> },
> >> +};
> >> +
> >> static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data)
> >> {
> >> DeviceClass *dc = DEVICE_CLASS(klass);
> >> @@ -721,7 +731,7 @@ static void pnv_chip_power8e_class_init(ObjectClass
> >> *klass, void *data)
> >> k->chip_cfam_id = 0x221ef0498000ull; /* P8 Murano DD2.1 */
> >> k->cores_mask = POWER8E_CORE_MASK;
> >> k->core_pir = pnv_chip_core_pir_p8;
> >> -k->xscom_base = 0x003fc00ull;
> >> +k->phys_map = pnv_chip_power8_phys_map;
> >> dc->desc = "PowerNV Chip POWER8E";
> >> }
> >>
> >> @@ -734,7 +744,7 @@ static void pnv_chip_power8_class_init(ObjectClass
> >> *klass, void *data)
> >> k->chip_cfam_id = 0x220ea0498000ull; /* P8 Venice DD2.0 */
> >> k->cores_mask = POWER8_CORE_MASK;
> >> k->core_pir = pnv_chip_core_pir_p8;
> >> -k->xscom_base = 0x003fc00ull;
> >> +k->phys_map = pnv_chip_power8_phys_map;
> >> dc->desc = "PowerNV Chip POWER8";
> >> }
> >>
> >> @@ -747,10 +757,17 @@ static void
> >> pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data)
> >> k->chip_cfam_id = 0x120d30498000ull; /* P8 Naples DD1.0 */
> >> k->cores_mask = POWER8_CORE_MASK;
> >> k->core_pir = pnv_chip_core_pir_p8;
> >> -k->xscom_base = 0x003fc00ull;
> >> +k->phys_map = pnv_chip_power8_phys_map;
> >> dc->desc = "PowerNV Chip POWER8NVL";
> >> }
> >>
> >> +/*
> >> + * POWER9 MMIOs
> >> + */
> >> +static const PnvPhysMapEntry pnv_chip_power9_phys_map[] = {
> >> +[PNV_MAP_XSCOM] = { 0x000603fcull, 0x0400ull
> >> },
> >> +};
> >> +
> >> static void pnv_chip_power9_class_init(ObjectClass *klass, void *data)
> >> {
> >> DeviceClass *dc = DEVICE_CLASS(klass);
> >> @@ -760,7 +777,7 @@ static void pnv_chip_power9_class_init(ObjectClass
> >> *klass, void *data)
> >> k->chip_cfam_id = 0x220d10498000ull; /* P9 Nimbus DD2.0 */
> >> k->cores_mask = POWER9_CORE_MASK;
> >> k->core_pir = pnv_chip_core_pir_p9;
> >> -k->xscom_base = 0x00603fcull;
> >> +k->phys_map = pnv_chip_power9_phys_map;
> >> dc->desc = "PowerNV Chip POWER9";
> >> }
> >>
> >> @@ -797,15 +814,14 @@ static void pnv_chip_core_sanitize(PnvChip *chip,
> >> Error **errp)
> >> static void pnv_chip_init(Object *obj)
> >> {
> >> PnvChip *chip = PNV_CHIP(obj);
> >> -PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
> >> -
> >> -chip->xscom_base = pcc->xscom_base;
> >>
> >> object_initialize(&chip->lpc, sizeof(chip->lpc), TYPE_PNV_LPC);
> >> object_property_add_child(obj, "lpc", OBJECT(&chip->lpc), NULL);
> >>
> >> object_initialize(&chip->psi, sizeof(chip->psi), TYPE_PNV_PSI);
> >> object_property_add_child(obj, "psi", OBJECT(&chip->psi), NULL);
> >> +object_property_add_const_link(OBJECT(&chip->psi), "chip", obj,
> >> + &error_abort);
> >> object_property_add_const_link(OBJECT(&chip->psi), "xics",
> >> OBJECT(qdev_get_machine()),
> >> &error_abort);
> >>
> >> @@ -829,7 +845,7 @@ static void pnv_chip_icp_realize(PnvChip *chip, Error
> >> **errp)
> >> XICSFabric *xi = XICS_FABRIC(qdev_get_machine());
>
Re: [Qemu-devel] [PATCH] pnv: add a physical mapping array describing MMIO ranges in each chip
On 05/18/2018 11:00 AM, Greg Kurz wrote:
> On Thu, 17 May 2018 15:18:14 +0200
> Cédric Le Goater wrote:
>
>> Based on previous work done in skiboot, the physical mapping array
>> helps in calculating the MMIO ranges of each controller depending on
>> the chip id and the chip type. This is will be particularly useful for
>> the P9 models which use less the XSCOM bus and rely more on MMIOs.
>>
>> A link on the chip is now necessary to calculate MMIO BARs and
>> sizes. This is why such a link is introduced in the PSIHB model.
>>
>> Signed-off-by: Cédric Le Goater
>> ---
>> hw/ppc/pnv.c | 32 +
>> hw/ppc/pnv_psi.c | 11 +-
>> hw/ppc/pnv_xscom.c | 8
>> include/hw/ppc/pnv.h | 58
>> +---
>> 4 files changed, 80 insertions(+), 29 deletions(-)
>>
>> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
>> index 031488131629..330bf6f74810 100644
>> --- a/hw/ppc/pnv.c
>> +++ b/hw/ppc/pnv.c
>> @@ -712,6 +712,16 @@ static uint32_t pnv_chip_core_pir_p9(PnvChip *chip,
>> uint32_t core_id)
>> */
>> #define POWER9_CORE_MASK (0xffull)
>>
>> +/*
>> + * POWER8 MMIOs
>> + */
>> +static const PnvPhysMapEntry pnv_chip_power8_phys_map[] = {
>> +[PNV_MAP_XSCOM] = { 0x0003fc00ull, 0x0008ull },
>> +[PNV_MAP_ICP] = { 0x00038000ull, 0x0010ull },
>> +[PNV_MAP_PSIHB] = { 0x0003fffe8000ull, 0x0010ull },
>> +[PNV_MAP_PSIHB_FSP] = { 0x0003ffe0ull, 0x0001ull },
>> +};
>> +
>> static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data)
>> {
>> DeviceClass *dc = DEVICE_CLASS(klass);
>> @@ -721,7 +731,7 @@ static void pnv_chip_power8e_class_init(ObjectClass
>> *klass, void *data)
>> k->chip_cfam_id = 0x221ef0498000ull; /* P8 Murano DD2.1 */
>> k->cores_mask = POWER8E_CORE_MASK;
>> k->core_pir = pnv_chip_core_pir_p8;
>> -k->xscom_base = 0x003fc00ull;
>> +k->phys_map = pnv_chip_power8_phys_map;
>> dc->desc = "PowerNV Chip POWER8E";
>> }
>>
>> @@ -734,7 +744,7 @@ static void pnv_chip_power8_class_init(ObjectClass
>> *klass, void *data)
>> k->chip_cfam_id = 0x220ea0498000ull; /* P8 Venice DD2.0 */
>> k->cores_mask = POWER8_CORE_MASK;
>> k->core_pir = pnv_chip_core_pir_p8;
>> -k->xscom_base = 0x003fc00ull;
>> +k->phys_map = pnv_chip_power8_phys_map;
>> dc->desc = "PowerNV Chip POWER8";
>> }
>>
>> @@ -747,10 +757,17 @@ static void pnv_chip_power8nvl_class_init(ObjectClass
>> *klass, void *data)
>> k->chip_cfam_id = 0x120d30498000ull; /* P8 Naples DD1.0 */
>> k->cores_mask = POWER8_CORE_MASK;
>> k->core_pir = pnv_chip_core_pir_p8;
>> -k->xscom_base = 0x003fc00ull;
>> +k->phys_map = pnv_chip_power8_phys_map;
>> dc->desc = "PowerNV Chip POWER8NVL";
>> }
>>
>> +/*
>> + * POWER9 MMIOs
>> + */
>> +static const PnvPhysMapEntry pnv_chip_power9_phys_map[] = {
>> +[PNV_MAP_XSCOM] = { 0x000603fcull, 0x0400ull },
>> +};
>> +
>> static void pnv_chip_power9_class_init(ObjectClass *klass, void *data)
>> {
>> DeviceClass *dc = DEVICE_CLASS(klass);
>> @@ -760,7 +777,7 @@ static void pnv_chip_power9_class_init(ObjectClass
>> *klass, void *data)
>> k->chip_cfam_id = 0x220d10498000ull; /* P9 Nimbus DD2.0 */
>> k->cores_mask = POWER9_CORE_MASK;
>> k->core_pir = pnv_chip_core_pir_p9;
>> -k->xscom_base = 0x00603fcull;
>> +k->phys_map = pnv_chip_power9_phys_map;
>> dc->desc = "PowerNV Chip POWER9";
>> }
>>
>> @@ -797,15 +814,14 @@ static void pnv_chip_core_sanitize(PnvChip *chip,
>> Error **errp)
>> static void pnv_chip_init(Object *obj)
>> {
>> PnvChip *chip = PNV_CHIP(obj);
>> -PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
>> -
>> -chip->xscom_base = pcc->xscom_base;
>>
>> object_initialize(&chip->lpc, sizeof(chip->lpc), TYPE_PNV_LPC);
>> object_property_add_child(obj, "lpc", OBJECT(&chip->lpc), NULL);
>>
>> object_initialize(&chip->psi, sizeof(chip->psi), TYPE_PNV_PSI);
>> object_property_add_child(obj, "psi", OBJECT(&chip->psi), NULL);
>> +object_property_add_const_link(OBJECT(&chip->psi), "chip", obj,
>> + &error_abort);
>> object_property_add_const_link(OBJECT(&chip->psi), "xics",
>> OBJECT(qdev_get_machine()),
>> &error_abort);
>>
>> @@ -829,7 +845,7 @@ static void pnv_chip_icp_realize(PnvChip *chip, Error
>> **errp)
>> XICSFabric *xi = XICS_FABRIC(qdev_get_machine());
>>
>> name = g_strdup_printf("icp-%x", chip->chip_id);
>> -memory_region_init(&chip->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE);
>> +memory_region_init(&chip->icp_mmio, OBJECT(chip), name,
>> PNV_ICP_SIZE(chip));
>> sysbus_init_mmio(SYS_BUS_DEVICE(chip), &chip->icp_mmio);
>> g_free(name);
>>
>> di
Re: [Qemu-devel] [PATCH] pnv: add a physical mapping array describing MMIO ranges in each chip
On Thu, 17 May 2018 15:18:14 +0200
Cédric Le Goater wrote:
> Based on previous work done in skiboot, the physical mapping array
> helps in calculating the MMIO ranges of each controller depending on
> the chip id and the chip type. This is will be particularly useful for
> the P9 models which use less the XSCOM bus and rely more on MMIOs.
>
> A link on the chip is now necessary to calculate MMIO BARs and
> sizes. This is why such a link is introduced in the PSIHB model.
>
> Signed-off-by: Cédric Le Goater
> ---
> hw/ppc/pnv.c | 32 +
> hw/ppc/pnv_psi.c | 11 +-
> hw/ppc/pnv_xscom.c | 8
> include/hw/ppc/pnv.h | 58
> +---
> 4 files changed, 80 insertions(+), 29 deletions(-)
>
> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
> index 031488131629..330bf6f74810 100644
> --- a/hw/ppc/pnv.c
> +++ b/hw/ppc/pnv.c
> @@ -712,6 +712,16 @@ static uint32_t pnv_chip_core_pir_p9(PnvChip *chip,
> uint32_t core_id)
> */
> #define POWER9_CORE_MASK (0xffull)
>
> +/*
> + * POWER8 MMIOs
> + */
> +static const PnvPhysMapEntry pnv_chip_power8_phys_map[] = {
> +[PNV_MAP_XSCOM] = { 0x0003fc00ull, 0x0008ull },
> +[PNV_MAP_ICP] = { 0x00038000ull, 0x0010ull },
> +[PNV_MAP_PSIHB] = { 0x0003fffe8000ull, 0x0010ull },
> +[PNV_MAP_PSIHB_FSP] = { 0x0003ffe0ull, 0x0001ull },
> +};
> +
> static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data)
> {
> DeviceClass *dc = DEVICE_CLASS(klass);
> @@ -721,7 +731,7 @@ static void pnv_chip_power8e_class_init(ObjectClass
> *klass, void *data)
> k->chip_cfam_id = 0x221ef0498000ull; /* P8 Murano DD2.1 */
> k->cores_mask = POWER8E_CORE_MASK;
> k->core_pir = pnv_chip_core_pir_p8;
> -k->xscom_base = 0x003fc00ull;
> +k->phys_map = pnv_chip_power8_phys_map;
> dc->desc = "PowerNV Chip POWER8E";
> }
>
> @@ -734,7 +744,7 @@ static void pnv_chip_power8_class_init(ObjectClass
> *klass, void *data)
> k->chip_cfam_id = 0x220ea0498000ull; /* P8 Venice DD2.0 */
> k->cores_mask = POWER8_CORE_MASK;
> k->core_pir = pnv_chip_core_pir_p8;
> -k->xscom_base = 0x003fc00ull;
> +k->phys_map = pnv_chip_power8_phys_map;
> dc->desc = "PowerNV Chip POWER8";
> }
>
> @@ -747,10 +757,17 @@ static void pnv_chip_power8nvl_class_init(ObjectClass
> *klass, void *data)
> k->chip_cfam_id = 0x120d30498000ull; /* P8 Naples DD1.0 */
> k->cores_mask = POWER8_CORE_MASK;
> k->core_pir = pnv_chip_core_pir_p8;
> -k->xscom_base = 0x003fc00ull;
> +k->phys_map = pnv_chip_power8_phys_map;
> dc->desc = "PowerNV Chip POWER8NVL";
> }
>
> +/*
> + * POWER9 MMIOs
> + */
> +static const PnvPhysMapEntry pnv_chip_power9_phys_map[] = {
> +[PNV_MAP_XSCOM] = { 0x000603fcull, 0x0400ull },
> +};
> +
> static void pnv_chip_power9_class_init(ObjectClass *klass, void *data)
> {
> DeviceClass *dc = DEVICE_CLASS(klass);
> @@ -760,7 +777,7 @@ static void pnv_chip_power9_class_init(ObjectClass
> *klass, void *data)
> k->chip_cfam_id = 0x220d10498000ull; /* P9 Nimbus DD2.0 */
> k->cores_mask = POWER9_CORE_MASK;
> k->core_pir = pnv_chip_core_pir_p9;
> -k->xscom_base = 0x00603fcull;
> +k->phys_map = pnv_chip_power9_phys_map;
> dc->desc = "PowerNV Chip POWER9";
> }
>
> @@ -797,15 +814,14 @@ static void pnv_chip_core_sanitize(PnvChip *chip, Error
> **errp)
> static void pnv_chip_init(Object *obj)
> {
> PnvChip *chip = PNV_CHIP(obj);
> -PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
> -
> -chip->xscom_base = pcc->xscom_base;
>
> object_initialize(&chip->lpc, sizeof(chip->lpc), TYPE_PNV_LPC);
> object_property_add_child(obj, "lpc", OBJECT(&chip->lpc), NULL);
>
> object_initialize(&chip->psi, sizeof(chip->psi), TYPE_PNV_PSI);
> object_property_add_child(obj, "psi", OBJECT(&chip->psi), NULL);
> +object_property_add_const_link(OBJECT(&chip->psi), "chip", obj,
> + &error_abort);
> object_property_add_const_link(OBJECT(&chip->psi), "xics",
> OBJECT(qdev_get_machine()), &error_abort);
>
> @@ -829,7 +845,7 @@ static void pnv_chip_icp_realize(PnvChip *chip, Error
> **errp)
> XICSFabric *xi = XICS_FABRIC(qdev_get_machine());
>
> name = g_strdup_printf("icp-%x", chip->chip_id);
> -memory_region_init(&chip->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE);
> +memory_region_init(&chip->icp_mmio, OBJECT(chip), name,
> PNV_ICP_SIZE(chip));
> sysbus_init_mmio(SYS_BUS_DEVICE(chip), &chip->icp_mmio);
> g_free(name);
>
> diff --git a/hw/ppc/pnv_psi.c b/hw/ppc/pnv_psi.c
> index 5b969127c303..dd7707b971c9 100644
> --- a/hw/ppc/pnv_psi.c
> +++ b/hw/ppc/pnv_psi.c
> @@ -465,6 +465,15 @@ static
Re: [Qemu-devel] [PATCH] pnv: add a physical mapping array describing MMIO ranges in each chip
On 05/17/2018 03:53 PM, Philippe Mathieu-Daudé wrote:
> Hi Cédric,
>
> On 05/17/2018 10:18 AM, Cédric Le Goater wrote:
>> Based on previous work done in skiboot, the physical mapping array
>> helps in calculating the MMIO ranges of each controller depending on
>> the chip id and the chip type. This is will be particularly useful for
>> the P9 models which use less the XSCOM bus and rely more on MMIOs.
>>
>> A link on the chip is now necessary to calculate MMIO BARs and
>> sizes. This is why such a link is introduced in the PSIHB model.
>>
>> Signed-off-by: Cédric Le Goater
>> ---
>> hw/ppc/pnv.c | 32 +
>> hw/ppc/pnv_psi.c | 11 +-
>> hw/ppc/pnv_xscom.c | 8
>> include/hw/ppc/pnv.h | 58
>> +---
>
> I recommend you to use the scripts/git.orderfile to make this review easier.
ok.
>
>> 4 files changed, 80 insertions(+), 29 deletions(-)
>>
>> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
>> index 031488131629..330bf6f74810 100644
>> --- a/hw/ppc/pnv.c
>> +++ b/hw/ppc/pnv.c
>> @@ -712,6 +712,16 @@ static uint32_t pnv_chip_core_pir_p9(PnvChip *chip,
>> uint32_t core_id)
>> */
>> #define POWER9_CORE_MASK (0xffull)
>>
>> +/*
>> + * POWER8 MMIOs
>> + */
>> +static const PnvPhysMapEntry pnv_chip_power8_phys_map[] = {
>> +[PNV_MAP_XSCOM] = { 0x0003fc00ull, 0x0008ull },
>> +[PNV_MAP_ICP] = { 0x00038000ull, 0x0010ull },
>> +[PNV_MAP_PSIHB] = { 0x0003fffe8000ull, 0x0010ull },
>> +[PNV_MAP_PSIHB_FSP] = { 0x0003ffe0ull, 0x0001ull },
>> +};
>> +
>> static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data)
>> {
>> DeviceClass *dc = DEVICE_CLASS(klass);
>> @@ -721,7 +731,7 @@ static void pnv_chip_power8e_class_init(ObjectClass
>> *klass, void *data)
>> k->chip_cfam_id = 0x221ef0498000ull; /* P8 Murano DD2.1 */
>> k->cores_mask = POWER8E_CORE_MASK;
>> k->core_pir = pnv_chip_core_pir_p8;
>> -k->xscom_base = 0x003fc00ull;
>> +k->phys_map = pnv_chip_power8_phys_map;
>> dc->desc = "PowerNV Chip POWER8E";
>> }
>>
>> @@ -734,7 +744,7 @@ static void pnv_chip_power8_class_init(ObjectClass
>> *klass, void *data)
>> k->chip_cfam_id = 0x220ea0498000ull; /* P8 Venice DD2.0 */
>> k->cores_mask = POWER8_CORE_MASK;
>> k->core_pir = pnv_chip_core_pir_p8;
>> -k->xscom_base = 0x003fc00ull;
>> +k->phys_map = pnv_chip_power8_phys_map;
>> dc->desc = "PowerNV Chip POWER8";
>> }
>>
>> @@ -747,10 +757,17 @@ static void pnv_chip_power8nvl_class_init(ObjectClass
>> *klass, void *data)
>> k->chip_cfam_id = 0x120d30498000ull; /* P8 Naples DD1.0 */
>> k->cores_mask = POWER8_CORE_MASK;
>> k->core_pir = pnv_chip_core_pir_p8;
>> -k->xscom_base = 0x003fc00ull;
>> +k->phys_map = pnv_chip_power8_phys_map;
>> dc->desc = "PowerNV Chip POWER8NVL";
>> }
>>
>> +/*
>> + * POWER9 MMIOs
>> + */
>> +static const PnvPhysMapEntry pnv_chip_power9_phys_map[] = {
>> +[PNV_MAP_XSCOM] = { 0x000603fcull, 0x0400ull },
>> +};
>> +
>> static void pnv_chip_power9_class_init(ObjectClass *klass, void *data)
>> {
>> DeviceClass *dc = DEVICE_CLASS(klass);
>> @@ -760,7 +777,7 @@ static void pnv_chip_power9_class_init(ObjectClass
>> *klass, void *data)
>> k->chip_cfam_id = 0x220d10498000ull; /* P9 Nimbus DD2.0 */
>> k->cores_mask = POWER9_CORE_MASK;
>> k->core_pir = pnv_chip_core_pir_p9;
>> -k->xscom_base = 0x00603fcull;
>> +k->phys_map = pnv_chip_power9_phys_map;
>> dc->desc = "PowerNV Chip POWER9";
>> }
>>
>> @@ -797,15 +814,14 @@ static void pnv_chip_core_sanitize(PnvChip *chip,
>> Error **errp)
>> static void pnv_chip_init(Object *obj)
>> {
>> PnvChip *chip = PNV_CHIP(obj);
>> -PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
>> -
>> -chip->xscom_base = pcc->xscom_base;
>>
>> object_initialize(&chip->lpc, sizeof(chip->lpc), TYPE_PNV_LPC);
>> object_property_add_child(obj, "lpc", OBJECT(&chip->lpc), NULL);
>>
>> object_initialize(&chip->psi, sizeof(chip->psi), TYPE_PNV_PSI);
>> object_property_add_child(obj, "psi", OBJECT(&chip->psi), NULL);
>> +object_property_add_const_link(OBJECT(&chip->psi), "chip", obj,
>> + &error_abort);
>> object_property_add_const_link(OBJECT(&chip->psi), "xics",
>> OBJECT(qdev_get_machine()),
>> &error_abort);
>>
>> @@ -829,7 +845,7 @@ static void pnv_chip_icp_realize(PnvChip *chip, Error
>> **errp)
>> XICSFabric *xi = XICS_FABRIC(qdev_get_machine());
>>
>> name = g_strdup_printf("icp-%x", chip->chip_id);
>> -memory_region_init(&chip->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE);
>> +memory_region_init(&chip->icp_mmio, OBJECT(chip), name,
>> PNV_ICP_SIZE(ch
Re: [Qemu-devel] [PATCH] pnv: add a physical mapping array describing MMIO ranges in each chip
Hi Cédric,
On 05/17/2018 10:18 AM, Cédric Le Goater wrote:
> Based on previous work done in skiboot, the physical mapping array
> helps in calculating the MMIO ranges of each controller depending on
> the chip id and the chip type. This is will be particularly useful for
> the P9 models which use less the XSCOM bus and rely more on MMIOs.
>
> A link on the chip is now necessary to calculate MMIO BARs and
> sizes. This is why such a link is introduced in the PSIHB model.
>
> Signed-off-by: Cédric Le Goater
> ---
> hw/ppc/pnv.c | 32 +
> hw/ppc/pnv_psi.c | 11 +-
> hw/ppc/pnv_xscom.c | 8
> include/hw/ppc/pnv.h | 58
> +---
I recommend you to use the scripts/git.orderfile to make this review easier.
> 4 files changed, 80 insertions(+), 29 deletions(-)
>
> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
> index 031488131629..330bf6f74810 100644
> --- a/hw/ppc/pnv.c
> +++ b/hw/ppc/pnv.c
> @@ -712,6 +712,16 @@ static uint32_t pnv_chip_core_pir_p9(PnvChip *chip,
> uint32_t core_id)
> */
> #define POWER9_CORE_MASK (0xffull)
>
> +/*
> + * POWER8 MMIOs
> + */
> +static const PnvPhysMapEntry pnv_chip_power8_phys_map[] = {
> +[PNV_MAP_XSCOM] = { 0x0003fc00ull, 0x0008ull },
> +[PNV_MAP_ICP] = { 0x00038000ull, 0x0010ull },
> +[PNV_MAP_PSIHB] = { 0x0003fffe8000ull, 0x0010ull },
> +[PNV_MAP_PSIHB_FSP] = { 0x0003ffe0ull, 0x0001ull },
> +};
> +
> static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data)
> {
> DeviceClass *dc = DEVICE_CLASS(klass);
> @@ -721,7 +731,7 @@ static void pnv_chip_power8e_class_init(ObjectClass
> *klass, void *data)
> k->chip_cfam_id = 0x221ef0498000ull; /* P8 Murano DD2.1 */
> k->cores_mask = POWER8E_CORE_MASK;
> k->core_pir = pnv_chip_core_pir_p8;
> -k->xscom_base = 0x003fc00ull;
> +k->phys_map = pnv_chip_power8_phys_map;
> dc->desc = "PowerNV Chip POWER8E";
> }
>
> @@ -734,7 +744,7 @@ static void pnv_chip_power8_class_init(ObjectClass
> *klass, void *data)
> k->chip_cfam_id = 0x220ea0498000ull; /* P8 Venice DD2.0 */
> k->cores_mask = POWER8_CORE_MASK;
> k->core_pir = pnv_chip_core_pir_p8;
> -k->xscom_base = 0x003fc00ull;
> +k->phys_map = pnv_chip_power8_phys_map;
> dc->desc = "PowerNV Chip POWER8";
> }
>
> @@ -747,10 +757,17 @@ static void pnv_chip_power8nvl_class_init(ObjectClass
> *klass, void *data)
> k->chip_cfam_id = 0x120d30498000ull; /* P8 Naples DD1.0 */
> k->cores_mask = POWER8_CORE_MASK;
> k->core_pir = pnv_chip_core_pir_p8;
> -k->xscom_base = 0x003fc00ull;
> +k->phys_map = pnv_chip_power8_phys_map;
> dc->desc = "PowerNV Chip POWER8NVL";
> }
>
> +/*
> + * POWER9 MMIOs
> + */
> +static const PnvPhysMapEntry pnv_chip_power9_phys_map[] = {
> +[PNV_MAP_XSCOM] = { 0x000603fcull, 0x0400ull },
> +};
> +
> static void pnv_chip_power9_class_init(ObjectClass *klass, void *data)
> {
> DeviceClass *dc = DEVICE_CLASS(klass);
> @@ -760,7 +777,7 @@ static void pnv_chip_power9_class_init(ObjectClass
> *klass, void *data)
> k->chip_cfam_id = 0x220d10498000ull; /* P9 Nimbus DD2.0 */
> k->cores_mask = POWER9_CORE_MASK;
> k->core_pir = pnv_chip_core_pir_p9;
> -k->xscom_base = 0x00603fcull;
> +k->phys_map = pnv_chip_power9_phys_map;
> dc->desc = "PowerNV Chip POWER9";
> }
>
> @@ -797,15 +814,14 @@ static void pnv_chip_core_sanitize(PnvChip *chip, Error
> **errp)
> static void pnv_chip_init(Object *obj)
> {
> PnvChip *chip = PNV_CHIP(obj);
> -PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
> -
> -chip->xscom_base = pcc->xscom_base;
>
> object_initialize(&chip->lpc, sizeof(chip->lpc), TYPE_PNV_LPC);
> object_property_add_child(obj, "lpc", OBJECT(&chip->lpc), NULL);
>
> object_initialize(&chip->psi, sizeof(chip->psi), TYPE_PNV_PSI);
> object_property_add_child(obj, "psi", OBJECT(&chip->psi), NULL);
> +object_property_add_const_link(OBJECT(&chip->psi), "chip", obj,
> + &error_abort);
> object_property_add_const_link(OBJECT(&chip->psi), "xics",
> OBJECT(qdev_get_machine()), &error_abort);
>
> @@ -829,7 +845,7 @@ static void pnv_chip_icp_realize(PnvChip *chip, Error
> **errp)
> XICSFabric *xi = XICS_FABRIC(qdev_get_machine());
>
> name = g_strdup_printf("icp-%x", chip->chip_id);
> -memory_region_init(&chip->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE);
> +memory_region_init(&chip->icp_mmio, OBJECT(chip), name,
> PNV_ICP_SIZE(chip));
> sysbus_init_mmio(SYS_BUS_DEVICE(chip), &chip->icp_mmio);
> g_free(name);
>
> diff --git a/hw/ppc/pnv_psi.c b/hw/ppc/pnv_psi.c
> index 5b969127c303..dd7707b971c9 100644
>
