On 03/13/2018 11:39 AM, Paolo Bonzini wrote:
> Signed-off-by: Paolo Bonzini
> ---
> include/standard-headers/linux/input-event-codes.h | 1 +
> include/standard-headers/linux/pci_regs.h | 30 +-
> include/standard-headers/linux/virtio_gpu.h| 1 -
> include/standard-headers/linux/virtio_net.h| 13 +
> include/standard-headers/linux/virtio_ring.h | 2 +-
> include/standard-headers/rdma/vmw_pvrdma-abi.h | 13 +-
> linux-headers/asm-powerpc/kvm.h| 2 +
> linux-headers/asm-powerpc/unistd.h | 3 +
> linux-headers/asm-s390/unistd.h| 401
> +
> linux-headers/asm-s390/unistd_32.h | 364 +++
> linux-headers/asm-s390/unistd_64.h | 331 +
> linux-headers/asm-x86/kvm_para.h | 5 +
> linux-headers/linux/kvm.h | 92 +
> linux-headers/linux/psci.h | 3 +
> linux-headers/linux/vfio.h | 72
> scripts/update-linux-headers.sh| 2 +
> 16 files changed, 918 insertions(+), 417 deletions(-)
> create mode 100644 linux-headers/asm-s390/unistd_32.h
> create mode 100644 linux-headers/asm-s390/unistd_64.h
s390 part look sane.
Acked-by: Christian Borntraeger
>
> diff --git a/include/standard-headers/linux/input-event-codes.h
> b/include/standard-headers/linux/input-event-codes.h
> index 79841b5..9e6a8ba 100644
> --- a/include/standard-headers/linux/input-event-codes.h
> +++ b/include/standard-headers/linux/input-event-codes.h
> @@ -594,6 +594,7 @@
> #define BTN_DPAD_RIGHT 0x223
>
> #define KEY_ALS_TOGGLE 0x230 /* Ambient light sensor */
> +#define KEY_ROTATE_LOCK_TOGGLE 0x231 /* Display rotation lock */
>
> #define KEY_BUTTONCONFIG 0x240 /* AL Button Configuration */
> #define KEY_TASKMANAGER 0x241 /* AL Task/Project Manager */
> diff --git a/include/standard-headers/linux/pci_regs.h
> b/include/standard-headers/linux/pci_regs.h
> index 70c2b2a..0c79eac 100644
> --- a/include/standard-headers/linux/pci_regs.h
> +++ b/include/standard-headers/linux/pci_regs.h
> @@ -622,15 +622,19 @@
> * safely.
> */
> #define PCI_EXP_DEVCAP2 36 /* Device Capabilities 2 */
> +#define PCI_EXP_DEVCAP2_COMP_TMOUT_DIS 0x0010 /* Completion
> Timeout Disable supported */
> #define PCI_EXP_DEVCAP2_ARI 0x0020 /* Alternative Routing-ID */
> #define PCI_EXP_DEVCAP2_ATOMIC_ROUTE0x0040 /* Atomic Op routing
> */
> -#define PCI_EXP_DEVCAP2_ATOMIC_COMP640x0100 /* Atomic 64-bit
> compare */
> +#define PCI_EXP_DEVCAP2_ATOMIC_COMP32 0x0080 /* 32b AtomicOp
> completion */
> +#define PCI_EXP_DEVCAP2_ATOMIC_COMP64 0x0100 /* 64b AtomicOp
> completion */
> +#define PCI_EXP_DEVCAP2_ATOMIC_COMP128 0x0200 /* 128b AtomicOp
> completion */
> #define PCI_EXP_DEVCAP2_LTR 0x0800 /* Latency tolerance
> reporting */
> #define PCI_EXP_DEVCAP2_OBFF_MASK 0x000c /* OBFF support mechanism */
> #define PCI_EXP_DEVCAP2_OBFF_MSG0x0004 /* New message signaling */
> #define PCI_EXP_DEVCAP2_OBFF_WAKE 0x0008 /* Re-use WAKE# for OBFF */
> #define PCI_EXP_DEVCTL2 40 /* Device Control 2 */
> #define PCI_EXP_DEVCTL2_COMP_TIMEOUT0x000f /* Completion Timeout
> Value */
> +#define PCI_EXP_DEVCTL2_COMP_TMOUT_DIS 0x0010 /* Completion Timeout
> Disable */
> #define PCI_EXP_DEVCTL2_ARI 0x0020 /* Alternative Routing-ID */
> #define PCI_EXP_DEVCTL2_ATOMIC_REQ 0x0040 /* Set Atomic requests */
> #define PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK 0x0080 /* Block atomic egress */
> @@ -966,26 +970,28 @@
>
> /* Downstream Port Containment */
> #define PCI_EXP_DPC_CAP 4 /* DPC Capability */
> -#define PCI_EXP_DPC_IRQ 0x1f/* DPC Interrupt
> Message Number */
> -#define PCI_EXP_DPC_CAP_RP_EXT 0x20/* Root Port Extensions
> for DPC */
> -#define PCI_EXP_DPC_CAP_POISONED_TLP0x40/* Poisoned TLP Egress
> Blocking Supported */
> -#define PCI_EXP_DPC_CAP_SW_TRIGGER 0x80/* Software Triggering
> Supported */
> -#define PCI_EXP_DPC_RP_PIO_LOG_SIZE 0xF00 /* RP PIO log size */
> +#define PCI_EXP_DPC_IRQ 0x001F /* Interrupt Message
> Number */
> +#define PCI_EXP_DPC_CAP_RP_EXT 0x0020 /* Root Port Extensions
> */
> +#define PCI_EXP_DPC_CAP_POISONED_TLP0x0040 /* Poisoned TLP Egress
> Blocking Supported */
> +#define PCI_EXP_DPC_CAP_SW_TRIGGER 0x0080 /* Software Triggering
> Supported */
> +#define PCI_EXP_DPC_RP_PIO_LOG_SIZE 0x0F00 /* RP PIO Log Size */
> #define PCI_EXP_DPC_CAP_DL_ACTIVE 0x1000 /* ERR_COR signal on DL_Active
> supported