On 10/11/2016 10:12 AM, Peter Maydell wrote:
> On 11 October 2016 at 16:51, Thomas Hanson wrote:
>> On 5 October 2016 at 16:01, Peter Maydell wrote:
>>> It matches the style of the rest of the code which generally
>>> prefers to convert
On 11 October 2016 at 16:51, Thomas Hanson wrote:
> On 5 October 2016 at 16:01, Peter Maydell wrote:
>> It matches the style of the rest of the code which generally
>> prefers to convert register numbers into TCGv earlier rather
>> than later
On 10/11/2016 10:51 AM, Thomas Hanson wrote:
As a separate issue, we now have functions to load the PC from an immediate
value and from a register. Where else could we legitimately load the PC from?
E.g. an internal cpu register holding an exception return address?
I don't know the
On 5 October 2016 at 16:01, Peter Maydell wrote:
> On 5 October 2016 at 14:53, Tom Hanson wrote:
> > On 09/29/2016 07:24 PM, Peter Maydell wrote:
> >> On 16 September 2016 at 10:34, Thomas Hanson
> wrote:
> >>> +void
On 5 October 2016 at 14:53, Tom Hanson wrote:
> On 09/29/2016 07:24 PM, Peter Maydell wrote:
>> On 16 September 2016 at 10:34, Thomas Hanson
>> wrote:
>>> +void gen_a64_set_pc_reg(DisasContext *s, unsigned int rn)
>>
>> I think it would be
On 09/29/2016 07:24 PM, Peter Maydell wrote:
> On 16 September 2016 at 10:34, Thomas Hanson wrote:
...
>> diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
>> index f5e29d2..4d6f951 100644
...
>> @@ -176,6 +177,58 @@ void gen_a64_set_pc_im(uint64_t
On 16 September 2016 at 10:34, Thomas Hanson wrote:
> gen_intermediate_code_a64() transfers TBI values from TB->flags to
> DisasContext structure.
>
> disas_uncond_b_reg() calls new function gen_a64_set_pc_reg() to handle BR,
> BLR and RET instructions.
>
>