Re: [Qemu-devel] [PATCH v1 1/1] configure: Add RISC-V host support
On 31 July 2018 at 10:30, Daniel P. Berrangé wrote: > On Mon, Jul 30, 2018 at 07:37:55PM +0100, Peter Maydell wrote: >> We should fix this somewhat nonsensical error message by >> completing the deprecate-and-drop cycle for this bit of >> configure, ie by outright rejecting attempts to build on >> host CPU types we don't recognize and support, the same >> way we do with unrecognized host OS types. > > Do you mean to imply that we should drop the TCG intepreter too, or do > you consider that something that makes it a supported host CPU ? TCG > intepretor essentially makes any host supportable, if we keep it. I would happily drop the TCG host interpreter, but I don't object in the short term to keeping it around (as an experimental thing for people who really want it for some reason). I do want to stop claiming we "support" host CPUs which we in practice don't, because the interpreter's performance is not good and it only works with a subset of host OS calling convention ABIs anyway. Either a host CPU architecture matters enough that we can put in the not-all-that-huge effort to support it properly, or it doesn't. I don't think it serves the (probably nearly zero) users trying to run QEMU on weird CPUs to produce a sort-of-but-not-really-working setup which we'll then disclaim any interest in if they do try to report problems to us. thanks -- PMM
Re: [Qemu-devel] [PATCH v1 1/1] configure: Add RISC-V host support
On Mon, Jul 30, 2018 at 07:37:55PM +0100, Peter Maydell wrote: > On 30 July 2018 at 19:20, Philippe Mathieu-Daudé wrote: > > Before this patch: > > > > $ ./configure > > > > ERROR: Unsupported CPU = riscv64, try --enable-tcg-interpreter > > > > $ ./configure --enable-tcg-interpreter > > Unsupported CPU = riscv64, will use TCG with TCI (experimental) > > > > [...] > > > > WARNING: SUPPORT FOR THIS HOST CPU WILL GO AWAY IN FUTURE RELEASES! > > > > It is unlikely the RISC-V port goes away in the next future releases :) > > ...but it is not supported as a *host* CPU. > > We should fix this somewhat nonsensical error message by > completing the deprecate-and-drop cycle for this bit of > configure, ie by outright rejecting attempts to build on > host CPU types we don't recognize and support, the same > way we do with unrecognized host OS types. Do you mean to imply that we should drop the TCG intepreter too, or do you consider that something that makes it a supported host CPU ? TCG intepretor essentially makes any host supportable, if we keep it. Regards, Daniel -- |: https://berrange.com -o-https://www.flickr.com/photos/dberrange :| |: https://libvirt.org -o-https://fstop138.berrange.com :| |: https://entangle-photo.org-o-https://www.instagram.com/dberrange :|
Re: [Qemu-devel] [PATCH v1 1/1] configure: Add RISC-V host support
On 30 July 2018 at 19:20, Philippe Mathieu-Daudé wrote: > Before this patch: > > $ ./configure > > ERROR: Unsupported CPU = riscv64, try --enable-tcg-interpreter > > $ ./configure --enable-tcg-interpreter > Unsupported CPU = riscv64, will use TCG with TCI (experimental) > > [...] > > WARNING: SUPPORT FOR THIS HOST CPU WILL GO AWAY IN FUTURE RELEASES! > It is unlikely the RISC-V port goes away in the next future releases :) ...but it is not supported as a *host* CPU. We should fix this somewhat nonsensical error message by completing the deprecate-and-drop cycle for this bit of configure, ie by outright rejecting attempts to build on host CPU types we don't recognize and support, the same way we do with unrecognized host OS types. thanks -- PMM
Re: [Qemu-devel] [PATCH v1 1/1] configure: Add RISC-V host support
On 30 July 2018 at 18:24, Alistair Francis wrote: > On Sun, Jul 29, 2018 at 4:28 AM, Peter Maydell > wrote: >>> Another piece that even Michael Clark does not have is >>> linux-user/host/*/safe-syscall.S. >> >> It might be nice to complete the safe-syscall stuff for all hosts, >> and then remove the fallback that lets you build an unreliable >> linux-user binary without it... > > At the moment though QEMU won't build with Linux user. So some work is > required just to get the build working. Right -- it's not really sufficient to just change configure. I'd rather see: (a) a proper backend for any host CPU type we actually care about, which is what Michael's work is doing (b) support for the various per-host-arch things that are needed like the safe-syscall shim (c) QEMU's build infrastructure guiding the process of implementing both of those, by making it a build failure to not provide all the set of things, rather than producing a configuration that will build but not work reliably thanks -- PMM
Re: [Qemu-devel] [PATCH v1 1/1] configure: Add RISC-V host support
On 07/27/2018 08:49 PM, Alistair Francis wrote:
> Allow QEMU to be built to run on a RISC-V host.
>
> QEMU does not yet have a RISC-V TCG or user mode target port, but
> running other architectures on RISC-V using TCI does work.
>
> Signed-off-by: Alistair Francis
> ---
> configure | 18 +-
> 1 file changed, 17 insertions(+), 1 deletion(-)
>
> diff --git a/configure b/configure
> index 2a7796ea80..c3ff3ae146 100755
> --- a/configure
> +++ b/configure
> @@ -606,6 +606,16 @@ EOF
>compile_object
> }
>
> +check_define_value() {
> +cat > $TMPC < +#if (($1) != ($2))
> +#error $1 != ($2)
> +#endif
> +int main(void) { return 0; }
> +EOF
> + compile_object
> +}
> +
> check_include() {
> cat > $TMPC < #include <$1>
> @@ -704,6 +714,12 @@ elif check_define __arm__ ; then
>cpu="arm"
> elif check_define __aarch64__ ; then
>cpu="aarch64"
> +elif check_define __riscv ; then
> + if check_define_value __riscv_xlen 64 ; then
> +cpu="riscv64"
> + else
> +cpu="riscv32"
> + fi
> else
>cpu=$(uname -m)
> fi
> @@ -712,7 +728,7 @@ ARCH=
> # Normalise host CPU name and set ARCH.
> # Note that this case should only have supported host CPUs, not guests.
> case "$cpu" in
> - ppc|ppc64|s390|s390x|sparc64|x32)
> + ppc|ppc64|s390|s390x|sparc64|x32|riscv32|riscv64)
> cpu="$cpu"
> supported_cpu="yes"
> eval "cross_cc_${cpu}=\$host_cc"
>
Before this patch:
$ ./configure
ERROR: Unsupported CPU = riscv64, try --enable-tcg-interpreter
$ ./configure --enable-tcg-interpreter
Unsupported CPU = riscv64, will use TCG with TCI (experimental)
[...]
WARNING: SUPPORT FOR THIS HOST CPU WILL GO AWAY IN FUTURE RELEASES!
CPU host architecture riscv64 support is not currently maintained.
The QEMU project intends to remove support for this host CPU in
a future release if nobody volunteers to maintain it and to
provide a build host for our continuous integration setup.
configure has succeeded and you can continue to build, but
if you care about QEMU on this platform you should contact
us upstream at qemu-devel@nongnu.org.
It is unlikely the RISC-V port goes away in the next future releases :)
With this patch we can now build/use QEMU tools such qemu-img qemu-io
qemu-nbd ivshmem-client ivshmem-server scsi/qemu-pr-helper
qemu-bridge-helper qemu-keymap fsdev/virtfs-proxy-helper qemu-ga
vhost-user-scsi vhost-user-blk.
This is still not enough for system/user emulation, but this is
certainly an improvement, a starting point for the built system tests
(we have other crippled targets such TriCore).
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Re: [Qemu-devel] [PATCH v1 1/1] configure: Add RISC-V host support
On Sun, Jul 29, 2018 at 4:28 AM, Peter Maydell wrote: > On 28 July 2018 at 17:36, Richard Henderson > wrote: >> On 07/27/2018 04:49 PM, Alistair Francis wrote: >>> Allow QEMU to be built to run on a RISC-V host. >>> >>> QEMU does not yet have a RISC-V TCG or user mode target port, but >>> running other architectures on RISC-V using TCI does work. >>> >>> Signed-off-by: Alistair Francis >>> --- >>> configure | 18 +- >>> 1 file changed, 17 insertions(+), 1 deletion(-) >> >> This is ok as far as it goes. >> >> Even for TCI, you need some more. >> >> At minimum, see Michael Clark's branch changes to accel/tcg/user-exec.c for >> host signal handling. While you can run *-softmmu without this, none of >> *-linux-user will work reliably. >> >> Another piece that even Michael Clark does not have is >> linux-user/host/*/safe-syscall.S. > > It might be nice to complete the safe-syscall stuff for all hosts, > and then remove the fallback that lets you build an unreliable > linux-user binary without it... At the moment though QEMU won't build with Linux user. So some work is required just to get the build working. Alistair > > thanks > -- PMM
Re: [Qemu-devel] [PATCH v1 1/1] configure: Add RISC-V host support
On 28 July 2018 at 17:36, Richard Henderson wrote: > On 07/27/2018 04:49 PM, Alistair Francis wrote: >> Allow QEMU to be built to run on a RISC-V host. >> >> QEMU does not yet have a RISC-V TCG or user mode target port, but >> running other architectures on RISC-V using TCI does work. >> >> Signed-off-by: Alistair Francis >> --- >> configure | 18 +- >> 1 file changed, 17 insertions(+), 1 deletion(-) > > This is ok as far as it goes. > > Even for TCI, you need some more. > > At minimum, see Michael Clark's branch changes to accel/tcg/user-exec.c for > host signal handling. While you can run *-softmmu without this, none of > *-linux-user will work reliably. > > Another piece that even Michael Clark does not have is > linux-user/host/*/safe-syscall.S. It might be nice to complete the safe-syscall stuff for all hosts, and then remove the fallback that lets you build an unreliable linux-user binary without it... thanks -- PMM
Re: [Qemu-devel] [PATCH v1 1/1] configure: Add RISC-V host support
On 07/27/2018 04:49 PM, Alistair Francis wrote: > Allow QEMU to be built to run on a RISC-V host. > > QEMU does not yet have a RISC-V TCG or user mode target port, but > running other architectures on RISC-V using TCI does work. > > Signed-off-by: Alistair Francis > --- > configure | 18 +- > 1 file changed, 17 insertions(+), 1 deletion(-) This is ok as far as it goes. Even for TCI, you need some more. At minimum, see Michael Clark's branch changes to accel/tcg/user-exec.c for host signal handling. While you can run *-softmmu without this, none of *-linux-user will work reliably. Another piece that even Michael Clark does not have is linux-user/host/*/safe-syscall.S. r~
Re: [Qemu-devel] [PATCH v1 1/1] configure: Add RISC-V host support
On Sat, Jul 28, 2018 at 11:49 AM, Alistair Francis wrote:
> Allow QEMU to be built to run on a RISC-V host.
>
> QEMU does not yet have a RISC-V TCG or user mode target port, but
> running other architectures on RISC-V using TCI does work.
>
There is this RISC-V TCG backend here:
https://github.com/riscv/riscv-qemu/tree/wip-riscv-tcg-backend
I realized I had not sent an update to the list. There is a working TCG
backend for RISC-V:
- I've so far tested it with user-mode translation only.
- It does not support large guests e.g. 64-bit hosts on riscv32.
- The softmmu implementation is there but needs testing.
- Some things are missing, e.g. memory fences. big-endian support
You might find some other relevant changes in the configure hunks in the
patch. IIRC there were a few changes to configure, one of them was to get
the riscv disassembler working.
Signed-off-by: Alistair Francis
> ---
> configure | 18 +-
> 1 file changed, 17 insertions(+), 1 deletion(-)
>
> diff --git a/configure b/configure
> index 2a7796ea80..c3ff3ae146 100755
> --- a/configure
> +++ b/configure
> @@ -606,6 +606,16 @@ EOF
>compile_object
> }
>
> +check_define_value() {
> +cat > $TMPC < +#if (($1) != ($2))
> +#error $1 != ($2)
> +#endif
> +int main(void) { return 0; }
> +EOF
> + compile_object
> +}
> +
> check_include() {
> cat > $TMPC < #include <$1>
> @@ -704,6 +714,12 @@ elif check_define __arm__ ; then
>cpu="arm"
> elif check_define __aarch64__ ; then
>cpu="aarch64"
> +elif check_define __riscv ; then
> + if check_define_value __riscv_xlen 64 ; then
> +cpu="riscv64"
> + else
> +cpu="riscv32"
> + fi
> else
>cpu=$(uname -m)
> fi
> @@ -712,7 +728,7 @@ ARCH=
> # Normalise host CPU name and set ARCH.
> # Note that this case should only have supported host CPUs, not guests.
> case "$cpu" in
> - ppc|ppc64|s390|s390x|sparc64|x32)
> + ppc|ppc64|s390|s390x|sparc64|x32|riscv32|riscv64)
> cpu="$cpu"
> supported_cpu="yes"
> eval "cross_cc_${cpu}=\$host_cc"
> --
> 2.17.1
>
>
