On 02/09/2018 08:58 AM, Peter Maydell wrote: > M profile cores have a similar setup for cache ID registers > to A profile: > * Cache Level ID Register (CLIDR) is a fixed value > * Cache Type Register (CTR) is a fixed value > * Cache Size ID Registers (CCSIDR) are a bank of registers; > which one you see is selected by the Cache Size Selection > Register (CSSELR) > > The only difference is that they're in the NVIC memory mapped > register space rather than being coprocessor registers. > Implement the M profile view of them. > > Since neither Cortex-M3 nor Cortex-M4 implement caches, > we don't need to update their init functions and can leave > the ctr/clidr/ccsidr[] fields in their ARMCPU structs at zero. > Newer cores (like the Cortex-M33) will want to be able to > set these ID registers to non-zero values, though. > > Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> > --- > v1->v2 changes: use FIELD() to define some constants; > add compile-time assert that we won't index outside cssidr[] > --- > target/arm/cpu.h | 26 ++++++++++++++++++++++++++ > hw/intc/armv7m_nvic.c | 16 ++++++++++++++++ > target/arm/machine.c | 36 ++++++++++++++++++++++++++++++++++++ > 3 files changed, 78 insertions(+)
Reviewed-by: Richard Henderson <richard.hender...@linaro.org> r~
