Re: [Qemu-devel] [PATCH v4 06/20] ppc/pnv: add XSCOM infrastructure
On 11/07/2016 09:26 AM, Olaf Hering wrote: > On Mon, Oct 03, Cédric Le Goater wrote: > >> +++ b/include/hw/ppc/pnv_xscom.h > >> +typedef struct PnvChip PnvChip; > > This causes a compile error with gcc 4.5.1: Ah yes. That happens with "old" compilers. I will remove the extra definition. Thanks, C. > ... > [ 552s] In file included from > /usr/src/packages/BUILD/qemu-20161104T092624.9226682/hw/ppc/pnv.c:29:0: > [ 552s] > /usr/src/packages/BUILD/qemu-20161104T092624.9226682/include/hw/ppc/pnv.h:60:3: > error: redefinition of typedef 'PnvChip' > [ 552s] > /usr/src/packages/BUILD/qemu-20161104T092624.9226682/include/hw/ppc/pnv_xscom.h:24:24: > note: previous declaration of 'PnvChip' was here > [ 552s] make[1]: *** [hw/ppc/pnv.o] Error 1 > [ 552s] make[1]: Leaving directory > `/usr/src/packages/BUILD/qemu-20161104T092624.9226682/ppc64-softmmu' > [ 552s] make: *** [subdir-ppc64-softmmu] Error 2 > ... > > Olaf >
Re: [Qemu-devel] [PATCH v4 06/20] ppc/pnv: add XSCOM infrastructure
On Mon, Oct 03, Cédric Le Goater wrote: > +++ b/include/hw/ppc/pnv_xscom.h > +typedef struct PnvChip PnvChip; This causes a compile error with gcc 4.5.1: ... [ 552s] In file included from /usr/src/packages/BUILD/qemu-20161104T092624.9226682/hw/ppc/pnv.c:29:0: [ 552s] /usr/src/packages/BUILD/qemu-20161104T092624.9226682/include/hw/ppc/pnv.h:60:3: error: redefinition of typedef 'PnvChip' [ 552s] /usr/src/packages/BUILD/qemu-20161104T092624.9226682/include/hw/ppc/pnv_xscom.h:24:24: note: previous declaration of 'PnvChip' was here [ 552s] make[1]: *** [hw/ppc/pnv.o] Error 1 [ 552s] make[1]: Leaving directory `/usr/src/packages/BUILD/qemu-20161104T092624.9226682/ppc64-softmmu' [ 552s] make: *** [subdir-ppc64-softmmu] Error 2 ... Olaf signature.asc Description: PGP signature
Re: [Qemu-devel] [PATCH v4 06/20] ppc/pnv: add XSCOM infrastructure
On 10/13/2016 02:41 AM, David Gibson wrote:
> On Mon, Oct 03, 2016 at 09:24:42AM +0200, Cédric Le Goater wrote:
>> On a real POWER8 system, the Pervasive Interconnect Bus (PIB) serves
>> as a backbone to connect different units of the system. The host
>> firmware connects to the PIB through a bridge unit, the
>> Alter-Display-Unit (ADU), which gives him access to all the chiplets
>> on the PCB network (Pervasive Connect Bus), the PIB acting as the root
>> of this network.
>>
>> XSCOM (serial communication) is the interface to the sideband bus
>> provided by the POWER8 pervasive unit to read and write to chiplets
>> resources. This is needed by the host firmware, OPAL and to a lesser
>> extent, Linux. This is among others how the PCI Host bridges get
>> configured at boot or how the LPC bus is accessed.
>>
>> To represent the ADU of a real system, we introduce a specific
>> AddressSpace to dispatch XSCOM accesses to the targeted chiplets. The
>> translation of an XSCOM address into a PCB register address is
>> slightly different between the P9 and the P8. This is handled before
>> the dispatch using a 8byte alignment for all.
>>
>> To customize the device tree, a QOM InterfaceClass, PnvXScomInterface,
>> is provided with a populate() handler. The chip populates the device
>> tree by simply looping on its children. Therefore, each model needing
>> custom nodes should not forget to declare itself as a child at
>> instantiation time.
>>
>> Based on previous work done by :
>> Benjamin Herrenschmidt
>>
>> Signed-off-by: Cédric Le Goater
>> ---
>>
>> Changes since v3:
>>
>> - reworked the model to dispatch addresses to the memory regions
>>using pcb_addr << 3, which is a no-op for the P9. The benefit is
>>that all the address translation work can be done before dispatch
>>and the conversion handlers in the chip and in the xscom interface
>>are gone.
>>
>> - removed the proxy PnnXscom object and extended the PnvChip object
>>with an address space for XSCOM and its associated memory region.
>>
>> - changed the read/write handlers in the address space to use
>>address_space_stq() and address_space_ldq()
>>
>> - introduced 'fake' default read/write handlers to handle 'core'
>>registers. We can add a real device model when more work needs to
>>be done under these.
>>
>> - fixed an issue with the monitor doing read/write in the XSCOM
>>address space. When under the monitor, we don't have a cpu to
>>update the HMER SPR. That might need more work in the long term.
>>
>> - introduced a xscom base field to hold the xscom base address as
>>it is different on P9
>>
>> - renamed the devnode() handler to populate()
>>
>> Changes since v2:
>>
>> - QOMified the model.
>>
>> - all mappings in main memory space are now gathered in
>>pnv_chip_realize() as done on other architectures.
>>
>> - removed XScomBus. The parenthood is established through the QOM
>>model
>>
>> - replaced the XScomDevice with an InterfaceClass : PnvXScomInterface.
>> - introduced an XSCOM address space to dispatch accesses to the
>>chiplets
>>
>> hw/ppc/Makefile.objs | 2 +-
>> hw/ppc/pnv.c | 25 +
>> hw/ppc/pnv_xscom.c | 262
>> +
>> include/hw/ppc/pnv.h | 15 +++
>> include/hw/ppc/pnv_xscom.h | 47
>> 5 files changed, 350 insertions(+), 1 deletion(-)
>> create mode 100644 hw/ppc/pnv_xscom.c
>> create mode 100644 include/hw/ppc/pnv_xscom.h
>>
>> diff --git a/hw/ppc/Makefile.objs b/hw/ppc/Makefile.objs
>> index f8c7d1db9ade..08c213c40684 100644
>> --- a/hw/ppc/Makefile.objs
>> +++ b/hw/ppc/Makefile.objs
>> @@ -6,7 +6,7 @@ obj-$(CONFIG_PSERIES) += spapr_hcall.o spapr_iommu.o
>> spapr_rtas.o
>> obj-$(CONFIG_PSERIES) += spapr_pci.o spapr_rtc.o spapr_drc.o spapr_rng.o
>> obj-$(CONFIG_PSERIES) += spapr_cpu_core.o
>> # IBM PowerNV
>> -obj-$(CONFIG_POWERNV) += pnv.o pnv_core.o
>> +obj-$(CONFIG_POWERNV) += pnv.o pnv_xscom.o pnv_core.o
>> ifeq ($(CONFIG_PCI)$(CONFIG_PSERIES)$(CONFIG_LINUX), yyy)
>> obj-y += spapr_pci_vfio.o
>> endif
>> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
>> index 2376bb222918..5e19b6880387 100644
>> --- a/hw/ppc/pnv.c
>> +++ b/hw/ppc/pnv.c
>> @@ -32,6 +32,8 @@
>> #include "exec/address-spaces.h"
>> #include "qemu/cutils.h"
>>
>> +#include "hw/ppc/pnv_xscom.h"
>> +
>> #include
>>
>> #define FDT_MAX_SIZE0x0010
>> @@ -218,6 +220,8 @@ static void powernv_populate_chip(PnvChip *chip, void
>> *fdt)
>> size_t typesize = object_type_get_instance_size(typename);
>> int i;
>>
>> +pnv_xscom_populate(chip, fdt, 0);
>> +
>> for (i = 0; i < chip->nr_cores; i++) {
>> PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize);
>>
>> @@ -450,6 +454,7 @@ static void pnv_chip_power8e_class_init(ObjectClass
>> *klass, void *data)
>> k->chip_cfam_id = 0x221ef0498000ull; /* P8 Murano DD2.1
Re: [Qemu-devel] [PATCH v4 06/20] ppc/pnv: add XSCOM infrastructure
On Mon, Oct 03, 2016 at 09:24:42AM +0200, Cédric Le Goater wrote:
> On a real POWER8 system, the Pervasive Interconnect Bus (PIB) serves
> as a backbone to connect different units of the system. The host
> firmware connects to the PIB through a bridge unit, the
> Alter-Display-Unit (ADU), which gives him access to all the chiplets
> on the PCB network (Pervasive Connect Bus), the PIB acting as the root
> of this network.
>
> XSCOM (serial communication) is the interface to the sideband bus
> provided by the POWER8 pervasive unit to read and write to chiplets
> resources. This is needed by the host firmware, OPAL and to a lesser
> extent, Linux. This is among others how the PCI Host bridges get
> configured at boot or how the LPC bus is accessed.
>
> To represent the ADU of a real system, we introduce a specific
> AddressSpace to dispatch XSCOM accesses to the targeted chiplets. The
> translation of an XSCOM address into a PCB register address is
> slightly different between the P9 and the P8. This is handled before
> the dispatch using a 8byte alignment for all.
>
> To customize the device tree, a QOM InterfaceClass, PnvXScomInterface,
> is provided with a populate() handler. The chip populates the device
> tree by simply looping on its children. Therefore, each model needing
> custom nodes should not forget to declare itself as a child at
> instantiation time.
>
> Based on previous work done by :
> Benjamin Herrenschmidt
>
> Signed-off-by: Cédric Le Goater
> ---
>
> Changes since v3:
>
> - reworked the model to dispatch addresses to the memory regions
>using pcb_addr << 3, which is a no-op for the P9. The benefit is
>that all the address translation work can be done before dispatch
>and the conversion handlers in the chip and in the xscom interface
>are gone.
>
> - removed the proxy PnnXscom object and extended the PnvChip object
>with an address space for XSCOM and its associated memory region.
>
> - changed the read/write handlers in the address space to use
>address_space_stq() and address_space_ldq()
>
> - introduced 'fake' default read/write handlers to handle 'core'
>registers. We can add a real device model when more work needs to
>be done under these.
>
> - fixed an issue with the monitor doing read/write in the XSCOM
>address space. When under the monitor, we don't have a cpu to
>update the HMER SPR. That might need more work in the long term.
>
> - introduced a xscom base field to hold the xscom base address as
>it is different on P9
>
> - renamed the devnode() handler to populate()
>
> Changes since v2:
>
> - QOMified the model.
>
> - all mappings in main memory space are now gathered in
>pnv_chip_realize() as done on other architectures.
>
> - removed XScomBus. The parenthood is established through the QOM
>model
>
> - replaced the XScomDevice with an InterfaceClass : PnvXScomInterface.
> - introduced an XSCOM address space to dispatch accesses to the
>chiplets
>
> hw/ppc/Makefile.objs | 2 +-
> hw/ppc/pnv.c | 25 +
> hw/ppc/pnv_xscom.c | 262
> +
> include/hw/ppc/pnv.h | 15 +++
> include/hw/ppc/pnv_xscom.h | 47
> 5 files changed, 350 insertions(+), 1 deletion(-)
> create mode 100644 hw/ppc/pnv_xscom.c
> create mode 100644 include/hw/ppc/pnv_xscom.h
>
> diff --git a/hw/ppc/Makefile.objs b/hw/ppc/Makefile.objs
> index f8c7d1db9ade..08c213c40684 100644
> --- a/hw/ppc/Makefile.objs
> +++ b/hw/ppc/Makefile.objs
> @@ -6,7 +6,7 @@ obj-$(CONFIG_PSERIES) += spapr_hcall.o spapr_iommu.o
> spapr_rtas.o
> obj-$(CONFIG_PSERIES) += spapr_pci.o spapr_rtc.o spapr_drc.o spapr_rng.o
> obj-$(CONFIG_PSERIES) += spapr_cpu_core.o
> # IBM PowerNV
> -obj-$(CONFIG_POWERNV) += pnv.o pnv_core.o
> +obj-$(CONFIG_POWERNV) += pnv.o pnv_xscom.o pnv_core.o
> ifeq ($(CONFIG_PCI)$(CONFIG_PSERIES)$(CONFIG_LINUX), yyy)
> obj-y += spapr_pci_vfio.o
> endif
> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
> index 2376bb222918..5e19b6880387 100644
> --- a/hw/ppc/pnv.c
> +++ b/hw/ppc/pnv.c
> @@ -32,6 +32,8 @@
> #include "exec/address-spaces.h"
> #include "qemu/cutils.h"
>
> +#include "hw/ppc/pnv_xscom.h"
> +
> #include
>
> #define FDT_MAX_SIZE0x0010
> @@ -218,6 +220,8 @@ static void powernv_populate_chip(PnvChip *chip, void
> *fdt)
> size_t typesize = object_type_get_instance_size(typename);
> int i;
>
> +pnv_xscom_populate(chip, fdt, 0);
> +
> for (i = 0; i < chip->nr_cores; i++) {
> PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize);
>
> @@ -450,6 +454,7 @@ static void pnv_chip_power8e_class_init(ObjectClass
> *klass, void *data)
> k->chip_cfam_id = 0x221ef0498000ull; /* P8 Murano DD2.1 */
> k->cores_mask = POWER8E_CORE_MASK;
> k->core_pir = pnv_chip_core_pir_p8;
> +k->xscom_base = 0x003fc00ull;
> dc->desc = "Pow
