Re: [Qemu-devel] [PATCH v4 09/14] pci: Add support for Designware IP block

[Andrey Smirnov]

On Wed, Jan 31, 2018 at 4:13 AM, Marcel Apfelbaum  wrote:
> On 30/01/2018 19:49, Andrey Smirnov wrote:
>> On Tue, Jan 30, 2018 at 5:18 AM, Marcel Apfelbaum
>>  wrote:
>>> Hi Andrei,
>>>
>>> Sorry for letting you wait,
>>> I have some comments/questions below.
>>>
>>>
>>> On 16/01/2018 3:37, Andrey Smirnov wrote:

 Add code needed to get a functional PCI subsytem when using in
 conjunction with upstream Linux guest (4.13+). Tested to work against
 "e1000e" (network adapter, using MSI interrupts) as well as
 "usb-ehci" (USB controller, using legacy PCI interrupts).

 Cc: Peter Maydell 
 Cc: Jason Wang 
 Cc: Philippe Mathieu-Daudé 
 Cc: qemu-devel@nongnu.org
 Cc: qemu-...@nongnu.org
 Cc: yurov...@gmail.com
 Signed-off-by: Andrey Smirnov 
 ---
   default-configs/arm-softmmu.mak  |   2 +
   hw/pci-host/Makefile.objs|   2 +
   hw/pci-host/designware.c | 618
 +++
   include/hw/pci-host/designware.h |  93 ++
   include/hw/pci/pci_ids.h |   2 +
   5 files changed, 717 insertions(+)
   create mode 100644 hw/pci-host/designware.c
   create mode 100644 include/hw/pci-host/designware.h

 diff --git a/default-configs/arm-softmmu.mak
 b/default-configs/arm-softmmu.mak
 index b0d6e65038..0c5ae914ed 100644
 --- a/default-configs/arm-softmmu.mak
 +++ b/default-configs/arm-softmmu.mak
 @@ -132,3 +132,5 @@ CONFIG_GPIO_KEY=y
   CONFIG_MSF2=y
   CONFIG_FW_CFG_DMA=y
   CONFIG_XILINX_AXI=y
 +CONFIG_PCI_DESIGNWARE=y
 +
 diff --git a/hw/pci-host/Makefile.objs b/hw/pci-host/Makefile.objs
 index 9c7909cf44..0e2c0a123b 100644
 --- a/hw/pci-host/Makefile.objs
 +++ b/hw/pci-host/Makefile.objs
 @@ -17,3 +17,5 @@ common-obj-$(CONFIG_PCI_PIIX) += piix.o
   common-obj-$(CONFIG_PCI_Q35) += q35.o
   common-obj-$(CONFIG_PCI_GENERIC) += gpex.o
   common-obj-$(CONFIG_PCI_XILINX) += xilinx-pcie.o
 +
 +common-obj-$(CONFIG_PCI_DESIGNWARE) += designware.o
 diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c
 new file mode 100644
 index 00..98fff5e5f3
 --- /dev/null
 +++ b/hw/pci-host/designware.c
 @@ -0,0 +1,618 @@
 +/*
 + * Copyright (c) 2017, Impinj, Inc.
>>>
>>> 2018 :)
>>>
 + *
 + * Designware PCIe IP block emulation
 + *
 + * This library is free software; you can redistribute it and/or
 + * modify it under the terms of the GNU Lesser General Public
 + * License as published by the Free Software Foundation; either
 + * version 2 of the License, or (at your option) any later version.
 + *
 + * This library is distributed in the hope that it will be useful,
 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 + * Lesser General Public License for more details.
 + *
 + * You should have received a copy of the GNU Lesser General Public
 + * License along with this library; if not, see
 + * .
 + */
 +
 +#include "qemu/osdep.h"
 +#include "qapi/error.h"
 +#include "hw/pci/msi.h"
 +#include "hw/pci/pci_bridge.h"
 +#include "hw/pci/pci_host.h"
 +#include "hw/pci/pcie_port.h"
 +#include "hw/pci-host/designware.h"
 +
 +#define PCIE_PORT_LINK_CONTROL  0x710
 +
 +#define PCIE_PHY_DEBUG_R1   0x72C
 +#define PCIE_PHY_DEBUG_R1_XMLH_LINK_UP  BIT(4)
 +
 +#define PCIE_LINK_WIDTH_SPEED_CONTROL   0x80C
 +
 +#define PCIE_MSI_ADDR_LO0x820
 +#define PCIE_MSI_ADDR_HI0x824
 +#define PCIE_MSI_INTR0_ENABLE   0x828
 +#define PCIE_MSI_INTR0_MASK 0x82C
 +#define PCIE_MSI_INTR0_STATUS   0x830
 +
 +#define PCIE_ATU_VIEWPORT   0x900
 +#define PCIE_ATU_REGION_INBOUND (0x1 << 31)
 +#define PCIE_ATU_REGION_OUTBOUND(0x0 << 31)
 +#define PCIE_ATU_REGION_INDEX2  (0x2 << 0)
 +#define PCIE_ATU_REGION_INDEX1  (0x1 << 0)
 +#define PCIE_ATU_REGION_INDEX0  (0x0 << 0)
 +#define PCIE_ATU_CR10x904
 +#define PCIE_ATU_TYPE_MEM   (0x0 << 0)
 +#define PCIE_ATU_TYPE_IO(0x2 << 0)
 +#define PCIE_ATU_TYPE_CFG0  (0x4 << 0)
 +#define PCIE_ATU_TYPE_CFG1  (0x5 << 0)
 +#define PCIE_ATU_CR20x908
 +#define PCIE_ATU_ENABLE (0x1 << 31)
 +#define PCIE_ATU_BAR_MODE_ENABLE(0x1 << 30)
 +#define PCIE_ATU_LOWER_BASE 0x90C
 +#define PCIE_ATU_UPPER_BASE 0x910
 +#define PCIE_ATU_LIMIT   

Re: [Qemu-devel] [PATCH v4 09/14] pci: Add support for Designware IP block

[Marcel Apfelbaum]

On 30/01/2018 19:49, Andrey Smirnov wrote:
> On Tue, Jan 30, 2018 at 5:18 AM, Marcel Apfelbaum
>  wrote:
>> Hi Andrei,
>>
>> Sorry for letting you wait,
>> I have some comments/questions below.
>>
>>
>> On 16/01/2018 3:37, Andrey Smirnov wrote:
>>>
>>> Add code needed to get a functional PCI subsytem when using in
>>> conjunction with upstream Linux guest (4.13+). Tested to work against
>>> "e1000e" (network adapter, using MSI interrupts) as well as
>>> "usb-ehci" (USB controller, using legacy PCI interrupts).
>>>
>>> Cc: Peter Maydell 
>>> Cc: Jason Wang 
>>> Cc: Philippe Mathieu-Daudé 
>>> Cc: qemu-devel@nongnu.org
>>> Cc: qemu-...@nongnu.org
>>> Cc: yurov...@gmail.com
>>> Signed-off-by: Andrey Smirnov 
>>> ---
>>>   default-configs/arm-softmmu.mak  |   2 +
>>>   hw/pci-host/Makefile.objs|   2 +
>>>   hw/pci-host/designware.c | 618
>>> +++
>>>   include/hw/pci-host/designware.h |  93 ++
>>>   include/hw/pci/pci_ids.h |   2 +
>>>   5 files changed, 717 insertions(+)
>>>   create mode 100644 hw/pci-host/designware.c
>>>   create mode 100644 include/hw/pci-host/designware.h
>>>
>>> diff --git a/default-configs/arm-softmmu.mak
>>> b/default-configs/arm-softmmu.mak
>>> index b0d6e65038..0c5ae914ed 100644
>>> --- a/default-configs/arm-softmmu.mak
>>> +++ b/default-configs/arm-softmmu.mak
>>> @@ -132,3 +132,5 @@ CONFIG_GPIO_KEY=y
>>>   CONFIG_MSF2=y
>>>   CONFIG_FW_CFG_DMA=y
>>>   CONFIG_XILINX_AXI=y
>>> +CONFIG_PCI_DESIGNWARE=y
>>> +
>>> diff --git a/hw/pci-host/Makefile.objs b/hw/pci-host/Makefile.objs
>>> index 9c7909cf44..0e2c0a123b 100644
>>> --- a/hw/pci-host/Makefile.objs
>>> +++ b/hw/pci-host/Makefile.objs
>>> @@ -17,3 +17,5 @@ common-obj-$(CONFIG_PCI_PIIX) += piix.o
>>>   common-obj-$(CONFIG_PCI_Q35) += q35.o
>>>   common-obj-$(CONFIG_PCI_GENERIC) += gpex.o
>>>   common-obj-$(CONFIG_PCI_XILINX) += xilinx-pcie.o
>>> +
>>> +common-obj-$(CONFIG_PCI_DESIGNWARE) += designware.o
>>> diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c
>>> new file mode 100644
>>> index 00..98fff5e5f3
>>> --- /dev/null
>>> +++ b/hw/pci-host/designware.c
>>> @@ -0,0 +1,618 @@
>>> +/*
>>> + * Copyright (c) 2017, Impinj, Inc.
>>
>> 2018 :)
>>
>>> + *
>>> + * Designware PCIe IP block emulation
>>> + *
>>> + * This library is free software; you can redistribute it and/or
>>> + * modify it under the terms of the GNU Lesser General Public
>>> + * License as published by the Free Software Foundation; either
>>> + * version 2 of the License, or (at your option) any later version.
>>> + *
>>> + * This library is distributed in the hope that it will be useful,
>>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
>>> + * Lesser General Public License for more details.
>>> + *
>>> + * You should have received a copy of the GNU Lesser General Public
>>> + * License along with this library; if not, see
>>> + * .
>>> + */
>>> +
>>> +#include "qemu/osdep.h"
>>> +#include "qapi/error.h"
>>> +#include "hw/pci/msi.h"
>>> +#include "hw/pci/pci_bridge.h"
>>> +#include "hw/pci/pci_host.h"
>>> +#include "hw/pci/pcie_port.h"
>>> +#include "hw/pci-host/designware.h"
>>> +
>>> +#define PCIE_PORT_LINK_CONTROL  0x710
>>> +
>>> +#define PCIE_PHY_DEBUG_R1   0x72C
>>> +#define PCIE_PHY_DEBUG_R1_XMLH_LINK_UP  BIT(4)
>>> +
>>> +#define PCIE_LINK_WIDTH_SPEED_CONTROL   0x80C
>>> +
>>> +#define PCIE_MSI_ADDR_LO0x820
>>> +#define PCIE_MSI_ADDR_HI0x824
>>> +#define PCIE_MSI_INTR0_ENABLE   0x828
>>> +#define PCIE_MSI_INTR0_MASK 0x82C
>>> +#define PCIE_MSI_INTR0_STATUS   0x830
>>> +
>>> +#define PCIE_ATU_VIEWPORT   0x900
>>> +#define PCIE_ATU_REGION_INBOUND (0x1 << 31)
>>> +#define PCIE_ATU_REGION_OUTBOUND(0x0 << 31)
>>> +#define PCIE_ATU_REGION_INDEX2  (0x2 << 0)
>>> +#define PCIE_ATU_REGION_INDEX1  (0x1 << 0)
>>> +#define PCIE_ATU_REGION_INDEX0  (0x0 << 0)
>>> +#define PCIE_ATU_CR10x904
>>> +#define PCIE_ATU_TYPE_MEM   (0x0 << 0)
>>> +#define PCIE_ATU_TYPE_IO(0x2 << 0)
>>> +#define PCIE_ATU_TYPE_CFG0  (0x4 << 0)
>>> +#define PCIE_ATU_TYPE_CFG1  (0x5 << 0)
>>> +#define PCIE_ATU_CR20x908
>>> +#define PCIE_ATU_ENABLE (0x1 << 31)
>>> +#define PCIE_ATU_BAR_MODE_ENABLE(0x1 << 30)
>>> +#define PCIE_ATU_LOWER_BASE 0x90C
>>> +#define PCIE_ATU_UPPER_BASE 0x910
>>> +#define PCIE_ATU_LIMIT  0x914
>>> +#define PCIE_ATU_LOWER_TARGET   0x918
>>> +#define PCIE_ATU_BUS(x) (((x) >> 24) & 0xff)
>>> +#define PCIE_ATU_DEVFN(x)   (((x) >> 16) & 0xff)

Re: [Qemu-devel] [PATCH v4 09/14] pci: Add support for Designware IP block

[Andrey Smirnov]

On Tue, Jan 30, 2018 at 5:18 AM, Marcel Apfelbaum
 wrote:
> Hi Andrei,
>
> Sorry for letting you wait,
> I have some comments/questions below.
>
>
> On 16/01/2018 3:37, Andrey Smirnov wrote:
>>
>> Add code needed to get a functional PCI subsytem when using in
>> conjunction with upstream Linux guest (4.13+). Tested to work against
>> "e1000e" (network adapter, using MSI interrupts) as well as
>> "usb-ehci" (USB controller, using legacy PCI interrupts).
>>
>> Cc: Peter Maydell 
>> Cc: Jason Wang 
>> Cc: Philippe Mathieu-Daudé 
>> Cc: qemu-devel@nongnu.org
>> Cc: qemu-...@nongnu.org
>> Cc: yurov...@gmail.com
>> Signed-off-by: Andrey Smirnov 
>> ---
>>   default-configs/arm-softmmu.mak  |   2 +
>>   hw/pci-host/Makefile.objs|   2 +
>>   hw/pci-host/designware.c | 618
>> +++
>>   include/hw/pci-host/designware.h |  93 ++
>>   include/hw/pci/pci_ids.h |   2 +
>>   5 files changed, 717 insertions(+)
>>   create mode 100644 hw/pci-host/designware.c
>>   create mode 100644 include/hw/pci-host/designware.h
>>
>> diff --git a/default-configs/arm-softmmu.mak
>> b/default-configs/arm-softmmu.mak
>> index b0d6e65038..0c5ae914ed 100644
>> --- a/default-configs/arm-softmmu.mak
>> +++ b/default-configs/arm-softmmu.mak
>> @@ -132,3 +132,5 @@ CONFIG_GPIO_KEY=y
>>   CONFIG_MSF2=y
>>   CONFIG_FW_CFG_DMA=y
>>   CONFIG_XILINX_AXI=y
>> +CONFIG_PCI_DESIGNWARE=y
>> +
>> diff --git a/hw/pci-host/Makefile.objs b/hw/pci-host/Makefile.objs
>> index 9c7909cf44..0e2c0a123b 100644
>> --- a/hw/pci-host/Makefile.objs
>> +++ b/hw/pci-host/Makefile.objs
>> @@ -17,3 +17,5 @@ common-obj-$(CONFIG_PCI_PIIX) += piix.o
>>   common-obj-$(CONFIG_PCI_Q35) += q35.o
>>   common-obj-$(CONFIG_PCI_GENERIC) += gpex.o
>>   common-obj-$(CONFIG_PCI_XILINX) += xilinx-pcie.o
>> +
>> +common-obj-$(CONFIG_PCI_DESIGNWARE) += designware.o
>> diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c
>> new file mode 100644
>> index 00..98fff5e5f3
>> --- /dev/null
>> +++ b/hw/pci-host/designware.c
>> @@ -0,0 +1,618 @@
>> +/*
>> + * Copyright (c) 2017, Impinj, Inc.
>
> 2018 :)
>
>> + *
>> + * Designware PCIe IP block emulation
>> + *
>> + * This library is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU Lesser General Public
>> + * License as published by the Free Software Foundation; either
>> + * version 2 of the License, or (at your option) any later version.
>> + *
>> + * This library is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
>> + * Lesser General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU Lesser General Public
>> + * License along with this library; if not, see
>> + * .
>> + */
>> +
>> +#include "qemu/osdep.h"
>> +#include "qapi/error.h"
>> +#include "hw/pci/msi.h"
>> +#include "hw/pci/pci_bridge.h"
>> +#include "hw/pci/pci_host.h"
>> +#include "hw/pci/pcie_port.h"
>> +#include "hw/pci-host/designware.h"
>> +
>> +#define PCIE_PORT_LINK_CONTROL  0x710
>> +
>> +#define PCIE_PHY_DEBUG_R1   0x72C
>> +#define PCIE_PHY_DEBUG_R1_XMLH_LINK_UP  BIT(4)
>> +
>> +#define PCIE_LINK_WIDTH_SPEED_CONTROL   0x80C
>> +
>> +#define PCIE_MSI_ADDR_LO0x820
>> +#define PCIE_MSI_ADDR_HI0x824
>> +#define PCIE_MSI_INTR0_ENABLE   0x828
>> +#define PCIE_MSI_INTR0_MASK 0x82C
>> +#define PCIE_MSI_INTR0_STATUS   0x830
>> +
>> +#define PCIE_ATU_VIEWPORT   0x900
>> +#define PCIE_ATU_REGION_INBOUND (0x1 << 31)
>> +#define PCIE_ATU_REGION_OUTBOUND(0x0 << 31)
>> +#define PCIE_ATU_REGION_INDEX2  (0x2 << 0)
>> +#define PCIE_ATU_REGION_INDEX1  (0x1 << 0)
>> +#define PCIE_ATU_REGION_INDEX0  (0x0 << 0)
>> +#define PCIE_ATU_CR10x904
>> +#define PCIE_ATU_TYPE_MEM   (0x0 << 0)
>> +#define PCIE_ATU_TYPE_IO(0x2 << 0)
>> +#define PCIE_ATU_TYPE_CFG0  (0x4 << 0)
>> +#define PCIE_ATU_TYPE_CFG1  (0x5 << 0)
>> +#define PCIE_ATU_CR20x908
>> +#define PCIE_ATU_ENABLE (0x1 << 31)
>> +#define PCIE_ATU_BAR_MODE_ENABLE(0x1 << 30)
>> +#define PCIE_ATU_LOWER_BASE 0x90C
>> +#define PCIE_ATU_UPPER_BASE 0x910
>> +#define PCIE_ATU_LIMIT  0x914
>> +#define PCIE_ATU_LOWER_TARGET   0x918
>> +#define PCIE_ATU_BUS(x) (((x) >> 24) & 0xff)
>> +#define PCIE_ATU_DEVFN(x)   (((x) >> 16) & 0xff)
>> +#define PCIE_ATU_UPPER_TARGET   0x91C
>> +
>> +static DesignwarePCIEHost *
>> +designware_pcie_root_to_host(DesignwarePCIERoot *root)
>> +{
>> +BusState 

Re: [Qemu-devel] [PATCH v4 09/14] pci: Add support for Designware IP block

[Marcel Apfelbaum]

Hi Andrei,

Sorry for letting you wait,
I have some comments/questions below.

On 16/01/2018 3:37, Andrey Smirnov wrote:

Add code needed to get a functional PCI subsytem when using in
conjunction with upstream Linux guest (4.13+). Tested to work against
"e1000e" (network adapter, using MSI interrupts) as well as
"usb-ehci" (USB controller, using legacy PCI interrupts).

Cc: Peter Maydell 
Cc: Jason Wang 
Cc: Philippe Mathieu-Daudé 
Cc: qemu-devel@nongnu.org
Cc: qemu-...@nongnu.org
Cc: yurov...@gmail.com
Signed-off-by: Andrey Smirnov 
---
  default-configs/arm-softmmu.mak  |   2 +
  hw/pci-host/Makefile.objs|   2 +
  hw/pci-host/designware.c | 618 +++
  include/hw/pci-host/designware.h |  93 ++
  include/hw/pci/pci_ids.h |   2 +
  5 files changed, 717 insertions(+)
  create mode 100644 hw/pci-host/designware.c
  create mode 100644 include/hw/pci-host/designware.h

diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index b0d6e65038..0c5ae914ed 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -132,3 +132,5 @@ CONFIG_GPIO_KEY=y
  CONFIG_MSF2=y
  CONFIG_FW_CFG_DMA=y
  CONFIG_XILINX_AXI=y
+CONFIG_PCI_DESIGNWARE=y
+
diff --git a/hw/pci-host/Makefile.objs b/hw/pci-host/Makefile.objs
index 9c7909cf44..0e2c0a123b 100644
--- a/hw/pci-host/Makefile.objs
+++ b/hw/pci-host/Makefile.objs
@@ -17,3 +17,5 @@ common-obj-$(CONFIG_PCI_PIIX) += piix.o
  common-obj-$(CONFIG_PCI_Q35) += q35.o
  common-obj-$(CONFIG_PCI_GENERIC) += gpex.o
  common-obj-$(CONFIG_PCI_XILINX) += xilinx-pcie.o
+
+common-obj-$(CONFIG_PCI_DESIGNWARE) += designware.o
diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c
new file mode 100644
index 00..98fff5e5f3
--- /dev/null
+++ b/hw/pci-host/designware.c
@@ -0,0 +1,618 @@
+/*
+ * Copyright (c) 2017, Impinj, Inc.

2018 :)

+ *
+ * Designware PCIe IP block emulation
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see
+ * .
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "hw/pci/msi.h"
+#include "hw/pci/pci_bridge.h"
+#include "hw/pci/pci_host.h"
+#include "hw/pci/pcie_port.h"
+#include "hw/pci-host/designware.h"
+
+#define PCIE_PORT_LINK_CONTROL  0x710
+
+#define PCIE_PHY_DEBUG_R1   0x72C
+#define PCIE_PHY_DEBUG_R1_XMLH_LINK_UP  BIT(4)
+
+#define PCIE_LINK_WIDTH_SPEED_CONTROL   0x80C
+
+#define PCIE_MSI_ADDR_LO0x820
+#define PCIE_MSI_ADDR_HI0x824
+#define PCIE_MSI_INTR0_ENABLE   0x828
+#define PCIE_MSI_INTR0_MASK 0x82C
+#define PCIE_MSI_INTR0_STATUS   0x830
+
+#define PCIE_ATU_VIEWPORT   0x900
+#define PCIE_ATU_REGION_INBOUND (0x1 << 31)
+#define PCIE_ATU_REGION_OUTBOUND(0x0 << 31)
+#define PCIE_ATU_REGION_INDEX2  (0x2 << 0)
+#define PCIE_ATU_REGION_INDEX1  (0x1 << 0)
+#define PCIE_ATU_REGION_INDEX0  (0x0 << 0)
+#define PCIE_ATU_CR10x904
+#define PCIE_ATU_TYPE_MEM   (0x0 << 0)
+#define PCIE_ATU_TYPE_IO(0x2 << 0)
+#define PCIE_ATU_TYPE_CFG0  (0x4 << 0)
+#define PCIE_ATU_TYPE_CFG1  (0x5 << 0)
+#define PCIE_ATU_CR20x908
+#define PCIE_ATU_ENABLE (0x1 << 31)
+#define PCIE_ATU_BAR_MODE_ENABLE(0x1 << 30)
+#define PCIE_ATU_LOWER_BASE 0x90C
+#define PCIE_ATU_UPPER_BASE 0x910
+#define PCIE_ATU_LIMIT  0x914
+#define PCIE_ATU_LOWER_TARGET   0x918
+#define PCIE_ATU_BUS(x) (((x) >> 24) & 0xff)
+#define PCIE_ATU_DEVFN(x)   (((x) >> 16) & 0xff)
+#define PCIE_ATU_UPPER_TARGET   0x91C
+
+static DesignwarePCIEHost *
+designware_pcie_root_to_host(DesignwarePCIERoot *root)
+{
+BusState *bus = qdev_get_parent_bus(DEVICE(root));
+return DESIGNWARE_PCIE_HOST(bus->parent);
+}
+
+static void designware_pcie_root_msi_write(void *opaque, hwaddr addr,
+   uint64_t val, unsigned len)
+{
+DesignwarePCIERoot *root = DESIGNWARE_PCIE_ROOT(opaque);
+DesignwarePCIEHost *host = designware_pcie_root_to_host(root);
+
+root->msi.intr[0].status |= (1 << val) & root->msi.intr[0].enable;
+
+

Re: [Qemu-devel] [PATCH v4 09/14] pci: Add support for Designware IP block

[Philippe Mathieu-Daudé]

Hi Andrey,

On Wed, Jan 17, 2018 at 1:12 PM, Andrey Smirnov
 wrote:
> On Wed, Jan 17, 2018 at 7:23 AM, Marcel Apfelbaum
>  wrote:
>> That being said, if Andrey can point me to the PCI spec for the Designware
>> PCI host bridge and what parts they implemented for it I can have a look,
>> sure.
>> (I will not be available for a week or so, but right after)
>>
>
> Just in case you still want this:
>
> To the best of my knowledge, Synposys does not provide specification
> for their PCIe IP to general public and I am in no way affiliated with
> them, so I don't have any backchannels to get it any other way.
>
> The next best thing to an actual spec, that I found to be pretty
> useful, is PCIe chapter of i.MX6Q Reference Manual
> (https://www.nxp.com/docs/en/reference-manual/IMX6DQRM.pdf   page
> 4049), which is what I used to implement the code in question.

Please add a comment about it in your respin, such:

Based on "i.MX6 Applications Processor Reference Manual" (Document
Number: IMX6DQRM Rev. 4)

> Last, and probably the most important, "source of truth" was actual
> Linux PCIe driver for i.MX/Designware which I used as a sort of
> inverse reference implementation.

Same here:

Reversed from Linux v4.9 drivers/pci/host/pcie-designware.c

Re: [Qemu-devel] [PATCH v4 09/14] pci: Add support for Designware IP block

[Marcel Apfelbaum]

On 17/01/2018 18:12, Andrey Smirnov wrote:

On Wed, Jan 17, 2018 at 7:23 AM, Marcel Apfelbaum
 wrote:


Hi Peter,


On 16/01/2018 16:34, Peter Maydell wrote:


On 16 January 2018 at 01:37, Andrey Smirnov 
wrote:


Add code needed to get a functional PCI subsytem when using in
conjunction with upstream Linux guest (4.13+). Tested to work against
"e1000e" (network adapter, using MSI interrupts) as well as
"usb-ehci" (USB controller, using legacy PCI interrupts).

Cc: Peter Maydell 
Cc: Jason Wang 
Cc: Philippe Mathieu-Daudé 
Cc: qemu-devel@nongnu.org
Cc: qemu-...@nongnu.org
Cc: yurov...@gmail.com
Signed-off-by: Andrey Smirnov 
---
   default-configs/arm-softmmu.mak  |   2 +
   hw/pci-host/Makefile.objs|   2 +
   hw/pci-host/designware.c | 618
+++
   include/hw/pci-host/designware.h |  93 ++
   include/hw/pci/pci_ids.h |   2 +
   5 files changed, 717 insertions(+)
   create mode 100644 hw/pci-host/designware.c
   create mode 100644 include/hw/pci-host/designware.h


I'm not familiar enough with our PCI code to be able to review
this, I'm afraid. MST and Marcel are our PCI subsystem maintainers --
could one of you have a look at whether this seems to be a correct
implementation of a pcie host controller ?



Sadly PCI Host bridges do not have a standard, each HW vendor
can do pretty much what they want.

That being said, if Andrey can point me to the PCI spec for the Designware
PCI host bridge and what parts they implemented for it I can have a look,
sure.
(I will not be available for a week or so, but right after)



Just in case you still want this:

To the best of my knowledge, Synposys does not provide specification
for their PCIe IP to general public and I am in no way affiliated with
them, so I don't have any backchannels to get it any other way.

The next best thing to an actual spec, that I found to be pretty
useful, is PCIe chapter of i.MX6Q Reference Manual
(https://www.nxp.com/docs/en/reference-manual/IMX6DQRM.pdf   page
4049), which is what I used to implement the code in question.



Appreciated.


Last, and probably the most important, "source of truth" was actual
Linux PCIe driver for i.MX/Designware which I used as a sort of
inverse reference implementation.



We did the same for our PVRDMA device implementation :)


Thanks,
Marcel


Thanks,
Andrey Smirnov

Re: [Qemu-devel] [PATCH v4 09/14] pci: Add support for Designware IP block

[Marcel Apfelbaum]

On 17/01/2018 17:35, Peter Maydell wrote:

On 17 January 2018 at 15:23, Marcel Apfelbaum  wrote:


On 16/01/2018 16:34, Peter Maydell wrote:

On 16 January 2018 at 01:37, Andrey Smirnov 
I'm not familiar enough with our PCI code to be able to review
this, I'm afraid. MST and Marcel are our PCI subsystem maintainers --
could one of you have a look at whether this seems to be a correct
implementation of a pcie host controller ?



Sadly PCI Host bridges do not have a standard, each HW vendor
can do pretty much what they want.

That being said, if Andrey can point me to the PCI spec for the Designware
PCI host bridge and what parts they implemented for it I can have a look,
sure.


I'm not so worried about whether it's implementing the spec for
the hardware (I trust Andrey has done enough testing for that
side of things), but whether the code seems to be structured
the way we expect a QEMU pcie host controller to be structured,
is using the right APIs, and so on.



Got it, I'll review in a week.

Thanks,
Marcel


thanks
-- PMM

Re: [Qemu-devel] [PATCH v4 09/14] pci: Add support for Designware IP block

[Andrey Smirnov]

On Wed, Jan 17, 2018 at 7:23 AM, Marcel Apfelbaum
 wrote:
>
> Hi Peter,
>
>
> On 16/01/2018 16:34, Peter Maydell wrote:
>>
>> On 16 January 2018 at 01:37, Andrey Smirnov 
>> wrote:
>>>
>>> Add code needed to get a functional PCI subsytem when using in
>>> conjunction with upstream Linux guest (4.13+). Tested to work against
>>> "e1000e" (network adapter, using MSI interrupts) as well as
>>> "usb-ehci" (USB controller, using legacy PCI interrupts).
>>>
>>> Cc: Peter Maydell 
>>> Cc: Jason Wang 
>>> Cc: Philippe Mathieu-Daudé 
>>> Cc: qemu-devel@nongnu.org
>>> Cc: qemu-...@nongnu.org
>>> Cc: yurov...@gmail.com
>>> Signed-off-by: Andrey Smirnov 
>>> ---
>>>   default-configs/arm-softmmu.mak  |   2 +
>>>   hw/pci-host/Makefile.objs|   2 +
>>>   hw/pci-host/designware.c | 618
>>> +++
>>>   include/hw/pci-host/designware.h |  93 ++
>>>   include/hw/pci/pci_ids.h |   2 +
>>>   5 files changed, 717 insertions(+)
>>>   create mode 100644 hw/pci-host/designware.c
>>>   create mode 100644 include/hw/pci-host/designware.h
>>
>> I'm not familiar enough with our PCI code to be able to review
>> this, I'm afraid. MST and Marcel are our PCI subsystem maintainers --
>> could one of you have a look at whether this seems to be a correct
>> implementation of a pcie host controller ?
>
>
> Sadly PCI Host bridges do not have a standard, each HW vendor
> can do pretty much what they want.
>
> That being said, if Andrey can point me to the PCI spec for the Designware
> PCI host bridge and what parts they implemented for it I can have a look,
> sure.
> (I will not be available for a week or so, but right after)
>

Just in case you still want this:

To the best of my knowledge, Synposys does not provide specification
for their PCIe IP to general public and I am in no way affiliated with
them, so I don't have any backchannels to get it any other way.

The next best thing to an actual spec, that I found to be pretty
useful, is PCIe chapter of i.MX6Q Reference Manual
(https://www.nxp.com/docs/en/reference-manual/IMX6DQRM.pdf   page
4049), which is what I used to implement the code in question.

Last, and probably the most important, "source of truth" was actual
Linux PCIe driver for i.MX/Designware which I used as a sort of
inverse reference implementation.

Thanks,
Andrey Smirnov

Re: [Qemu-devel] [PATCH v4 09/14] pci: Add support for Designware IP block

[Peter Maydell]

On 17 January 2018 at 15:23, Marcel Apfelbaum  wrote:
>
> On 16/01/2018 16:34, Peter Maydell wrote:
>> On 16 January 2018 at 01:37, Andrey Smirnov 
>> I'm not familiar enough with our PCI code to be able to review
>> this, I'm afraid. MST and Marcel are our PCI subsystem maintainers --
>> could one of you have a look at whether this seems to be a correct
>> implementation of a pcie host controller ?
>
>
> Sadly PCI Host bridges do not have a standard, each HW vendor
> can do pretty much what they want.
>
> That being said, if Andrey can point me to the PCI spec for the Designware
> PCI host bridge and what parts they implemented for it I can have a look,
> sure.

I'm not so worried about whether it's implementing the spec for
the hardware (I trust Andrey has done enough testing for that
side of things), but whether the code seems to be structured
the way we expect a QEMU pcie host controller to be structured,
is using the right APIs, and so on.

thanks
-- PMM

Re: [Qemu-devel] [PATCH v4 09/14] pci: Add support for Designware IP block

[Marcel Apfelbaum]

Hi Peter,

On 16/01/2018 16:34, Peter Maydell wrote:

On 16 January 2018 at 01:37, Andrey Smirnov  wrote:

Add code needed to get a functional PCI subsytem when using in
conjunction with upstream Linux guest (4.13+). Tested to work against
"e1000e" (network adapter, using MSI interrupts) as well as
"usb-ehci" (USB controller, using legacy PCI interrupts).

Cc: Peter Maydell 
Cc: Jason Wang 
Cc: Philippe Mathieu-Daudé 
Cc: qemu-devel@nongnu.org
Cc: qemu-...@nongnu.org
Cc: yurov...@gmail.com
Signed-off-by: Andrey Smirnov 
---
  default-configs/arm-softmmu.mak  |   2 +
  hw/pci-host/Makefile.objs|   2 +
  hw/pci-host/designware.c | 618 +++
  include/hw/pci-host/designware.h |  93 ++
  include/hw/pci/pci_ids.h |   2 +
  5 files changed, 717 insertions(+)
  create mode 100644 hw/pci-host/designware.c
  create mode 100644 include/hw/pci-host/designware.h

I'm not familiar enough with our PCI code to be able to review
this, I'm afraid. MST and Marcel are our PCI subsystem maintainers --
could one of you have a look at whether this seems to be a correct
implementation of a pcie host controller ?


Sadly PCI Host bridges do not have a standard, each HW vendor
can do pretty much what they want.

That being said, if Andrey can point me to the PCI spec for the Designware
PCI host bridge and what parts they implemented for it I can have a look, sure.
(I will not be available for a week or so, but right after)

Thanks,
Marcel

I did notice it seems to be missing device state save/load support.

thanks
-- PMM

Re: [Qemu-devel] [PATCH v4 09/14] pci: Add support for Designware IP block

[Peter Maydell]

On 16 January 2018 at 01:37, Andrey Smirnov  wrote:
> Add code needed to get a functional PCI subsytem when using in
> conjunction with upstream Linux guest (4.13+). Tested to work against
> "e1000e" (network adapter, using MSI interrupts) as well as
> "usb-ehci" (USB controller, using legacy PCI interrupts).
>
> Cc: Peter Maydell 
> Cc: Jason Wang 
> Cc: Philippe Mathieu-Daudé 
> Cc: qemu-devel@nongnu.org
> Cc: qemu-...@nongnu.org
> Cc: yurov...@gmail.com
> Signed-off-by: Andrey Smirnov 
> ---
>  default-configs/arm-softmmu.mak  |   2 +
>  hw/pci-host/Makefile.objs|   2 +
>  hw/pci-host/designware.c | 618 
> +++
>  include/hw/pci-host/designware.h |  93 ++
>  include/hw/pci/pci_ids.h |   2 +
>  5 files changed, 717 insertions(+)
>  create mode 100644 hw/pci-host/designware.c
>  create mode 100644 include/hw/pci-host/designware.h

I'm not familiar enough with our PCI code to be able to review
this, I'm afraid. MST and Marcel are our PCI subsystem maintainers --
could one of you have a look at whether this seems to be a correct
implementation of a pcie host controller ?

I did notice it seems to be missing device state save/load support.

thanks
-- PMM