Re: [Qemu-devel] [Qemu-arm] [PATCH v2 07/67] target/arm: Implement SVE Predicate Logical Operations Group

[Peter Maydell]

On 22 February 2018 at 19:37, Richard Henderson
 wrote:
> On 02/22/2018 10:55 AM, Peter Maydell wrote:
>>> +# Three prediate operand, with governing predicate, flag setting
>>
>> Three what?
>
> Feh, typo for predicate.

Oh, right -- I'd thought it might be some mashup/typo of something-immediate.

-- PMM

Re: [Qemu-devel] [Qemu-arm] [PATCH v2 07/67] target/arm: Implement SVE Predicate Logical Operations Group

[Richard Henderson]

On 02/22/2018 10:55 AM, Peter Maydell wrote:
>> +# Three prediate operand, with governing predicate, flag setting
> 
> Three what?

Feh, typo for predicate.  But more verbosely,

Three operands that are predicates, plus another predicate operand which
"governs" the operation (I believe that's the language from the ARM), plus an
"s" bit that controls whether the flags are set.


r~

Re: [Qemu-devel] [Qemu-arm] [PATCH v2 07/67] target/arm: Implement SVE Predicate Logical Operations Group

[Peter Maydell]

On 17 February 2018 at 18:22, Richard Henderson
 wrote:
> Signed-off-by: Richard Henderson 

> -void trans_PTEST(DisasContext *s, arg_PTEST *a, uint32_t insn)
> +static void trans_PTEST(DisasContext *s, arg_PTEST *a, uint32_t insn)
>  {

Should this be in a previous patch?

>  int nofs = pred_full_reg_offset(s, a->rn);
>  int gofs = pred_full_reg_offset(s, a->pg);
> diff --git a/target/arm/sve.decode b/target/arm/sve.decode
> index 7efaa8fe8e..d92886127a 100644
> --- a/target/arm/sve.decode
> +++ b/target/arm/sve.decode
> @@ -31,6 +31,7 @@
>
> rd rn imm
>  _esz   rd rn rm esz
> +_srd pg rn rm s
>
>  ###
>  # Named instruction formats.  These are generally used to
> @@ -39,6 +40,9 @@
>  # Three operand with unused vector element size
>  @rd_rn_rm_e0    ... rm:5 ... ... rn:5 rd:5 _esz esz=0
>
> +# Three prediate operand, with governing predicate, flag setting

Three what?

> +@pd_pg_pn_pm_s  . s:1 .. rm:4 .. pg:4 . rn:4 . rd:4_s
> +
>  # Basic Load/Store with 9-bit immediate offset
>  @pd_rn_i9    .. rn:5 . rd:4\
>  imm=%imm9_16_10
> @@ -56,6 +60,18 @@ ORR_zzz  0100 01 1 . 001 100 . 
> . @rd_rn_rm_e0
>  EOR_zzz0100 10 1 . 001 100 . . 
> @rd_rn_rm_e0
>  BIC_zzz0100 11 1 . 001 100 . . 
> @rd_rn_rm_e0
>
> +### SVE Predicate Logical Operations Group
> +
> +# SVE predicate logical operations
> +AND_   00100101 0. 00  01  0  0    @pd_pg_pn_pm_s
> +BIC_   00100101 0. 00  01  0  1    @pd_pg_pn_pm_s
> +EOR_   00100101 0. 00  01  1  0    @pd_pg_pn_pm_s
> +SEL_   00100101 0. 00  01  1  1    @pd_pg_pn_pm_s
> +ORR_   00100101 1. 00  01  0  0    @pd_pg_pn_pm_s
> +ORN_   00100101 1. 00  01  0  1    @pd_pg_pn_pm_s
> +NOR_   00100101 1. 00  01  1  0    @pd_pg_pn_pm_s
> +NAND_  00100101 1. 00  01  1  1    @pd_pg_pn_pm_s
> +
>  ### SVE Predicate Misc Group

Otherwise
Reviewed-by: Peter Maydell 

thanks
-- PMM