Re: [RFC v2 01/12] target/ppc: powerpc_excp: Set alternate SRRs directly
On Mon, Dec 20, 2021 at 03:18:52PM -0300, Fabiano Rosas wrote:
> There are currently only two interrupts that use alternate SRRs, so
> let them write to them directly during the setup code.
>
> No functional change intented.
>
> Signed-off-by: Fabiano Rosas
Reviewed-by: David Gibson
> ---
> target/ppc/excp_helper.c | 23 ---
> 1 file changed, 8 insertions(+), 15 deletions(-)
>
> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
> index f90e616aac..8b9c6bc5a8 100644
> --- a/target/ppc/excp_helper.c
> +++ b/target/ppc/excp_helper.c
> @@ -298,7 +298,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int
> excp_model, int excp)
> CPUState *cs = CPU(cpu);
> CPUPPCState *env = >env;
> target_ulong msr, new_msr, vector;
> -int srr0, srr1, asrr0, asrr1, lev = -1;
> +int srr0, srr1, lev = -1;
>
> qemu_log_mask(CPU_LOG_INT, "Raise exception at " TARGET_FMT_lx
>" => %08x (%02x)\n", env->nip, excp, env->error_code);
> @@ -319,8 +319,6 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int
> excp_model, int excp)
> /* target registers */
> srr0 = SPR_SRR0;
> srr1 = SPR_SRR1;
> -asrr0 = -1;
> -asrr1 = -1;
>
> /*
> * check for special resume at 0x100 from doze/nap/sleep/winkle on
> @@ -410,8 +408,9 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int
> excp_model, int excp)
> /* FIXME: choose one or the other based on CPU type */
> srr0 = SPR_BOOKE_MCSRR0;
> srr1 = SPR_BOOKE_MCSRR1;
> -asrr0 = SPR_BOOKE_CSRR0;
> -asrr1 = SPR_BOOKE_CSRR1;
> +
> +env->spr[SPR_BOOKE_CSRR0] = env->nip;
> +env->spr[SPR_BOOKE_CSRR1] = msr;
> break;
> default:
> break;
> @@ -570,8 +569,10 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int
> excp_model, int excp)
> /* FIXME: choose one or the other based on CPU type */
> srr0 = SPR_BOOKE_DSRR0;
> srr1 = SPR_BOOKE_DSRR1;
> -asrr0 = SPR_BOOKE_CSRR0;
> -asrr1 = SPR_BOOKE_CSRR1;
> +
> +env->spr[SPR_BOOKE_CSRR0] = env->nip;
> +env->spr[SPR_BOOKE_CSRR1] = msr;
> +
> /* DBSR already modified by caller */
> } else {
> cpu_abort(cs, "Debug exception triggered on unsupported
> model\n");
> @@ -838,14 +839,6 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int
> excp_model, int excp)
>
> vector |= env->excp_prefix;
>
> -/* If any alternate SRR register are defined, duplicate saved values */
> -if (asrr0 != -1) {
> -env->spr[asrr0] = env->nip;
> -}
> -if (asrr1 != -1) {
> -env->spr[asrr1] = msr;
> -}
> -
> #if defined(TARGET_PPC64)
> if (excp_model == POWERPC_EXCP_BOOKE) {
> if (env->spr[SPR_BOOKE_EPCR] & EPCR_ICM) {
--
David Gibson| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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Re: [RFC v2 01/12] target/ppc: powerpc_excp: Set alternate SRRs directly
On 12/20/21 19:18, Fabiano Rosas wrote:
There are currently only two interrupts that use alternate SRRs, so
let them write to them directly during the setup code.
No functional change intented.
intended.
Signed-off-by: Fabiano Rosas
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
target/ppc/excp_helper.c | 23 ---
1 file changed, 8 insertions(+), 15 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index f90e616aac..8b9c6bc5a8 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -298,7 +298,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int
excp_model, int excp)
CPUState *cs = CPU(cpu);
CPUPPCState *env = >env;
target_ulong msr, new_msr, vector;
-int srr0, srr1, asrr0, asrr1, lev = -1;
+int srr0, srr1, lev = -1;
qemu_log_mask(CPU_LOG_INT, "Raise exception at " TARGET_FMT_lx
" => %08x (%02x)\n", env->nip, excp, env->error_code);
@@ -319,8 +319,6 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int
excp_model, int excp)
/* target registers */
srr0 = SPR_SRR0;
srr1 = SPR_SRR1;
-asrr0 = -1;
-asrr1 = -1;
/*
* check for special resume at 0x100 from doze/nap/sleep/winkle on
@@ -410,8 +408,9 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int
excp_model, int excp)
/* FIXME: choose one or the other based on CPU type */
srr0 = SPR_BOOKE_MCSRR0;
srr1 = SPR_BOOKE_MCSRR1;
-asrr0 = SPR_BOOKE_CSRR0;
-asrr1 = SPR_BOOKE_CSRR1;
+
+env->spr[SPR_BOOKE_CSRR0] = env->nip;
+env->spr[SPR_BOOKE_CSRR1] = msr;
break;
default:
break;
@@ -570,8 +569,10 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int
excp_model, int excp)
/* FIXME: choose one or the other based on CPU type */
srr0 = SPR_BOOKE_DSRR0;
srr1 = SPR_BOOKE_DSRR1;
-asrr0 = SPR_BOOKE_CSRR0;
-asrr1 = SPR_BOOKE_CSRR1;
+
+env->spr[SPR_BOOKE_CSRR0] = env->nip;
+env->spr[SPR_BOOKE_CSRR1] = msr;
+
/* DBSR already modified by caller */
} else {
cpu_abort(cs, "Debug exception triggered on unsupported model\n");
@@ -838,14 +839,6 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int
excp_model, int excp)
vector |= env->excp_prefix;
-/* If any alternate SRR register are defined, duplicate saved values */
-if (asrr0 != -1) {
-env->spr[asrr0] = env->nip;
-}
-if (asrr1 != -1) {
-env->spr[asrr1] = msr;
-}
-
#if defined(TARGET_PPC64)
if (excp_model == POWERPC_EXCP_BOOKE) {
if (env->spr[SPR_BOOKE_EPCR] & EPCR_ICM) {
Re: [RFC v2 01/12] target/ppc: powerpc_excp: Set alternate SRRs directly
On 12/20/21 10:18 AM, Fabiano Rosas wrote: There are currently only two interrupts that use alternate SRRs, so let them write to them directly during the setup code. No functional change intented. Signed-off-by: Fabiano Rosas --- target/ppc/excp_helper.c | 23 --- 1 file changed, 8 insertions(+), 15 deletions(-) Reviewed-by: Richard Henderson r~
