Re: [Qemu-discuss] Getting qemu-system-i386 to use more than one core on Cortex A7 host

2016-01-05 Thread Jakob Bohm
On 06/01/2016 00:53, Peter Maydell wrote: On 5 January 2016 at 23:10, Jakob Bohm wrote: On 05/01/2016 18:35, Peter Maydell wrote: (It would also be possible to use the v8 ARM load-acquire and store-release instructions rather than full on barriers, but on v7 I think barriers are the only answe

Re: [Qemu-discuss] Getting qemu-system-i386 to use more than one core on Cortex A7 host

2016-01-05 Thread Peter Maydell
On 5 January 2016 at 23:10, Jakob Bohm wrote: > On 05/01/2016 18:35, Peter Maydell wrote: >> (It would also be possible >> to use the v8 ARM load-acquire and store-release instructions >> rather than full on barriers, but on v7 I think barriers are >> the only answer.) >> > > The Load acquire/stor

Re: [Qemu-discuss] Getting qemu-system-i386 to use more than one core on Cortex A7 host

2016-01-05 Thread Jakob Bohm
On 05/01/2016 18:35, Peter Maydell wrote: On 4 January 2016 at 22:00, Jakob Bohm wrote: On 04/01/2016 22:29, Peter Maydell wrote: On 4 January 2016 at 13:24, Jakob Bohm wrote: https://en.wikipedia.org/wiki/Memory_ordering#In_symmetric_multiprocessing_.28SMP.29_microprocessor_systems lists se

Re: [Qemu-discuss] Getting qemu-system-i386 to use more than one core on Cortex A7 host

2016-01-05 Thread Peter Maydell
On 4 January 2016 at 22:00, Jakob Bohm wrote: > On 04/01/2016 22:29, Peter Maydell wrote: >> >> On 4 January 2016 at 13:24, Jakob Bohm wrote: >> https://en.wikipedia.org/wiki/Memory_ordering#In_symmetric_multiprocessing_.28SMP.29_microprocessor_systems >> lists several cases like load-after-load

Re: [Qemu-discuss] Getting qemu-system-i386 to use more than one core on Cortex A7 host

2016-01-04 Thread Jakob Bohm
On 04/01/2016 22:29, Peter Maydell wrote: On 4 January 2016 at 13:24, Jakob Bohm wrote: For your information, the x86 memory model only requires barriers in the following cases (this is somewhat implemented on modern machines with multiple actual x86 CPU sockets, as opposed to multicore chips,

Re: [Qemu-discuss] Getting qemu-system-i386 to use more than one core on Cortex A7 host

2016-01-04 Thread Peter Maydell
On 4 January 2016 at 13:24, Jakob Bohm wrote: > For your information, the x86 memory model only requires > barriers in the following cases (this is somewhat > implemented on modern machines with multiple actual x86 > CPU sockets, as opposed to multicore chips, it may also > be observed when using

Re: [Qemu-discuss] Getting qemu-system-i386 to use more than one core on Cortex A7 host

2016-01-04 Thread Jakob Bohm
On 04/01/2016 13:21, Peter Maydell wrote: On 3 January 2016 at 20:57, David Durham wrote: Any suggestions or comments on how to do this are very welcome ... I built qemu with --target-list i386-softmmu and when I run qemu, top only shows one qemu-system-i386 using 100% of one core This is expe

Re: [Qemu-discuss] Getting qemu-system-i386 to use more than one core on Cortex A7 host

2016-01-04 Thread Peter Maydell
On 3 January 2016 at 20:57, David Durham wrote: > Any suggestions or comments on how to do this are very welcome > ... I built qemu with --target-list i386-softmmu and when I run > qemu, top only shows one qemu-system-i386 using 100% of one core This is expected. Our current emulation is single t

[Qemu-discuss] Getting qemu-system-i386 to use more than one core on Cortex A7 host

2016-01-03 Thread David Durham
Any suggestions or comments on how to do this are very welcome ... I built qemu with --target-list i386-softmmu and when I run qemu, top only shows one qemu-system-i386 using 100% of one core ... thanks