Hi all,
I am working on some timing critical routines for standard QL w/wo SandyQboard
512 (no GC, no Aurora). Do you know how is memory shared between CPU and ULA?
Do you know how (if at all) is memory delayed when you need to access videoram
at the same time ULA is accessing it? Is there any
Palenicek Jan wrote:
I am working on some timing critical routines for standard QL w/wo
SandyQboard 512 (no GC, no Aurora). Do you know how is memory shared
between CPU and ULA? Do you know how (if at all) is memory delayed
when you need to access videoram at the same time ULA is accessing
Looking at a list of SBASIC extensions created with an EXTRAS
command,
there are 3 extensions I noticed that I don't know what they do.
Not
in my (admittedly old) manual. Anyone know?
CHK_HEAP (Some form of heap check suggested by the name)
HOME_CSET (presumably