On Thu, 16 May 2019, g80vmgm...@riseup.net wrote:
> From XSA297:
> """
> Work is ongoing on xen-devel to develop core-aware scheduling, which
> will mitigate the cross-domain leak by ensuring that vcpus from
> different domains are never concurrently scheduled on sibling threads.
> However, this
Ilpo Järvinen:
> On Thu, 16 May 2019, g80vmgm...@riseup.net wrote:
>
>> From XSA297:
>> """
>> Work is ongoing on xen-devel to develop core-aware scheduling, which
>> will mitigate the cross-domain leak by ensuring that vcpus from
>> different domains are never concurrently scheduled on sibling
Marek Marczykowski-Górecki:
> -BEGIN PGP SIGNED MESSAGE-
> Hash: SHA256
>
> Dear Qubes Community,
>
> We have just published Qubes Security Bulletin (QSB) #49: Microarchitectural
> Data Sampling speculative side channel (XSA-297).
> The text of this QSB is reproduced below.
> This QSB
On 5/15/19 6:24 PM, Marek Marczykowski-Górecki wrote:
Only Intel processors are affected.
I think the pattern showing AMD to be more conscientious in their
processor designs is now undeniable. Even if its only a matter of
degree, the difference appears to be rather substantial.
You should
