Title: Sr. Designer Engineer Location: Irvine, CA
Length: Full Time Position. In this position you will: - Develop comprehensive test plans and test strategies for post-silicon analog electrical parameters of physical layer (PHY) SerDes (Serializer and Deserializer) of high-speed broadband Mix-signal ASICs. - Develop and optimize PHY electrical bench test methodologies and procedures per industry standards - 10GbE (IEEE 802.3ae, IEEE 802.3ak, IEEE 802.3ap, IEEE 802.3aq), 40/100GbE (IEEE 802.3ba, IEEE 802.3bg), and 100GbE (IEEE 802.3bj, IEEE 802.3bm). - Perform post-silicon PHY bench testing of analog electrical parameters of high-speed broadband Mix-signal ASICs. - Lead and train junior engineers. - Generate comprehensive test reports and analysis. - Develop and implement bench test automation. - Collaborate with IC design team on chip performance optimization and failure analysis. Job Requirement: EE PhD or MS with minimum 6+ year working experience in high-speed broadband communication post-silicon analog test environment. Must be an expert in PHY test methodologies specified in at least one of above listed IEEE standards. Notes: This job requirement should focus on physical interface I/O electrical parameter test which is analog in nature and get into RF region with today’s ever higher data rate. We use Key sight DCA-J and J-BERT extensively. SKILLS AND CERTIFICATIONS: PHY electrical bench test methodologies and procedures per industry standards - 10GbE (IEEE 802.3ae) -- You received this message because you are subscribed to the Google Groups "REQSRESUMES" group. To unsubscribe from this group and stop receiving emails from it, send an email to reqsresumes+unsubscr...@googlegroups.com. To post to this group, send email to reqsresumes@googlegroups.com. Visit this group at http://groups.google.com/group/reqsresumes. For more options, visit https://groups.google.com/d/optout.
