Edwin Blink wrote:
Do you also have excact (pulse length) timings of interupt durations ?
Frame, Line and MIDI Out interrupts all last 128 tstates (MIDI In is likely
to be the same, but untested). Both frame and line interrupts begin at the
start of the right border area.
I don't have
Simon Owen wrote:
Frame, Line and MIDI Out interrupts all last 128 tstates (MIDI In
is likely
to be the same, but untested). Both frame and line interrupts
begin at the start of the right border area.
Actually, the MIDI Out interrupt is different (shorter). I don't remember
the exact
Simon Owen wrote:
There was 32
tstate rounding, and further offsetting by 16 tstates, or something like
that. Those timings are still a mystery to me - any ideas?
Heh, it was just trial and error. :-) The 32 tstates rounding must be the
resolution that the MIDI hardware can operate. I don't
I made some more test for the 4 Ts penalty
It looks like it occures once every 8 Ts (8 pixels?)
and when you have multiple INs at multiples of 8Ts
intervals with a minimum of 16 Ts ofcourse.
only the first IN might get the penalty and the others
won't because the first IN synched them(the same
Edwin Blink wrote:
I made some more test for the 4 Ts penalty It looks like it
occures once every 8 Ts (8 pixels?)
For I/O accesses, add 4 tstates for the read/write, rounding up to the next
multiple of 8 for ASIC ports (F8 to FF).
For memory accesses, add 3 tstates for the read/write,
I'm not aware of any outstanding issues in the latest SimCoupé betas,
despite Dave and I throwing everything we can at them.
Do you also have excact (pulse length) timings of interupt durations ?
Edwin
Wow nice one, I wonder how these reflect to the original zilog timings
C
-Original Message-
From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]
On Behalf Of Edwin Blink
Sent: 01 February 2004 20:06
To: sam-users@nvg.ntnu.no
Subject: Z80 Timings
Hi all
I decided to make a simple hardware
Edwin Blink wrote:
IN A,(n) 12 Ts (all ports)
The original tests I did for SimCoupé showed ports F8 to FF always
required ASIC attention, giving an extra 4 tstate penalty if not correctly
aligned (even in the border area). Just in case your test avoided it, could
you try it with a NOP
From: Chris White [EMAIL PROTECTED]
Wow nice one, I wonder how these reflect to the original zilog timings
Will include the original times in the list I will create too.
Previously I rounded common instructions to multiples of 4 and it worked for
me.
But now i'm puzzled ... I just found out
But now i'm puzzled ... I just found out that a LDI takes 19 Ts instead
of
20 !
Sorry It is 20 (Phew!) no 19 Like i mentioned before. I use the E
register to save the old counter value in and I forgot that it gets
increased
by LDI(r) instructions.
Well I better call it a day
Edwin
From: Simon Owen [EMAIL PROTECTED]
The original tests I did for SimCoupé showed ports F8 to FF always
required ASIC attention, giving an extra 4 tstate penalty if not correctly
aligned (even in the border area).
Yeah your Right! But there are still some oddities. In one case I tested
when the
On Tue, 28 May 2002 16:30:30 +0100 Winkless, Geoff [EMAIL PROTECTED] wrote:
The domain nvg.unit.no has expired.
Please use nvg.ntnu.no instead.
Send the original mail again.
Actually, I'm quite surprised the nvg.unit.no address still
resolves. It's
I wrote:
is it quicker to do:
AND EE = 7 cycles
Note: I should have written
AND C - 4 cycles
since the EE is preloaded to a register (ostensible to increase speed).
Geoff
I wrote:
is it quicker to do:
AND EE = 7 cycles
Second note: my apologies for sending the message twice. I got a message
back from the nvg admin telling me to do so, before the first email arrived
:(
The domain nvg.unit.no has expired.
Please use nvg.ntnu.no
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