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Please send me the updated resume to *abd...@systelcomputers.com <abd...@systelcomputers.com> * if you’re comfortable with the below job description. *Position: ASIC/FPGA Verification Engineer* *Location: San Jose, CA* *Duration: Longterm* *Job Description:* *· 5 years ASIC/FPGA verification experience· Knowledge of UVM, Verilog, System Verilog, Tcl/PERL/Python or other scripting tools· Build UVM verification test bench using System Verilog or equivalent to validate multiple FPGAs· Create bus functional models for PCIe, I2C, MDIO and other IO interfaces of the FPGAs· Write tests cases and validate functionality of FPGAs*· Develop regression environment · Familiar with Altera FPGA tools · Hands on lab bring up experience Abdul Aijaz Resourcing Specialist Desk: 678-250-9868 Email: *abd...@systelcomputers.com <abd...@systelcomputers.com> * Yahoo : *abdula.aijaz...@gmail.com <abdula.aijaz...@gmail.com> * -- You received this message because you are subscribed to the Google Groups "SAP or Oracle Financials" group. To unsubscribe from this group and stop receiving emails from it, send an email to sap-or-oracle-financials+unsubscr...@googlegroups.com. To post to this group, send email to sap-or-oracle-financials@googlegroups.com. Visit this group at https://groups.google.com/group/sap-or-oracle-financials. For more options, visit https://groups.google.com/d/optout.
