!! Need -ASIC Physical Design Engineer // Hillsboro, OR !!
*!! **DIRECT CLIENT NEED* *!!* Job Title: ASIC Physical Design Engineer Location: Hillsboro, OR Duration: 6-12 months Contract Required background: At least 4 years of experience in the following skills - Netlist-GDS flow with Synthesis, Layout (Floorplan, Place and Route, clock tree synthesis), Static Timing Analysis, Formal Verification, Physical Verification(DRC, LVS) and Power Analysis(IR drop, EMIG), Leakage Power Optimization using ICCLR/PTLR flows, on 22nm, 14nm, or lower process technology Desired Tools Experience: Synopsys ICC flow, Prime Time, Design Compiler, Redhawk, LEC/Formality, and Caliber. At least 4 years of experience in Project life cycle activities on development and maintenance projects. At least 4 years of experience in Physical Design and STA review. At least 4 years of experience in ASIC development life cycle. Ability to work in team in diverse/ multiple stakeholder environment Qualifications Basic Bachelor’s degree or foreign equivalent required. 4 to 6 years of experience in ASIC Physical Design *Note: Please reply me on my official E-Mail ID : **neil.kha...@itbtalent.com neil.kha...@itbtalent.com* Kindest Regards: Neil Khanna | Lead Professional Recruiter ITBrainiac Inc Princeton Forrestal Village,116 Village Blvd,Suite 200 Princeton, NJ 08540 Voice : (929) 268-0690 Email: neil.kha...@itbtalent.com -- You received this message because you are subscribed to the Google Groups SAP or Oracle Financials group. To unsubscribe from this group and stop receiving emails from it, send an email to sap-or-oracle-financials+unsubscr...@googlegroups.com. To post to this group, send email to sap-or-oracle-financials@googlegroups.com. Visit this group at http://groups.google.com/group/sap-or-oracle-financials. For more options, visit https://groups.google.com/d/optout.
!! Need - ASIC Physical Design Engineer // Hillsboro, OR !!
*!! **DIRECT CLIENT NEED* *!!* Job Title: ASIC Physical Design Engineer Location: Hillsboro, OR Duration: 6-12 months Contract Required background: Qualifications Basic Bachelor’s degree or foreign equivalent required. 4 to 6 years of experience in ASIC Physical Design Preferred Expertise At least 4 years of experience in the following skills - Netlist-GDS flow with Synthesis, Layout (Floorplan, Place and Route, clock tree synthesis), Static Timing Analysis, Formal Verification, Physical Verification(DRC, LVS) and Power Analysis(IR drop, EMIG), Leakage Power Optimization using ICCLR/PTLR flows, on 22nm, 14nm, or lower process technology Desired Tools Experience: Synopsys ICC flow, Prime Time, Design Compiler, Redhawk, LEC/Formality, and Caliber. At least 4 years of experience in Project life cycle activities on development and maintenance projects. At least 4 years of experience in Physical Design and STA review. At least 4 years of experience in ASIC development life cycle. Ability to work in team in diverse/ multiple stakeholder environment *Note: Please reply me on my official E-Mail ID : **neil.kha...@itbtalent.com neil.kha...@itbtalent.com* Kindest Regards: Neil Khanna | Lead Professional Recruiter ITBrainiac Inc Princeton Forrestal Village,116 Village Blvd,Suite 200 Princeton, NJ 08540 Voice : (929) 268-0690 Email: neil.kha...@itbtalent.com -- You received this message because you are subscribed to the Google Groups SAP or Oracle Financials group. To unsubscribe from this group and stop receiving emails from it, send an email to sap-or-oracle-financials+unsubscr...@googlegroups.com. To post to this group, send email to sap-or-oracle-financials@googlegroups.com. Visit this group at http://groups.google.com/group/sap-or-oracle-financials. For more options, visit https://groups.google.com/d/optout.
!! Need -ASIC Physical Design Engineer // Hillsboro, OR !!
*!! **DIRECT CLIENT NEED* *!!* *Job Title: ASIC Physical Design Engineer* Location: Hillsboro, OR Duration: 6-12 months Contract Required background: At least 4 years of experience in the following skills - Netlist-GDS flow with Synthesis, Layout (Floorplan, Place and Route, clock tree synthesis), Static Timing Analysis, Formal Verification, Physical Verification(DRC, LVS) and Power Analysis(IR drop, EMIG), Leakage Power Optimization using ICCLR/PTLR flows, on 22nm, 14nm, or lower process technology Desired Tools Experience: Synopsys ICC flow, Prime Time, Design Compiler, Redhawk, LEC/Formality, and Caliber. At least 4 years of experience in Project life cycle activities on development and maintenance projects. At least 4 years of experience in Physical Design and STA review. At least 4 years of experience in ASIC development life cycle. Ability to work in team in diverse/ multiple stakeholder environment *Note: Please reply me on my official E-Mail ID : **neil.kha...@itbtalent.com neil.kha...@itbtalent.com* Kindest Regards: Neil Khanna | Lead Professional Recruiter ITBrainiac Inc Princeton Forrestal Village,116 Village Blvd,Suite 200 Princeton, NJ 08540 Voice : (929) 268-0690 Email: neil.kha...@itbtalent.com -- You received this message because you are subscribed to the Google Groups SAP or Oracle Financials group. To unsubscribe from this group and stop receiving emails from it, send an email to sap-or-oracle-financials+unsubscr...@googlegroups.com. To post to this group, send email to sap-or-oracle-financials@googlegroups.com. Visit this group at http://groups.google.com/group/sap-or-oracle-financials. For more options, visit https://groups.google.com/d/optout.
!! Need - ASIC Physical Design Engineer // Hillsboro, OR !!
*!! **DIRECT CLIENT NEED* *!!* Job Title: ASIC Physical Design Engineer Location: Hillsboro, OR Duration: 6-12 Months Contract *Required background:* *Qualifications Basic* Bachelor’s degree or foreign equivalent required. 4 to 6 years of experience in ASIC Physical Design *Preferred Expertise* At least 4 years of experience in the following skills - Netlist-GDS flow with Synthesis, Layout (Floorplan, Place and Route, clock tree synthesis), Static Timing Analysis, Formal Verification, Physical Verification(DRC, LVS) and Power Analysis(IR drop, EMIG), Leakage Power Optimization using ICCLR/PTLR flows, on 22nm, 14nm, or lower process technology Desired Tools Experience: Synopsys ICC flow, Prime Time, Design Compiler, Redhawk, LEC/Formality, and Caliber. At least 4 years of experience in Project life cycle activities on development and maintenance projects. At least 4 years of experience in Physical Design and STA review. At least 4 years of experience in ASIC development life cycle. Ability to work in team in diverse/ multiple stakeholder environment *Note: Please reply me on my official E-Mail ID : **neil.kha...@itbtalent.com neil.kha...@itbtalent.com* *Kindest Regards:* *Neil Khanna* |* Team Lead * ITBrainiac Inc Princeton Forrestal Village,116 Village Blvd,Suite 200 Princeton, NJ 08540 *Voice : (929) 268-0690* Email: neil.kha...@itbtalent.com -- You received this message because you are subscribed to the Google Groups SAP or Oracle Financials group. To unsubscribe from this group and stop receiving emails from it, send an email to sap-or-oracle-financials+unsubscr...@googlegroups.com. To post to this group, send email to sap-or-oracle-financials@googlegroups.com. Visit this group at http://groups.google.com/group/sap-or-oracle-financials. For more options, visit https://groups.google.com/d/optout.
