"those instructions should all take one execution cycle each" is likely
where your problem lies. Who says so? The STM8 is pipelined and given
"cycle" counts assume that the first decode cycle of an instruction
overlaps with the execution cycle of the previous instruction. This is
only _mostly_
On 18/12/2022 11:14, Daniel Drotos wrote:
Can you send me hex of your two compiled test programs, A and B, please?
I have sent you a hex file off-list.
Regards,
Basil Hussain
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On 18/12/2022 10:55, Daniel Drotos wrote:
In script, instead of run, you should use expr /n sim_run=1
That did not work - same result.
0> info break 1
Num Type Disp Hit Cnt Address Cond
1 event keep 1 1 0x00500a write
cmd="timer stop benchmark; timer get benchmar
On Sun, 18 Dec 2022, Basil Hussain wrote:
Num Type Disp Hit Cnt Address Cond
1 event keep 1 1 0x00500a write
cmd="timer stop benchmark; timer get benchmark; timer set
benchmark 0; timer start benchmark; run"
Dear Basil,
In script, instead of run, you should use
On Sun, 18 Dec 2022, Basil Hussain wrote:
Benchmark wrapper assembly for code 'A':
Benchmark wrapper assembly for code 'B':
Dear Basil,
Can you send me hex of your two compiled test programs, A and B,
please?
Daniel
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I had the idea to check how the latest snapshot version of uCsim behaves
with regard to timer cycle counts. I downloaded SDCC snapshot of r13772,
which contains uCsim version 0.7.6.
However, something has changed or broken in the latest uCsim with regard
to breakpoint scripts, as my aforementi
I have a setup where I am using the timer facility in uCsim to
benchmark/profile the number of execution cycles of pieces of code. To
explain the setup briefly, I create a timer as well as a breakpoint on
writes to a GPIO port address, then with a breakpoint script, every time
it breaks I stop
