David Woodhouse wrote:
seems to *stop* before displaying the 'Autoboot in 9 seconds
Sounds like a timer problem. The hardware interrupt somehow supports
that theory.
//Peter
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SeaBIOS mailing list
On Tue, Jan 22, 2013 at 10:23:32AM -0500, Amos Kong wrote:
- Original Message -
On 01/09/2013 01:39 AM, Amos Kong wrote:
Current seabios will try to boot from selected devices first,
if they are all failed, seabios will also try to boot from
un-selected devices.
We need
On 01/22/2013 08:52 AM, Amos Kong wrote:
Libvirt will need to expose an attribute that lets the user control
whether to use this new option; how do we probe via QMP whether the
new
-boot strict=on command-line option is available?
Hi all,
How about add new info/query command?
(hmp)
Eric Blake ebl...@redhat.com writes:
On 01/22/2013 08:52 AM, Amos Kong wrote:
Libvirt will need to expose an attribute that lets the user control
whether to use this new option; how do we probe via QMP whether the
new
-boot strict=on command-line option is available?
Hi all,
How about
We seem to use the IRQEN bit of the PIRQn registers interchangeably
to select APIC mode or to disable an IRQ. I can't decide if we're
intending to disable the IRQ or select APIC mode here, but in either
case it prevents PIC mode assigned devices from working. When seabios
writes IRQEN to these
q35/ich9 doesn't use the same interrupt mapping function as
i440fx/piix. PIRQA:D and PIRQE:H are programmed identically, but we
start at index 0, not index -1. Slots 25 through 31 are also
programmed independently.
When running qemu w/o this patch, a device at address 0:6.0 will have
its PCI
On Tue, 2013-01-22 at 15:12 -0700, Alex Williamson wrote:
q35/ich9 doesn't use the same interrupt mapping function as
i440fx/piix. PIRQA:D and PIRQE:H are programmed identically, but we
start at index 0, not index -1. Slots 25 through 31 are also
programmed independently.
When running
q35/ich9 doesn't use the same interrupt mapping function as
i440fx/piix. PIRQA:D and PIRQE:H are programmed identically, but we
start at index 0, not index -1. Slots 25 through 31 are also
programmed independently.
When running qemu w/o this patch, a device at address 0:6.0 will have
its PCI
