[SeaBIOS] [PATCH v2] Update EFI_COMPATIBILITY16_TABLE to match 0.98 spec update

We expect to use the space between the top of option ROMs and the bottom of our own BIOS code as a stack. OVMF was previously marking the whole region from 0xC to 0xF read-only before invoking our Legacy16Boot method. Read-only stack considered harmful. Version 0.98 of the CSM spec adds

[SeaBIOS] [PATCH] run qemu_cfg_e820 only for CONFIG_QEMU=y

Otherwise we'll clobber the e820 table from coreboot. Signed-off-by: Gerd Hoffmann kra...@redhat.com --- src/fw/paravirt.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/fw/paravirt.c b/src/fw/paravirt.c index b84196a..00e327d 100644 --- a/src/fw/paravirt.c +++ b/src/fw/paravirt.c @@

[SeaBIOS] [PATCH 1/3] Introduce serial_out(), serial_in() macros in serialio.c

This will make it easier to abstract out the MMIO serial access. Even if that ends up in separate code which is a *copy* of this, at least they'll match. Signed-off-by: David Woodhouse david.woodho...@intel.com --- src/hw/serialio.c | 19 +++ 1 file changed, 11 insertions(+), 8

[SeaBIOS] [PATCH 2/3] Add Intel Quark UART support

This includes generic support for MMIO serial which can be used for other PCI (or non-PCI) serial ports too. Only outputs to the serial port in 32-bit mode, unless we're lucky enough that it's at an address below 1MiB. Signed-off-by: David Woodhouse david.woodho...@intel.com --- src/Kconfig

[SeaBIOS] [PATCH 3/3] Initialise debug output in handle_csm()

For a PCI serial port, we have to discover its location. Potentially on every entry, since UEFI may shift it at some point during the boot process from an early debug setup to a final location after real PCI enumeration. Signed-off-by: David Woodhouse david.woodho...@intel.com --- src/fw/csm.c |

[SeaBIOS] 'make oldconfig' broken...

Why does it keep forgetting my config and reverting to defaults, every time I touch src/Kconfig? [dwmw2@shinybook seabios]$ make oldconfig scripts/kconfig/conf --oldconfig /home/dwmw2/git/seabios/src/Kconfig # # configuration written to /home/dwmw2/git/seabios/.config # [dwmw2@shinybook

Re: [SeaBIOS] 'make oldconfig' broken...

On Fri, Dec 06, 2013 at 02:36:08PM +, David Woodhouse wrote: Why does it keep forgetting my config and reverting to defaults, every time I touch src/Kconfig? I noticed that the other day too. I'm not sure what's going on - it may have been the result of the recent Kconfig synch with the

[SeaBIOS] [PATCH] xhci: allocate scratch pad buffers

Untested. Anyone who tried to get xhci run on real hardware is welcome to test whenever this patch improves things. Signed-off-by: Gerd Hoffmann kra...@redhat.com --- src/hw/usb-xhci.c | 13 + 1 file changed, 13 insertions(+) diff --git a/src/hw/usb-xhci.c b/src/hw/usb-xhci.c index

[SeaBIOS] [PATCH] Separate out sec32init sections even when not doing code relocation.

The current code does not boot on QEMU with 256K roms when code relocation is disabled, because QEMU only maps the last 128K of the rom to low memory. The seabios make_bios_writable() call copies the full rom to low memory. This patch separates out the init sections even if code relocations are

[SeaBIOS] SMBIOS Type 4

Looking at the 1.7.3 source it appears that smbios_setup creates a type 4 entry for each core rather than one per package/socket as would be typical of a bare metal bios. Is this behavior by design? Thanks in advance Bret ___ SeaBIOS

Re: [SeaBIOS] [coreboot] Patch number 4 for floppy in SeaBIOS

On Fri, Dec 06, 2013 at 11:01:25AM +0100, Gelip wrote: Still Disk I/O error: 07.178: Booting from Floppy... 07.198: enter handle_13: 07.198:a=0201 b= c=0001 d= ds= es=07c0 ss=dd80 07.198: si= di= bp= sp=fae8 cs=f000 ip=c9a1

Re: [SeaBIOS] [PATCH] xhci: allocate scratch pad buffers

= 2013/12/6 Gerd Hoffmann kra...@redhat.com: Untested. Anyone who tried to get xhci run on real hardware is welcome to test whenever this patch improves things. With a keyboard attached to an OHCI/EHCI port, F12 will show the boot menu.. on XHCI, not at all (yet). Booting with