From: Marcel Apfelbaum marce...@redhat.com
This refactoring moves all the code needed (recursively)
to register TYPE_PCI_BUS type to a new file hw/pci/pci_bus.c .
This allows to properly add new functionality to the pci bus class.
Signed-off-by: Marcel Apfelbaum mar...@redhat.com
---
From: Marcel Apfelbaum marce...@redhat.com
The bios looks for 'etc/extra-pci-roots' to decide if
is going to scan further buses after bus 0 tree.
Signed-off-by: Marcel Apfelbaum mar...@redhat.com
---
hw/i386/pc.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/hw/i386/pc.c
From: Marcel Apfelbaum marce...@redhat.com
Signed-off-by: Marcel Apfelbaum mar...@redhat.com
---
hw/pci/pci.c | 8
include/hw/pci/pci_host.h | 4
2 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
index bf31168..d0d0035 100644
This series depends on:
- [SeaBIOS] [PATCH 0/2] fw/pci: better support for multiple host bridges
(https://www.mail-archive.com/seabios@seabios.org/msg07103.html)
- Not yet final, comments need to be adressed
- [Qemu-devel] [PATCH v2 00/47] ACPI refactoring: replace template patching
with
If the machine has several root busses, we need to add them to
acpi in order to be properly detected by guests.
Signed-off-by: Marcel Apfelbaum mar...@redhat.com
---
hw/i386/acpi-build.c | 30 ++
1 file changed, 30 insertions(+)
diff --git a/hw/i386/acpi-build.c
Save the IO/mem ranges assigned to the extra root busses
to be removed from the root bus 0 range.
Todo: find the actual bus numbers range for the root busses.
Signed-off-by: Marcel Apfelbaum mar...@redhat.com
---
hw/i386/acpi-build.c | 110 +++
1
Signed-off-by: Marcel Apfelbaum mar...@redhat.com
---
hw/acpi/acpi-build-utils.c | 107 +++--
include/hw/acpi/acpi-build-utils.h | 12 +
2 files changed, 116 insertions(+), 3 deletions(-)
diff --git a/hw/acpi/acpi-build-utils.c
The bios does not index the pxb slot number when
it computes the IRQ because it resides on bus 0
and not on the current bus.
However Qemu routes the irq through bus 0 and adds
the pxb slot to the IRQ computation.
Synchronize between bios and Qemu by canceling
pxb's effect.
Signed-off-by: Marcel
Signed-off-by: Marcel Apfelbaum mar...@redhat.com
---
hw/i386/acpi-build.c | 77
1 file changed, 77 insertions(+)
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 9837120..cb77fa3 100644
--- a/hw/i386/acpi-build.c
+++
From: Marcel Apfelbaum marce...@redhat.com
This is a marker interface used to differentiate the
default host bridge on a system with multiple host bridges.
This differentiation is required only for pc machines for now
by the ACPI subsystem.
Signed-off-by: Marcel Apfelbaum mar...@redhat.com
---
If multiple root busses are used, root bus 0 cannot use all the
pci holes ranges. Remove the IO/mem ranges used by the other
primary busses.
todo: properly compute the bus ranges for root bus 0.
Signed-off-by: Marcel Apfelbaum mar...@redhat.com
---
hw/i386/acpi-build.c | 74
From: Marcel Apfelbaum marce...@redhat.com
Use the newer pci_bus_num to correctly get the root bus number.
Signed-off-by: Marcel Apfelbaum mar...@redhat.com
---
hw/pci/pci.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
index dccb3d1..bf31168
From: Marcel Apfelbaum marce...@redhat.com
PXB is a light-weight host bridge whose purpose is to enable
the main host bridge to support multiple PCI root buses.
As oposed to PCI-2-PCI bridge's secondary bus, PXB's bus
is a primary bus and can be associated with a NUMA node
(different from the
Windows disables the pci-bridge if shpc bar has a memory conflict.
Until this problem is solved, this hack can be used for tests.
Signed-off-by: Marcel Apfelbaum mar...@redhat.com
---
hw/pci-bridge/pci_bridge_dev.c | 2 ++
1 file changed, 2 insertions(+)
diff --git
From: Marcel Apfelbaum marce...@redhat.com
Refactoring it as a method of PCIBusClass will allow
different implementations for subclasses.
Removed the assumption that the root bus does not
have a parent device because is specific only
to the default class implementation.
Signed-off-by: Marcel
From: Marcel Apfelbaum marce...@redhat.com
Instead of assuming it has only one bus, it
enumerates all the host bridges until it finds
the one with bus number corresponding with the
config register.
Signed-off-by: Marcel Apfelbaum mar...@redhat.com
---
hw/pci-host/piix.c | 57
From: Marcel Apfelbaum marce...@redhat.com
Refactoring it as a method of PCIBusClass will allow
different implementations for subclasses.
Signed-off-by: Marcel Apfelbaum mar...@redhat.com
---
hw/i386/kvm/pci-assign.c | 1 +
hw/pci/pci-hotplug-old.c | 1 +
hw/pci/pci.c | 7 ---
On Mon, Jan 26, 2015 at 02:07:41PM -0600, Timothy Pearson wrote:
On 01/26/2015 01:51 PM, Kevin O'Connor wrote:
It will likely be hard to figure out why your vendor vgabios is
hanging. It's possible something in seabios is causing it to get
confused, but it's also possible something during the
On Mon, Jan 26, 2015 at 12:57:06PM -0600, Timothy Pearson wrote:
All,
I have a board here that uses an XGI Volari Z9s integrated graphics device.
The board boots under coreboot and loads Linux, but if I add the appropriate
VGA option ROM (extracted from the vendor BIOS) SeaBIOS hangs:
On 01/26/2015 01:51 PM, Kevin O'Connor wrote:
It will likely be hard to figure out why your vendor vgabios is
hanging. It's possible something in seabios is causing it to get
confused, but it's also possible something during the coreboot
initialization is confusing it.
I suggest increasing the
On 01/26/2015 04:34 PM, Paul Menzel wrote:
Dear Timothy,
thank you for reporting this issue to the SeaBIOS mailing list.
Am Montag, den 26.01.2015, 12:57 -0600 schrieb Timothy Pearson:
I have a board here that uses an XGI Volari Z9s integrated graphics
device. The board boots under
Dear Timothy,
thank you for reporting this issue to the SeaBIOS mailing list.
Am Montag, den 26.01.2015, 12:57 -0600 schrieb Timothy Pearson:
I have a board here that uses an XGI Volari Z9s integrated graphics
device. The board boots under coreboot and loads Linux, but if I add
the
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