Hi Marcel,
Yup - I am using Seabios by default.
I took all the measures from the Kernel time reported in syslog.
As Seabios wasn't exhibiting any obvious scaling problem.
Ray K
-Original Message-
From: Marcel Apfelbaum [mailto:mar...@redhat.com]
Sent: Wednesday, August 2, 2017 5:43
On 07/08/2017 19:42, Alexander Bezzubikov wrote:
2017-08-07 19:39 GMT+03:00 Marcel Apfelbaum :
On 05/08/2017 23:27, Aleksandr Bezzubikov wrote:
Introduce a new PCIExpress-to-PCI Bridge device,
which is a hot-pluggable PCI Express device and
supports devices hot-plug with
On 05/08/2017 23:27, Aleksandr Bezzubikov wrote:
On PCI init PCI bridges may need some extra info about bus number,
IO, memory and prefetchable memory to reserve. QEMU can provide this
with a special vendor-specific PCI capability.
Hi Aleksandr,
Signed-off-by: Aleksandr Bezzubikov
2017-08-07 19:39 GMT+03:00 Marcel Apfelbaum :
> On 05/08/2017 23:27, Aleksandr Bezzubikov wrote:
>>
>> Introduce a new PCIExpress-to-PCI Bridge device,
>> which is a hot-pluggable PCI Express device and
>> supports devices hot-plug with SHPC.
>>
>
>
> Hi Aleksandr,
>
>> This
On 05/08/2017 23:27, Aleksandr Bezzubikov wrote:
Introduce a new PCIExpress-to-PCI Bridge device,
which is a hot-pluggable PCI Express device and
supports devices hot-plug with SHPC.
Hi Aleksandr,
This device is intended to replace the DMI-to-PCI
Bridge in an overwhelming majority of
On 07/08/2017 19:02, Alexander Bezzubikov wrote:
2017-08-07 18:52 GMT+03:00 Marcel Apfelbaum :
On 05/08/2017 23:29, Aleksandr Bezzubikov wrote:
On PCI init PCI bridge devices may need some
extra info about bus number to reserve, IO, memory and
prefetchable memory limits.
On 05/08/2017 23:29, Aleksandr Bezzubikov wrote:
In case of Red Hat Generic PCIE Root Port reserve additional buses,
which number is provided in a vendor-specific capability.
Hi Aleksandr,
It seems the subject/commit description does not cover
all that the patch does, not it also deals with
2017-08-07 18:52 GMT+03:00 Marcel Apfelbaum :
> On 05/08/2017 23:29, Aleksandr Bezzubikov wrote:
>>
>> On PCI init PCI bridge devices may need some
>> extra info about bus number to reserve, IO, memory and
>> prefetchable memory limits. QEMU can provide this
>> with special
On 05/08/2017 23:29, Aleksandr Bezzubikov wrote:
On PCI init PCI bridge devices may need some
extra info about bus number to reserve, IO, memory and
prefetchable memory limits. QEMU can provide this
with special vendor-specific PCI capability.
This capability is intended to be used only
for Red