From: Rob Barnes
Date: Wed, 22 Jan 2020 14:09:21 -0700
Some devices have the same vendor and device ID but need different
Option ROM files. Change the look-up to include the revision, then
fallback to looking up without the revision.
BUG=b:148125384
TEST=Manual, boot trembyle and confirm SeaBIO
From: Raul E Rangel
Date: Tue, 14 Jan 2020 14:19:00 -0700
There seems to be a mismatch between the ACPI table coreboot writes, and
what SeaBIOS is scanning:
SeaBIOS:
Scanning: 0x : 0x1000
Scanning: 0xade5 : 0xb000
Coreboot:
IMD ROOT0. a000 1000
IMD SMALL 1. af
From: Stefan Reinauer
Date: Tue, 4 Nov 2014 16:16:46 -0800
gcc complains about using potentially unused variables.
BUG=none
BRANCH=none
TEST=emerge-panther chromeos-seabios builds an image again
Signed-off-by: Stefan Reinauer
Change-Id: I6c3d556a6519a5baa3a345e4dcb33b37b22db1b3
Reviewed-on: h
From: Marc Jones
Date: Wed, 24 Sep 2014 15:14:41 -0600
Some devices don’t have legacy interrupt support, but still need to use
a legacy keyboard. This patch adds a KBC check and manual call to the
keyboard service if there is a key waiting in the KBC.
BUG=chrome-os-partner:30836
BRANCH=None
TES
From: "Ronald G. Minnich"
Date: Thu, 24 May 2012 11:27:26 -0700
Serial port detection in SeaBIOS tests for bit 2 in the IER. That bit is
never set, and SeaBIOS mistakenly reports 0 serial ports. As it happens,
just testing for IER to be not-all-ones is good enough.
This happens on all systems w
From: Stefan Reinauer
Date: Fri, 31 Jan 2014 13:53:58 -0800
Allow specifying a file instead of /dev/null for defconfig.
BUG=none
BRANCH=none
TEST=emerge-panther chromeos-seabios works and produces
usable SeaBIOS image
Change-Id: I01d902eb9a6dff9ced7e3dd061aa33f831a64e8c
Signed-off-by: Ste
thanks for upstreaming these Paul. IIRC, it was some Asus models, the
C200/C300, which prompted this change, but I know it improved the
reliability of detection on quite a few others as well
On Mon, Mar 16, 2020 at 4:41 AM Paul Menzel wrote:
>
> From: Matt DeVillier
> Date: Fri, 14 Dec 2018 01:2
On Mon, Mar 16, 2020 at 7:34 AM Paul Menzel wrote:
>
> Dear Fāng-ruì,
>
>
> Am 16.03.20 um 15:30 schrieb Fāng-ruì Sòng:
> > On Mon, Mar 16, 2020 at 1:05 AM Gerd Hoffmann wrote:
> >>
> >> On Sun, Mar 15, 2020 at 10:52:56AM -0700, Fangrui Song wrote:
> >>> (
> >>> depends on
> >>> https://mail.core
Dear Fāng-ruì,
Am 16.03.20 um 15:30 schrieb Fāng-ruì Sòng:
On Mon, Mar 16, 2020 at 1:05 AM Gerd Hoffmann wrote:
On Sun, Mar 15, 2020 at 10:52:56AM -0700, Fangrui Song wrote:
(
depends on
https://mail.coreboot.org/hyperkitty/list/seabios@seabios.org/thread/SWDV7MB6KSP2ZJF3SEVB3W3H3SOJMXEB/
"
On Mon, Mar 16, 2020 at 1:05 AM Gerd Hoffmann wrote:
>
> On Sun, Mar 15, 2020 at 10:52:56AM -0700, Fangrui Song wrote:
> > (
> > depends on
> > https://mail.coreboot.org/hyperkitty/list/seabios@seabios.org/thread/SWDV7MB6KSP2ZJF3SEVB3W3H3SOJMXEB/
> > "[PATCH] Makefile: Refactor cc-option"
> >
> >
On Tue, Mar 10, 2020 at 11:36:58AM -0400, Kevin O'Connor wrote:
> On Tue, Mar 10, 2020 at 11:22:45AM +0100, Gerd Hoffmann wrote:
> > Add function to set tsc frequency directly, without calibration.
> > Also tweak timer setup functions a bit: skip setup in case TimerPort
> > has not the default valu
From: Matt DeVillier
Date: Fri, 14 Dec 2018 01:20:31 -0600
This helps card detection on some Chromebooks.
Signed-off-by: Matt DeVillier
Signed-off-by: Paul Menzel
---
Upstream from https://github.com/MrChromebox/SeaBIOS/
Matt, it’d be great if you could list the affected Chromebooks you know
From: Matt DeVillier
Date: Fri, 12 Aug 2016 14:21:58 -0500
PS/2 keyboards on Chromebooks with upstream coreboot + SeaBIOS often
fail to init properly / register keystrokes. Modify ps2port init
to match that of TianoCore, which doesn't have said issues.
Signed-off-by: Matt DeVillier
Signed-off
From: Matt DeVillier
Date: Fri, 13 Jun 2014 17:20:23 -0500
Signed-off-by: Matt DeVillier
Signed-off-by: Paul Menzel
---
Upstream from https://github.com/MrChromebox/SeaBIOS/
src/boot.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/src/boot.c b/src/boot.c
index afeb36a..ace3fa5 10
On Sun, Mar 15, 2020 at 10:52:56AM -0700, Fangrui Song wrote:
> (
> depends on
> https://mail.coreboot.org/hyperkitty/list/seabios@seabios.org/thread/SWDV7MB6KSP2ZJF3SEVB3W3H3SOJMXEB/
> "[PATCH] Makefile: Refactor cc-option"
>
> see linux/arch/x86/Makefile for a similar use case
> )
Better patch
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