Agreed, this patch makes no sense at all.
If someone is building from my coreboot tree, then they can simply revert
the patch there which was made to accommodate edk2 payload, and no change
is needed to SeaBIOS.
On Tue, Feb 14, 2023 at 5:14 AM Peter Stuge wrote:
> Hi Christopher,
>
>
patch set tested successfully along with the subsequent single bounce
buffer patch on a Purism Librem 15v4 w/Samsung 960 EVO
On Wed, Jan 19, 2022 at 12:45 PM Kevin O'Connor wrote:
>
> Hi Alex,
>
> I was looking at your recent fix for SeaBIOS NVME. I agree that it is
> not valid to write to the
patch splits moves all PRP maintenance data from the actual namespace
> allocation and allocates them in ZoneHigh instead. That way, the PRP list
> is fully read-write at runtime.
>
> Fixes: 01f2736cc905d ("nvme: Pass large I/O requests as PRP lists")
> Reported-
On Tue, Jan 18, 2022 at 4:06 PM Alexander Graf wrote:
>
> Hi Matt,
hi Alex,
> On 18.01.22 18:46, Matt DeVillier wrote:
> > and attempting to boot from it:
> >
> > Booting from Hard Disk...
> > sq 0x7aa77bdf next_sqe 0
> > sq 0x7aa77bdf commit_sqe
; 2
sq 0x7aa77bdf advanced to 2
ns 1 read lba 1+1: 0
sq 0x7aa77bdf next_sqe 2
sq 0x7aa77bdf commit_sqe 2
cq 0x7aa77bf1 head 2 -> 3
sq 0x7aa77bdf advanced to 3
read io: 00010003 40270002
ns 1 read lba 2+105: 12
On Tue, Jan 18, 2022 at 11:45 AM Matt DeVillier
wrote:
>
> here's th
Registering bootable: NVMe NS 1: 476940 MiB (976773168
512-byte blocks + 0-byte metadata) (type:2 prio:103 data:f59e0)
|7aa26000| NVMe initialization complete!
\7aa26000/ End thread
On Mon, Jan 17, 2022 at 7:24 PM Matt DeVillier wrote:
>
> Greetings! Was this patch set tested on bare m
Greetings! Was this patch set tested on bare metal hardware? I'm
seeing "GRUB loading: Read Error" when attempting to boot from NVMe on
various Purism Librem devices (Intel Skylake thru Cometlake hardware).
Reverting this series resolves the issue. I'm not seeing anything in
coreboot's cbmem
>From 38f63fcd9b646d6a4eac30f0476bbaee611211ce Mon Sep 17 00:00:00 2001
From: Matt DeVillier
Date: Fri, 11 Sep 2020 12:54:21 -0500
Subject: [PATCH] usb.c: Fix devices using non-primary interface descriptor
A fair number of USB devices (keyboards in particular) use an
interface descriptor
ot
On Mon, Sep 7, 2020 at 4:36 PM Matt DeVillier wrote:
>
> On Mon, Sep 7, 2020 at 4:10 PM Matt DeVillier
> wrote:
> >
> > On Thu, Sep 3, 2020 at 10:53 PM Kevin O'Connor wrote:
> > >
> > > On Thu, Sep 03, 2020 at 10:32:24PM -0400, Kevin O'Connor wrote:
>
On Mon, Sep 7, 2020 at 4:10 PM Matt DeVillier wrote:
>
> On Thu, Sep 3, 2020 at 10:53 PM Kevin O'Connor wrote:
> >
> > On Thu, Sep 03, 2020 at 10:32:24PM -0400, Kevin O'Connor wrote:
> > > On Thu, Sep 03, 2020 at 09:03:50PM -0500, Matt DeVillier wrote:
> > &
On Thu, Sep 3, 2020 at 10:53 PM Kevin O'Connor wrote:
>
> On Thu, Sep 03, 2020 at 10:32:24PM -0400, Kevin O'Connor wrote:
> > On Thu, Sep 03, 2020 at 09:03:50PM -0500, Matt DeVillier wrote:
> > > On Thu, Sep 3, 2020 at 7:28 PM Kevin O'Connor wrote:
> > > > I
On Thu, Sep 3, 2020 at 7:28 PM Kevin O'Connor wrote:
>
> On Tue, Sep 01, 2020 at 01:31:18AM -0500, Matt DeVillier wrote:
> > From 9e408a5441330b120a477324c017c0525cb5b365 Mon Sep 17 00:00:00 2001
> > From: Matt DeVillier
> > Date: Tue, 1 Sep 2020 01:21:23 -0500
> >
>From 9e408a5441330b120a477324c017c0525cb5b365 Mon Sep 17 00:00:00 2001
From: Matt DeVillier
Date: Tue, 1 Sep 2020 01:21:23 -0500
Subject: [PATCH] usb-hid: Fix keyboards using non-primary interface descriptor
A fair number of USB keyboards use an interface descriptor other than
the fi
boot menu option shown by default.
Signed-off-by: Matt DeVillier
---
src/boot.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/boot.c b/src/boot.c
index 994b592f..58c13add 100644
--- a/src/boot.c
+++ b/src/boot.c
@@ -697,7 +697,7 @@ interactive_bootmenu(void)
// XXX
On Sun, Apr 19, 2020 at 10:40 AM Kevin O'Connor wrote:
> On Tue, Mar 17, 2020 at 08:27:59PM -0400, Kevin O'Connor wrote:
> > On Mon, Mar 16, 2020 at 10:32:41AM +0100, Paul Menzel wrote:
> > > From: Matt DeVillier
> > > Date: Fri, 13 Jun 2014 17:20:23 -0500
>
unfortunately I still need to re-test with that commit reverted
On Sun, Apr 19, 2020 at 10:38 AM Kevin O'Connor wrote:
> On Thu, Mar 26, 2020 at 03:52:58PM -0500, Matt DeVillier wrote:
> > On Thu, Mar 26, 2020 at 2:33 PM Paul Menzel
> wrote:
> > > Am 26.03.20 um 20:29 s
On Tue, Mar 31, 2020 at 12:29 PM Kevin O'Connor wrote:
>
> On Tue, Mar 31, 2020 at 04:53:02PM +0200, Gerd Hoffmann wrote:
> > On Fri, Mar 27, 2020 at 09:15:19AM -0400, Kevin O'Connor wrote:
> > > On Fri, Mar 27, 2020 at 09:12:06AM +0100, Gerd Hoffmann wrote:
> > > > > Something like:
> > > > >
>
On Thu, Mar 26, 2020 at 2:33 PM Paul Menzel wrote:
>
> Dear Matt,
>
>
> Am 26.03.20 um 20:29 schrieb Matt DeVillier:
>
> > as requested I went ahead and retested a few different Chromebook
> > devices/platforms using upstream coreboot + SeaBIOS master, with the
&
not even sure the patch addresses that;
pretty sure the fix needs to be on the EC end.
regards,
Matt
On Tue, Mar 17, 2020 at 7:30 PM Kevin O'Connor wrote:
>
> On Mon, Mar 16, 2020 at 10:38:25AM +0100, Paul Menzel wrote:
> > From: Matt DeVillier
> > Date: Fri, 12 Aug 2
Disabling hardware IRQ is sufficient on Baytrail ChromeOS devices like
Rambi, so I'd say no
On Tue, Mar 17, 2020, 9:34 AM Gerd Hoffmann wrote:
> > Some devices don’t have legacy interrupt support, but still need to use
> > a legacy keyboard. This patch adds a KBC check and manual call to the
>
thanks for upstreaming these Paul. IIRC, it was some Asus models, the
C200/C300, which prompted this change, but I know it improved the
reliability of detection on quite a few others as well
On Mon, Mar 16, 2020 at 4:41 AM Paul Menzel wrote:
>
> From: Matt DeVillier
> Date: Fri, 14 De
On Sun, Dec 15, 2019 at 6:26 PM Kevin O'Connor wrote:
>
> On Sat, Dec 14, 2019 at 11:26:17AM -0600, Matt DeVillier wrote:
> > Some USB keyboards report 9 or 10-byte max packet sizes, instead
> > of the 8-byte max specified by the USB HID spec. Handle this by
>
(since the former will always be smaller, and within spec).
Test: built/boot on Google Pixel Slate, observe keyboard functional
Signed-off-by: Matt DeVillier
---
src/hw/usb-hid.c | 17 -
1 file changed, 12 insertions(+), 5 deletions(-)
diff --git a/src/hw/usb-hid.c b/src/hw/usb
that of the keyevent struct
(since the former will always be smaller, and within spec) to
prevent buffer overflow.
Test: built/boot on Google Pixel Slate, observe keyboard functional
Signed-off-by: Matt DeVillier
---
src/hw/usb-hid.c | 19 ++-
1 file changed, 14 insertions(+), 5
Since the USB stack doesn't handle stalled pipes,
don't abort keyboard setup if the set_idle command fails,
since it's a non-critical feature. Instead, log a warning.
Test: build/boot Google Pixel Slate, observe keyboard functional
Signed-off-by: Matt DeVillier
---
src/hw/usb-hid.c | 2 +-
1
that of the keyevent struct
(since the former will always be smaller, and within spec).
Test: built/boot on Google Pixel Slate, observe keyboard functional
Signed-off-by: Matt DeVillier
---
src/hw/usb-hid.c | 17 -
1 file changed, 12 insertions(+), 5 deletions(-)
diff --git a/src/hw
'signed-off-by' is a linux kernel convention; by adding your Signed-off-by
line to a patch, you are certifying that you have read and understood the
Developer Certificate of Origin (DCO), originated in 2004 by the Linux
foundation as an affirmation that the source code being submitted
originated
On Thu, 2019-10-03 at 17:35 -0400, Kevin O'Connor wrote:
> On Tue, Sep 24, 2019 at 04:02:35PM -0500, Matt DeVillier wrote:
> > From 015d42aefa7cdebee79f12f9eca113e234574c89 Mon Sep 17 00:00:00 2001
> > From: Matt DeVillier
> > Date: Tue, 24 Sep 2019 12:29:55 -0500
> &
From 015d42aefa7cdebee79f12f9eca113e234574c89 Mon Sep 17 00:00:00 2001
From: Matt DeVillier
Date: Tue, 24 Sep 2019 12:29:55 -0500
Subject: [PATCH] Reduce video modeswitching when using a boot splash
image
In the normal boot flow, the VGA console is enabled immediately after
running the VGA
hi Chris,
normally ESC will provide you with the boot device menu, but you're using a
very old, buggy, and unsupported firmware on your device. I'd recommend
updating to mine, which is not only newer, but will allow you to set USB as
the higher priority/default at the time of installation
see:
CorebootPayloadPkg doesn't have the hooks requires for CSM, you'd need to
use OMVH as a model to integrate the CSM. I've played around with it but
never got it working. Maybe it would be better to try and integrate with
UefiPayloadPkg?
On Mon, Aug 19, 2019, 4:14 PM Rafael Send
wrote:
> Right,
verified working here, thanks Gerd
On Tue, May 21, 2019 at 12:41 AM Gerd Hoffmann wrote:
> Check whenever pnp roms attempt to redirect int19, and in case it does
> log a message and undo the redirect.
>
> A pnp rom should not need this, we have BEVs and BCVs for that.
> Nevertheless there are
On Mon, May 20, 2019 at 4:49 PM Kevin O'Connor wrote:
> On Mon, May 20, 2019 at 04:43:08PM -0500, Matt DeVillier wrote:
> > v2 of the patch works as intended, once 'current.offset !=
> current.offset'
> > is corrected to 'current.offset != seabios.offset'
>
> FWIW
v2 of the patch works as intended, once 'current.offset != current.offset'
is corrected to 'current.offset != seabios.offset'
cheers,
Matt
On Tue, Dec 11, 2018 at 2:03 AM Gerd Hoffmann wrote:
> On Mon, Dec 10, 2018 at 09:53:01PM -0500, Kevin O'Connor wrote:
> > On Thu, Dec 06, 2018 at
reviving this, as I've run into this issue with some Intel 10Gbe NICs on a
board I've been testing (Intel Corporation Ethernet Connection X552 10 GbE
SFP+ [8086:15ac]). This patch resolves the issue for me
On Wed, Dec 5, 2018 at 4:49 PM Kevin O'Connor wrote:
> On Wed, Dec 05, 2018 at
Atom boards need hardware IRQs disabled. so in SeaBIOS config:
CONFIG_HARDWARE_IRQ=y
needs to be
# CONFIG_HARDWARE_IRQ is not set
not sure if there is an easy way to set this when building coreboot outside
of saving the entire .config and telling coreboot to use that
On Wed, Feb 27, 2019 at 9:44
On every Atom-based Intel platform I've built SeaBIOS for (Baytrail,
Braswell, Apollolake), I've always had to unset CONFIG_HARDWARE_IRQ, which
is set by default. I'd have to heck if any are calling setup_lapic() as
part of init, but I suspect not (at least not in their stock ChromeOS
firmware)
>From 3e41f058836cd920ab67463d361b11a11729b390 Mon Sep 17 00:00:00 2001
From: Matt DeVillier
Date: Tue, 11 Sep 2018 16:54:53 -0500
Subject: [PATCH v2 1/1] SeaVGABios/cbvga: Fix bpp for coreboot framebuffer
Commit 4b42cc4 [SeaVGABios/cbvga: Advertise correct pixel format] neglected
to w
>From 52191d4f83fe9e3fa47ec2f9ee98aec83304a8f6 Mon Sep 17 00:00:00 2001
From: Matt DeVillier
Date: Tue, 11 Sep 2018 16:54:53 -0500
Subject: [PATCH 1/1] SeaVGABios/cbvga: Fix bpp for coreboot framebuffer
Commit 4b42cc4 [SeaVGABios/cbvga: Advertise correct pixel format] neglected
to wrap the c
I think you're conflating a lot of different things here. I'm assuming you
are running a 3rd party firmware on your device which boots SeaBIOS as its
payload. Wifi/LAN not working are unlikely to be firmware related, so
flashing something else isn't going to help. The 'update microcode'
message
>From 2741d96d07855c3bc904d6ce47c82391039bca87 Mon Sep 17 00:00:00 2001
From: Matt DeVillier
Date: Tues, 21 Aug 2018 10:00:53 -0500
Subject: [PATCH v2 1/1] nvme: fix I/O queue length calculation overflow
Commit cd47172 changed the I/O queue length calculation to use the
Maximum Queue Entr
On Mon, Aug 20, 2018 at 11:16 PM Kevin O'Connor wrote:
> On Sun, Aug 12, 2018 at 03:42:40PM -0500, Matt DeVillier wrote:
> > Commit cd47172 changed the I/O queue length calculation to use the
> > Maximum Queue Entries Supported (MQES) value from the capabilities
> &g
>From a17975b5fe0cb2b17fdf0335430d5f4d2ab3ba4d Mon Sep 17 00:00:00 2001
From: Matt DeVillier
Date: Sun, 12 Aug 2018 15:26:59 -0500
Subject: [PATCH 1/1] nvme: fix I/O queue length calculation overflow
Commit cd47172 changed the I/O queue length calculation to use the
Maximum Queue Entr
On Sat, Oct 28, 2017 at 10:26 AM, Kevin O'Connor wrote:
> Okay. One more thing to try is a slightly different voltage range.
>
> -Kevin
>
>
> --- a/src/hw/sdcard.c
> +++ b/src/hw/sdcard.c
> @@ -123,6 +123,17 @@ struct sdhci_s {
> #define SRF_DATA 0x04
>
> // SDHCI result
On Fri, Oct 27, 2017 at 7:08 PM, Kevin O'Connor wrote:
> Can you try the two patches below? (Go back to master, apply the
> first, gather the log, go back to master, apply the second, gather the
> log.)
>
> -Kevin
>
w/patch 1 only: https://paste.ubuntu.com/25833503/
On Thu, Oct 26, 2017 at 11:26 AM, Kevin O'Connor <ke...@koconnor.net> wrote:
> On Thu, Oct 26, 2017 at 11:14:53AM -0400, Matt DeVillier wrote:
> > On Thu, Oct 26, 2017 at 10:59 AM, Kevin O'Connor <ke...@koconnor.net>
> wrote:
> >
> > with the patch, USB dev
On Thu, Oct 26, 2017 at 10:59 AM, Kevin O'Connor <ke...@koconnor.net> wrote:
> On Thu, Oct 26, 2017 at 10:46:06AM -0400, Matt DeVillier wrote:
> > On Thu, Oct 26, 2017 at 12:56 AM, Kevin O'Connor <ke...@koconnor.net>
> wrote:
> >
> > > Does t
On Thu, Oct 26, 2017 at 12:56 AM, Kevin O'Connor wrote:
> Does the patch below help?
>
> -Kevin
>
>
> --- a/src/hw/sdcard.c
> +++ b/src/hw/sdcard.c
> @@ -405,6 +405,7 @@ sdcard_card_setup(struct sddrive_s *drive, int volt,
> int prio)
> if (!ret && param[0] == vrange)
>
On Mon, Oct 23, 2017 at 12:04 PM, Kevin O'Connor <ke...@koconnor.net> wrote:
> On Mon, Oct 23, 2017 at 11:59:16AM -0500, Matt DeVillier wrote:
> > On Mon, Oct 23, 2017 at 11:34 AM, Kevin O'Connor <ke...@koconnor.net>
> wrote:
> > > On Mon, Oct 23, 2017 at 10:55
On Mon, Oct 23, 2017 at 11:34 AM, Kevin O'Connor <ke...@koconnor.net> wrote:
> On Mon, Oct 23, 2017 at 10:55:57AM -0500, Matt DeVillier wrote:
> > On Mon, Oct 23, 2017 at 10:50 AM, Kevin O'Connor <ke...@koconnor.net>
> wrote:
> >
> > > On Mon, Oct 23, 2
On Mon, Oct 23, 2017 at 10:50 AM, Kevin O'Connor wrote:
> On Mon, Oct 23, 2017 at 10:39:03AM -0400, Kevin O'Connor wrote:
> > Hi Matt,
> >
> > Can you gzip and attach the full log? (At a minimum, we need to see
> > the log extracts around the failure.)
>
> Ah, nevermind - I
no problem -- attached
On Mon, Oct 23, 2017 at 9:39 AM, Kevin O'Connor <ke...@koconnor.net> wrote:
> On Thu, Oct 19, 2017 at 09:16:13PM -0500, Matt DeVillier wrote:
> > I have a user running one of my SeaBIOS builds on a Asus Chromebook
> C302sa
> > (google/cave) who is
I have a user running one of my SeaBIOS builds on a Asus Chromebook C302sa
(google/cave) who is having trouble with high-capacity SD cards - they
aren't detected at all due to timing out during init. I've tried adjusting
the various timeouts, and the only change is longer log files.
The SD card
given what you're trying to do, I'd think it would be easier to modify
depthcharge to jump to RW_LEGACY later / after doing the other init
normally done when booting ChromeOS, than to try and shoehorn SeaBIOS into
something depthcharge would load like a kernel
On Tue, Oct 3, 2017 at 9:42 PM, Tang
what device are you targeting? John Lewis and I both offer firmware for
Intel-based ChromeOS devices that boots directly to either SeaBIOS (for
legacy boot) or Tianocore (for UEFI boot). If you just need SeaBIOS as a
RW_LEGACY payload which will be loaded by depthcharge, we offer that too.
See:
.
This eliminates the delay in displaying the boot menu message on Baytrail
ChromeOS devices, where multiple /etc/sdcard entries are present in a
single
payload to cover the range of eMMC controller addresses used.
Signed-off-by: Matt DeVillier <matt.devill...@gmail.com>
---
src/hw/sdcard.
sdhci controllers in order to avoid
duplicate entries in the boot menu.
patch implementation suggested by Kevin O'Connor :)
Signed-off-by: Matt DeVillier <matt.devill...@gmail.com>
---
src/hw/sdcard.c | 17 +++--
1 file changed, 11 insertions(+), 6 deletions(-)
diff --git a/
sdhci controllers in order to avoid duplicate entries in
the boot menu.
patch implementation suggested by Kevin O'Connor :)
Signed-off-by: Matt DeVillier <matt.devill...@gmail.com>
---
src/hw/sdcard.c | 17 +++--
1 file changed, 11 insertions(+), 6 deletions(-)
diff --git a/
On 3/10/2016 9:03 AM, Kevin O'Connor wrote:
On Thu, Mar 10, 2016 at 12:38:14AM -0600, Matt DeVillier wrote:
Some BayTrail ChromeOS devices have the eMMC controller hidden (thus
requiring the use of etc/sdcard), while others do not, making it problematic
to have a single payload which serves
sdhci controllers in order to avoid duplicate entries in
the boot menu.
patch implementation suggested by Kevin O'Connor :)
Signed-off-by: Matt DeVillier <matt.devill...@gmail.com>
---
src/hw/sdcard.c | 15 +--
1 file changed, 9 insertions(+), 6 deletions(-)
diff --git a/
FYI, the current testing branch (commit 977a7d4) has issues booting
Windows 10 via USB / Windows installer media on a Haswell ChromeBox
(XHCI only), locks up on the Windows logo. Tag 1.9.0 (commit 01a84be)
has no such issues. Will re-test with upstream master and report back
On 12/21/2015
On 12/21/2015 5:02 PM, Kevin O'Connor wrote:
On Mon, Dec 21, 2015 at 04:53:24PM -0600, Matt DeVillier wrote:
FYI, the current testing branch (commit 977a7d4) has issues booting Windows
10 via USB / Windows installer media on a Haswell ChromeBox (XHCI only),
locks up on the Windows logo. Tag
On 12/14/2015 6:02 PM, Kevin O'Connor wrote:
On Sun, Dec 13, 2015 at 09:16:02PM +, edward wandasiewicz wrote:
On Sun, Dec 13, 2015 at 9:05 PM, edward wandasiewicz <0.w3...@gmail.com> wrote:
When I do, I will post output.
When attempting a cold boot - shutdown - cold boot - shutdown -
coincidentally enough, my patch to correct the 'Booting from' text for
USB devices
(which I just updated) should address the issue you describe in the
documentation patch:
https://github.com/MattDevo/SeaBIOS/commit/424fa77d61e6c3b002ccbe00e6e641a4599b3d6a
it's probably not the ideal
On Thu, May 21, 2015 at 9:49 AM, Kevin O'Connor ke...@koconnor.net wrote:
On Wed, May 13, 2015 at 11:43:19AM -0500, Matt DeVillier wrote:
Greetings,
my Haswell ChromeBox users are still reporting intermittent issues
with USB device detection at boot on SeaBIOS 1.81, with both the
stock
On 3/25/2015 3:59 PM, Kevin O'Connor wrote:
There have been success reports with SeaBIOS booting Windows 8, so
it's not a general win8 problem.
for sure - no issues booting Win8/8.1/10TP on the Haswell ChromeOS devices
using SeaBIOS 1.8.0
If possible, try to pull the disk image into a QEMU
.
Suggested-by: Matt DeVillier matt.devill...@gmail.com
Signed-off-by: Paolo Bonzini pbonz...@redhat.com
---
src/boot.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/src/boot.c b/src/boot.c
index f23e9e1..3aab8d4 100644
--- a/src/boot.c
+++ b/src/boot.c
@@ -486,9
On 3/11/2015 2:45 PM, Kevin O'Connor wrote:
On Wed, Mar 11, 2015 at 06:39:44PM +0100, Paolo Bonzini wrote:
On 11/03/2015 18:24, Kevin O'Connor wrote:
On Wed, Mar 11, 2015 at 05:42:18PM +0100, Paolo Bonzini wrote:
I have no problem with changing the key; the problem I have with ESC is
that I'm
no regressions using your testing branch on panther, with a variety of
USB2/USB3 flash devices connected to an xHCI controller.
On 9/10/2014 1:45 PM, Kevin O'Connor wrote:
This series reworks the timing of USB detection. Previously, the USB
controllers would wait for the port power to
+1 on both patches (or the two together at least)
On 9/9/2014 6:35 PM, Kevin O'Connor wrote:
Make sure to call usb_desc2pipe() when updating a pipe settings. This
ensures that pipe-devaddr is properly updated.
Signed-off-by: Kevin O'Connor ke...@koconnor.net
---
src/hw/usb-xhci.c | 37
On 6/24/2014 8:20 PM, Kevin O'Connor wrote:
On Tue, Jun 24, 2014 at 11:48:21AM -0500, Matt DeVillier wrote:
Here's how I did it - this will skip the 'Press XXX for boot menu.' as well,
so that there is no delay in booting, and no confusion on the user's part as
to why the boot menu key
Here's how I did it - this will skip the 'Press XXX for boot menu.' as well, so
that there is no delay in booting, and no confusion on the user's part as to
why the boot menu key isn't working :)
requires the file /etc/boot-auto to exist in the CBFS.
diff --git a/src/boot.c b/src/boot.c
index
On 6/22/2014 5:04 AM, Kevin O'Connor wrote:
On Sat, Jun 21, 2014 at 01:24:24PM -0500, Matt DeVillier wrote:
On 6/21/2014 1:22 PM, Kevin O'Connor wrote:
The above is fine. Can you also post 'lsusb -t' and 'lsusb -v' output
for the device? I'll take a look later tonight.
does it need
On 6/21/2014 1:08 PM, Kevin O'Connor wrote:
On Sat, Jun 21, 2014 at 12:20:21PM -0500, Matt DeVillier wrote:
Kevin,
I still have issues with various USB sticks not being detected at
boot due to the xhci_event_wait() call in xhci_cmd_submit() which
still has a timeout of 1000ms (vs 5000
Kevin,
I still have issues with various USB sticks not being detected at boot due to
the xhci_event_wait() call in xhci_cmd_submit() which still has a timeout of
1000ms (vs 5000 for the ones affected by this patch). Manually setting it to
5000 fixes the issues with all the USB flash devices
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