For a PCI serial port, we have to discover its location. Potentially on every entry, since UEFI may shift it at some point during the boot process from an early debug setup to a final location after real PCI enumeration.
Signed-off-by: David Woodhouse <david.woodho...@intel.com>
---
src/fw/csm.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/fw/csm.c b/src/fw/csm.c
index 4e4b688..39634cd 100644
--- a/src/fw/csm.c
+++ b/src/fw/csm.c
@@ -109,6 +109,8 @@ handle_csm_0001(struct bregs *regs)
return;
}
+ debug_preinit();
+
dprintf(3, "Legacy16UpdateBbs table %04x:%04x\n", regs->es, regs->bx);
csm_boot_table = MAKE_FLATPTR(regs->es, regs->bx);
--
1.8.3.1
--
David Woodhouse Open Source Technology Centre
david.woodho...@intel.com Intel Corporation
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