[SeaBIOS] [PATCH 0/4] Use 'struct pci_device' to limit option rom execution.

[Kevin O'Connor]

This patch series extends the proliferation of 'struct pci_device'
which was introduced in the last patch series.

The objective of this series is to ensure that ATA devices configured
to use the native ATA driver don't attempt to run an option rom on the
device.  This can become complex when a device that isn't identified
as a PCI_CLASS_STORAGE_IDE uses the native ATA driver.  So, a bit in
the 'struct pci_device' now notes when a native driver is in use and
the option rom code checks for it.

Gerd - this patch series (and the previous one) may conflict with your
work.


Kevin O'Connor (4):
  Use manual PCI search when making bios ram writable.
  Move pci_probe() call into pciinit() code.
  Convert pci_init_device to use 'struct pci_device'.
  Use 'struct pci_device' to note which devices have native drivers.

 src/acpi.c   |   16 ++--
 src/ata.c|   14 ++
 src/optionroms.c |4 +--
 src/pci.c|   33 +++---
 src/pci.h|   11 ++--
 src/pciinit.c|   69 --
 src/post.c   |1 -
 src/shadow.c |   41 ++--
 src/smm.c|6 ++--
 9 files changed, 101 insertions(+), 94 deletions(-)

-- 
1.7.4.4


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[SeaBIOS] [PATCH 1/4] Use manual PCI search when making bios ram writable.

[Kevin O'Connor]

During the ram unlock phase static variables can't be written, so
don't rely on the higher level PCI searching functions.  This will
allow for future simplification of those high level search functions.

This also limits the scan for the memory locking device to the first
bus - the device should also be on the root bus.
---
 src/shadow.c |   31 +--
 1 files changed, 13 insertions(+), 18 deletions(-)

diff --git a/src/shadow.c b/src/shadow.c
index 169decf..68c9230 100644
--- a/src/shadow.c
+++ b/src/shadow.c
@@ -9,6 +9,7 @@
 #include pci.h // pci_config_writeb
 #include config.h // CONFIG_*
 #include pci_ids.h // PCI_VENDOR_ID_INTEL
+#include pci_regs.h // PCI_VENDOR_ID
 #include xen.h // usingXen
 
 // On the emulators, the bios at 0xf is also at 0x
@@ -94,22 +95,11 @@ make_bios_readonly_intel(u16 bdf, u32 pam0)
 pci_config_writeb(bdf, pam0, 0x10);
 }
 
-static void i440fx_bios_make_writable(u16 bdf, void *arg)
-{
-make_bios_writable_intel(bdf, I440FX_PAM0);
-}
-
 static void i440fx_bios_make_readonly(u16 bdf, void *arg)
 {
 make_bios_readonly_intel(bdf, I440FX_PAM0);
 }
 
-static const struct pci_device_id dram_controller_make_writable_tbl[] = {
-PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441,
-   i440fx_bios_make_writable),
-PCI_DEVICE_END
-};
-
 static const struct pci_device_id dram_controller_make_readonly_tbl[] = {
 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441,
i440fx_bios_make_readonly),
@@ -125,14 +115,19 @@ make_bios_writable(void)
 
 dprintf(3, enabling shadow ram\n);
 
-// at this point, statically allocated variables can't be written.
-// so stack should be used.
-
-// Locate chip controlling ram shadowing.
-int bdf = pci_find_init_device(dram_controller_make_writable_tbl, NULL);
-if (bdf  0) {
-dprintf(1, Unable to unlock ram - bridge not found\n);
+// At this point, statically allocated variables can't be written,
+// so do this search manually.
+int bdf, max;
+foreachbdf_in_bus(bdf, max, 0) {
+u32 vendev = pci_config_readl(bdf, PCI_VENDOR_ID);
+u16 vendor = vendev  0x, device = vendev  16;
+if (vendor == PCI_VENDOR_ID_INTEL
+ device == PCI_DEVICE_ID_INTEL_82441) {
+make_bios_writable_intel(bdf, I440FX_PAM0);
+return;
+}
 }
+dprintf(1, Unable to unlock ram - bridge not found\n);
 }
 
 // Make the BIOS code segment area (0xf) read-only.
-- 
1.7.4.4


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[SeaBIOS] [PATCH 3/4] Convert pci_init_device to use 'struct pci_device'.

[Kevin O'Connor]

---
 src/acpi.c|   16 +++---
 src/ata.c |   13 ++-
 src/pci.c |   33 +-
 src/pci.h |8 --
 src/pciinit.c |   61 
 src/shadow.c  |   10 
 src/smm.c |6 ++--
 7 files changed, 77 insertions(+), 70 deletions(-)

diff --git a/src/acpi.c b/src/acpi.c
index 584e557..fc7867a 100644
--- a/src/acpi.c
+++ b/src/acpi.c
@@ -217,7 +217,7 @@ build_header(struct acpi_table_header *h, u32 sig, int len, 
u8 rev)
 #define PIIX4_GPE0_BLK  0xafe0
 #define PIIX4_GPE0_BLK_LEN  4
 
-static void piix4_fadt_init(u16 bdf, void *arg)
+static void piix4_fadt_init(struct pci_device *pci, void *arg)
 {
 struct fadt_descriptor_rev1 *fadt = arg;
 fadt-acpi_enable = PIIX4_ACPI_ENABLE;
@@ -234,8 +234,8 @@ static const struct pci_device_id fadt_init_tbl[] = {
 PCI_DEVICE_END
 };
 
-static void*
-build_fadt(int bdf)
+static void *
+build_fadt(struct pci_device *pci)
 {
 struct fadt_descriptor_rev1 *fadt = malloc_high(sizeof(*fadt));
 struct facs_descriptor_rev1 *facs = memalign_high(64, sizeof(*facs));
@@ -260,7 +260,7 @@ build_fadt(int bdf)
 fadt-dsdt = cpu_to_le32((u32)dsdt);
 fadt-model = 1;
 fadt-reserved1 = 0;
-int pm_sci_int = pci_config_readb(bdf, PCI_INTERRUPT_LINE);
+int pm_sci_int = pci_config_readb(pci-bdf, PCI_INTERRUPT_LINE);
 fadt-sci_int = cpu_to_le16(pm_sci_int);
 fadt-smi_cmd = cpu_to_le32(PORT_SMI_CMD);
 fadt-pm1a_evt_blk = cpu_to_le32(PORT_ACPI_PM_BASE);
@@ -271,7 +271,7 @@ build_fadt(int bdf)
 fadt-pm_tmr_len = 4;
 fadt-plvl2_lat = cpu_to_le16(0xfff); // C2 state not supported
 fadt-plvl3_lat = cpu_to_le16(0xfff); // C3 state not supported
-pci_init_device(fadt_init_tbl, bdf, fadt);
+pci_init_device(fadt_init_tbl, pci, fadt);
 /* WBINVD + PROC_C1 + SLP_BUTTON + FIX_RTC + RTC_S4 */
 fadt-flags = cpu_to_le32((1  0) | (1  2) | (1  5) | (1  6) | (1 
 7));
 
@@ -611,8 +611,8 @@ acpi_bios_init(void)
 dprintf(3, init ACPI tables\n);
 
 // This code is hardcoded for PIIX4 Power Management device.
-int bdf = pci_find_init_device(acpi_find_tbl, NULL);
-if (bdf  0)
+struct pci_device *pci = pci_find_init_device(acpi_find_tbl, NULL);
+if (!pci)
 // Device not found
 return;
 
@@ -633,7 +633,7 @@ acpi_bios_init(void)
 } while(0)
 
 // Add tables
-ACPI_INIT_TABLE(build_fadt(bdf));
+ACPI_INIT_TABLE(build_fadt(pci));
 ACPI_INIT_TABLE(build_ssdt());
 ACPI_INIT_TABLE(build_madt());
 ACPI_INIT_TABLE(build_hpet());
diff --git a/src/ata.c b/src/ata.c
index e07aabe..a6b5067 100644
--- a/src/ata.c
+++ b/src/ata.c
@@ -965,8 +965,9 @@ init_controller(int bdf, int irq, u32 port1, u32 port2, u32 
master)
 
 // Handle controllers on an ATA PCI device.
 static void
-init_pciata(u16 bdf, u8 prog_if)
+init_pciata(struct pci_device *pci, u8 prog_if)
 {
+u16 bdf = pci-bdf;
 u8 pciirq = pci_config_readb(bdf, PCI_INTERRUPT_LINE);
 int master = 0;
 if (CONFIG_ATA_DMA  prog_if  0x80) {
@@ -1007,18 +1008,18 @@ init_pciata(u16 bdf, u8 prog_if)
 }
 
 static void
-found_genericata(u16 bdf, void *arg)
+found_genericata(struct pci_device *pci, void *arg)
 {
-init_pciata(bdf, pci_config_readb(bdf, PCI_CLASS_PROG));
+init_pciata(pci, pci-prog_if);
 }
 
 static void
-found_compatibleahci(u16 bdf, void *arg)
+found_compatibleahci(struct pci_device *pci, void *arg)
 {
 if (CONFIG_AHCI)
 // Already handled directly via native ahci interface.
 return;
-init_pciata(bdf, 0x8f);
+init_pciata(pci, 0x8f);
 }
 
 static const struct pci_device_id pci_ata_tbl[] = {
@@ -1045,7 +1046,7 @@ ata_init(void)
 // Scan PCI bus for ATA adapters
 struct pci_device *pci;
 foreachpci(pci) {
-pci_init_device(pci_ata_tbl, pci-bdf, NULL);
+pci_init_device(pci_ata_tbl, pci, NULL);
 }
 }
 
diff --git a/src/pci.c b/src/pci.c
index eaf434a..78bbac2 100644
--- a/src/pci.c
+++ b/src/pci.c
@@ -190,19 +190,15 @@ pci_find_class(u16 classid)
 return -1;
 }
 
-int pci_init_device(const struct pci_device_id *ids, u16 bdf, void *arg)
+int pci_init_device(const struct pci_device_id *ids
+, struct pci_device *pci, void *arg)
 {
-u16 vendor_id = pci_config_readw(bdf, PCI_VENDOR_ID);
-u16 device_id = pci_config_readw(bdf, PCI_DEVICE_ID);
-u16 class = pci_config_readw(bdf, PCI_CLASS_DEVICE);
-
 while (ids-vendid || ids-class_mask) {
-if ((ids-vendid == PCI_ANY_ID || ids-vendid == vendor_id) 
-(ids-devid == PCI_ANY_ID || ids-devid == device_id) 
-!((ids-class ^ class)  ids-class_mask)) {
-if (ids-func) {
-ids-func(bdf, arg);
-}
+if ((ids-vendid == PCI_ANY_ID || ids-vendid == pci-vendor) 
+(ids-devid == PCI_ANY_ID || ids-devid == pci-device) 
+!((ids-class ^ pci-class)  ids-class_mask)) {
+