Re: [SeaBIOS] [PATCH RFC] x86: use volatile asm for read/write{b, w, l} implementations

2018-01-04 Thread Laszlo Ersek
On 01/04/18 15:29, Vitaly Kuznetsov wrote: > Laszlo Ersek writes: > In fact, the only writew() needs patching is in vp_notify(), when I > replace it with 'asm volatile' everything works. > >> * Does it make a difference if you disable EPT in the L1 KVM >> configuration? (EPT is probably primaril

Re: [SeaBIOS] [PATCH RFC] x86: use volatile asm for read/write{b, w, l} implementations

2018-01-04 Thread Vitaly Kuznetsov
Laszlo Ersek writes: > On 01/04/18 11:24, Vitaly Kuznetsov wrote: >> Laszlo Ersek writes: >> >>> Is it possible that the current barrier() is not sufficient for the >>> intended purpose in an L2 guest? >>> >>> What happens if you drop your current patch, but replace >>> >>> __asm__ __volatile

Re: [SeaBIOS] [PATCH RFC] x86: use volatile asm for read/write{b, w, l} implementations

2018-01-04 Thread Laszlo Ersek
On 01/04/18 11:24, Vitaly Kuznetsov wrote: > Laszlo Ersek writes: > >> Is it possible that the current barrier() is not sufficient for the >> intended purpose in an L2 guest? >> >> What happens if you drop your current patch, but replace >> >> __asm__ __volatile__("": : :"memory") >> >> in the

Re: [SeaBIOS] [PATCH RFC] x86: use volatile asm for read/write{b, w, l} implementations

2018-01-04 Thread Vitaly Kuznetsov
Laszlo Ersek writes: > Is it possible that the current barrier() is not sufficient for the > intended purpose in an L2 guest? > > What happens if you drop your current patch, but replace > > __asm__ __volatile__("": : :"memory") > > in the barrier() macro definition, with a real, heavy-weight b