[SeaBIOS] Re: [PATCH v4 5/6] qemu: log reservations in fw_cfg e820 table

On 24/8/23 10:57, Gerd Hoffmann wrote: With loglevel 1 (same we use for RAM entries), so it is included in the firmware log by default. Signed-off-by: Gerd Hoffmann --- src/fw/paravirt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) Reviewed-by: Philippe Mathieu-Daudé

[SeaBIOS] [PATCH v4 6/6] check for e820 conflict

Add support to check for overlaps with e820 entries. In case the 64bit pci io window has conflicts move it down. The only known case where this happens is AMD processors with 1TB address space which has some space just below 1TB reserved for HT. Signed-off-by: Gerd Hoffmann --- src/e820map.h

[SeaBIOS] [PATCH v4 5/6] qemu: log reservations in fw_cfg e820 table

With loglevel 1 (same we use for RAM entries), so it is included in the firmware log by default. Signed-off-by: Gerd Hoffmann --- src/fw/paravirt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/fw/paravirt.c b/src/fw/paravirt.c index 3aee4c0d4e6b..e5d4eca0cb5a 100644

[SeaBIOS] [PATCH v4 4/6] be less conservative with the 64bit pci io window

Current seabios code will only enable and use the 64bit pci io window in case it runs out of space in the 32bit pci mmio window below 4G. This patch will also enable the 64bit pci io window when (a) RAM above 4G is present, and (b) the physical address space size is known, and (c) seabios

[SeaBIOS] [PATCH v4 2/6] detect physical address space size

Check for pae and long mode using cpuid. If present also read the physical address bits. Apply some qemu sanity checks (see below). Record results in PhysBits and LongMode variables. In case we are not sure what the address space size is leave the PhysBits variable unset. On qemu we have the

[SeaBIOS] [PATCH v4 3/6] move 64bit pci window to end of address space

When the size of the physical address space is known (PhysBits is not zero) move the 64bit pci io window to the end of the address space. Signed-off-by: Gerd Hoffmann --- src/fw/pciinit.c | 8 1 file changed, 8 insertions(+) diff --git a/src/fw/pciinit.c b/src/fw/pciinit.c index

[SeaBIOS] [PATCH v4 0/6] misc tweaks for kvm and the 64bit pci window

v4 changes: - fix handling of 32bit memory bars. v3 changes: - rename variables, use u8 for CPULongMode. v2 changes: - e820 conflict fix Gerd Hoffmann (6): better kvm detection detect physical address space size move 64bit pci window to end of address space be less conservative with

[SeaBIOS] [PATCH v4 1/6] better kvm detection

In case kvm emulates features of another hypervisor (for example hyperv) two VMM CPUID blocks will be present, one for the emulated hypervisor and one for kvm itself. This patch makes seabios loop over the VMM CPUID blocks to make sure it will properly detect kvm when multiple blocks are present.

[SeaBIOS] Re: new release tag?

On Mon, Aug 07, 2023 at 10:51:33AM +, Niklas Cassel via SeaBIOS wrote: > Hello Seabios maintainers, > > > I was wondering, is there any chance of getting a new release tag > (e.g. rel-1.16.3) anytime soon? > Or is there any plan on when it will be tagged? > > I'm waiting to send out a (AHCI

[SeaBIOS] Re: [PATCH v3 0/3] esp-scsi: fix reliance on QEMU ESP SCSI implementation bugs

On Mon, Aug 07, 2023 at 07:52:57AM +0100, Mark Cave-Ayland wrote: > Whilst trying to improve QEMU's ESP SCSI implementation with regard to the > NCR datasheet, I noticed that SeaBIOS would fail to boot one of my Debian > test images with my patches applied. > > Further investigation revealed that

[SeaBIOS] Re: [Increase BUILD_MAX_E820 to 128] Increase BUILD_MAX_E820 to 128

On Fri, Jul 28, 2023 at 04:41:48AM +, Tony Titus via SeaBIOS wrote: > For platforms with high number of numa nodes, 32 e820 entries are not > enough. Linux kernel sets the maximum e820 entries to a base value of > 128. Setting BUILD_MAX_E820 to 128 to be in sync with this base value. > >