On 02/16/2015 12:07 PM, Igor Mammedov wrote:
On Mon, 16 Feb 2015 11:54:04 +0200
Marcel Apfelbaum mar...@redhat.com wrote:
Save the IO/mem/bus numbers ranges assigned to the extra root busses
to be removed from the root bus 0 range.
Hi Igor,
Thanks for the review.
Is it possible to make BIOS
From: Marcel Apfelbaum marce...@redhat.com
Instead of assuming it has only one bus, it
enumerates all the host bridges until it finds
the one with bus number corresponding with the
config register.
Signed-off-by: Marcel Apfelbaum mar...@redhat.com
---
hw/pci-host/piix.c | 57
From: Marcel Apfelbaum marce...@redhat.com
The bios looks for 'etc/extra-pci-roots' to decide if
is going to scan further buses after bus 0 tree.
Signed-off-by: Marcel Apfelbaum mar...@redhat.com
---
hw/i386/pc.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/hw/i386/pc.c b
The bios does not index the pxb slot number when
it computes the IRQ because it resides on bus 0
and not on the current bus.
However Qemu routes the irq through bus 0 and adds
the pxb slot to the IRQ computation.
Synchronize between bios and Qemu by canceling
pxb's effect.
Signed-off-by: Marcel
PCI root buses can be attached to a specific NUMA node.
PCI buses are not attached be default to a NUMA node.
Signed-off-by: Marcel Apfelbaum mar...@redhat.com
---
hw/pci/pci_bus.c | 7 +++
include/hw/pci/pci_bus.h | 6 ++
include/sysemu/sysemu.h | 1 +
3 files changed, 14
The pxb can be attach to and existing numa node by specifying
numa_node option that equals the desired numa nodeid.
Signed-off-by: Marcel Apfelbaum mar...@redhat.com
---
hw/i386/acpi-build.c| 12
hw/pci-bridge/pci_expander_bridge.c | 17 +
2 files
Signed-off-by: Marcel Apfelbaum mar...@redhat.com
---
hw/i386/acpi-build.c | 77
1 file changed, 77 insertions(+)
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index fedcb2e..ee1a50a 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386
From: Marcel Apfelbaum marce...@redhat.com
PXB is a light-weight host bridge whose purpose is to enable
the main host bridge to support multiple PCI root buses.
As oposed to PCI-2-PCI bridge's secondary bus, PXB's bus
is a primary bus and can be associated with a NUMA node
(different from
From: Marcel Apfelbaum marce...@redhat.com
Signed-off-by: Marcel Apfelbaum mar...@redhat.com
---
hw/pci/pci.c | 8
include/hw/pci/pci_host.h | 4
2 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
index bf31168..d0d0035 100644
From: Marcel Apfelbaum marce...@redhat.com
Refactoring it as a method of PCIBusClass will allow
different implementations for subclasses.
Signed-off-by: Marcel Apfelbaum mar...@redhat.com
---
hw/i386/kvm/pci-assign.c | 1 +
hw/pci/pci-hotplug-old.c | 1 +
hw/pci/pci.c | 7
Signed-off-by: Marcel Apfelbaum mar...@redhat.com
---
hw/acpi/acpi-build-utils.c | 107 +++--
include/hw/acpi/acpi-build-utils.h | 12 +
2 files changed, 116 insertions(+), 3 deletions(-)
diff --git a/hw/acpi/acpi-build-utils.c b/hw/acpi/acpi-build
Save the IO/mem/bus numbers ranges assigned to the extra root busses
to be removed from the root bus 0 range.
Signed-off-by: Marcel Apfelbaum mar...@redhat.com
---
hw/i386/acpi-build.c | 146 +++
1 file changed, 146 insertions(+)
diff --git a/hw
the device
patch 15 implements PXB map_irq function, (can be squashed into the actual PXB)
patch 16-17 adds NUMA support
Marcel Apfelbaum (17):
acpi: added needed acpi constructs
hw/acpi: add support for multiple root busses
hw/apci: add _PRT method for extra root busses
hw/acpi: add _CRS
If the machine has several root busses, we need to add them to
acpi in order to be properly detected by guests.
Signed-off-by: Marcel Apfelbaum mar...@redhat.com
---
hw/i386/acpi-build.c | 32
1 file changed, 32 insertions(+)
diff --git a/hw/i386/acpi-build.c b
From: Marcel Apfelbaum marce...@redhat.com
This is a marker interface used to differentiate the
default host bridge on a system with multiple host bridges.
This differentiation is required only for pc machines for now
by the ACPI subsystem.
Signed-off-by: Marcel Apfelbaum mar...@redhat.com
On 02/16/2015 11:54 AM, Marcel Apfelbaum wrote:
Save the IO/mem/bus numbers ranges assigned to the extra root busses
to be removed from the root bus 0 range.
Signed-off-by: Marcel Apfelbaum mar...@redhat.com
---
hw/i386/acpi-build.c | 146
From: Marcel Apfelbaum marce...@redhat.com
This refactoring moves all the code needed (recursively)
to register TYPE_PCI_BUS type to a new file hw/pci/pci_bus.c .
This allows to properly add new functionality to the pci bus class.
Signed-off-by: Marcel Apfelbaum mar...@redhat.com
From: Marcel Apfelbaum marce...@redhat.com
The bios looks for 'etc/extra-pci-roots' to decide if
is going to scan further buses after bus 0 tree.
Signed-off-by: Marcel Apfelbaum mar...@redhat.com
---
hw/i386/pc.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/hw/i386/pc.c b
From: Marcel Apfelbaum marce...@redhat.com
Signed-off-by: Marcel Apfelbaum mar...@redhat.com
---
hw/pci/pci.c | 8
include/hw/pci/pci_host.h | 4
2 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
index bf31168..d0d0035 100644
node (acpi proximity)
- Think of migration implications and missing code (Ideas?)
Any comments will be welcomed and appreciated.
I will not be able to respond next week, but after that
I'll answer to all questions/comments.
Thanks,
Marcel
Marcel Apfelbaum (17):
acpi: added needed acpi
If the machine has several root busses, we need to add them to
acpi in order to be properly detected by guests.
Signed-off-by: Marcel Apfelbaum mar...@redhat.com
---
hw/i386/acpi-build.c | 30 ++
1 file changed, 30 insertions(+)
diff --git a/hw/i386/acpi-build.c b/hw
Save the IO/mem ranges assigned to the extra root busses
to be removed from the root bus 0 range.
Todo: find the actual bus numbers range for the root busses.
Signed-off-by: Marcel Apfelbaum mar...@redhat.com
---
hw/i386/acpi-build.c | 110 +++
1
Signed-off-by: Marcel Apfelbaum mar...@redhat.com
---
hw/acpi/acpi-build-utils.c | 107 +++--
include/hw/acpi/acpi-build-utils.h | 12 +
2 files changed, 116 insertions(+), 3 deletions(-)
diff --git a/hw/acpi/acpi-build-utils.c b/hw/acpi/acpi-build
The bios does not index the pxb slot number when
it computes the IRQ because it resides on bus 0
and not on the current bus.
However Qemu routes the irq through bus 0 and adds
the pxb slot to the IRQ computation.
Synchronize between bios and Qemu by canceling
pxb's effect.
Signed-off-by: Marcel
Signed-off-by: Marcel Apfelbaum mar...@redhat.com
---
hw/i386/acpi-build.c | 77
1 file changed, 77 insertions(+)
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 9837120..cb77fa3 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386
From: Marcel Apfelbaum marce...@redhat.com
This is a marker interface used to differentiate the
default host bridge on a system with multiple host bridges.
This differentiation is required only for pc machines for now
by the ACPI subsystem.
Signed-off-by: Marcel Apfelbaum mar...@redhat.com
If multiple root busses are used, root bus 0 cannot use all the
pci holes ranges. Remove the IO/mem ranges used by the other
primary busses.
todo: properly compute the bus ranges for root bus 0.
Signed-off-by: Marcel Apfelbaum mar...@redhat.com
---
hw/i386/acpi-build.c | 74
From: Marcel Apfelbaum marce...@redhat.com
Use the newer pci_bus_num to correctly get the root bus number.
Signed-off-by: Marcel Apfelbaum mar...@redhat.com
---
hw/pci/pci.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
index dccb3d1..bf31168
From: Marcel Apfelbaum marce...@redhat.com
PXB is a light-weight host bridge whose purpose is to enable
the main host bridge to support multiple PCI root buses.
As oposed to PCI-2-PCI bridge's secondary bus, PXB's bus
is a primary bus and can be associated with a NUMA node
(different from
Windows disables the pci-bridge if shpc bar has a memory conflict.
Until this problem is solved, this hack can be used for tests.
Signed-off-by: Marcel Apfelbaum mar...@redhat.com
---
hw/pci-bridge/pci_bridge_dev.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/pci-bridge
From: Marcel Apfelbaum marce...@redhat.com
Refactoring it as a method of PCIBusClass will allow
different implementations for subclasses.
Removed the assumption that the root bus does not
have a parent device because is specific only
to the default class implementation.
Signed-off-by: Marcel
From: Marcel Apfelbaum marce...@redhat.com
Instead of assuming it has only one bus, it
enumerates all the host bridges until it finds
the one with bus number corresponding with the
config register.
Signed-off-by: Marcel Apfelbaum mar...@redhat.com
---
hw/pci-host/piix.c | 57
From: Marcel Apfelbaum marce...@redhat.com
Refactoring it as a method of PCIBusClass will allow
different implementations for subclasses.
Signed-off-by: Marcel Apfelbaum mar...@redhat.com
---
hw/i386/kvm/pci-assign.c | 1 +
hw/pci/pci-hotplug-old.c | 1 +
hw/pci/pci.c | 7
On Mon, 2014-11-24 at 13:28 +0100, Gerd Hoffmann wrote:
On Mo, 2014-11-24 at 11:47 +0200, Marcel Apfelbaum wrote:
Removed the assumption that the system has only one primary root bus.
When mapping memory and IO regions go over all buses, skipping
secondary and absent buses.
Hi Gerd
On Mon, 2014-11-24 at 15:28 +0100, Gerd Hoffmann wrote:
On Mo, 2014-11-24 at 15:38 +0200, Marcel Apfelbaum wrote:
On Mon, 2014-11-24 at 13:28 +0100, Gerd Hoffmann wrote:
On Mo, 2014-11-24 at 11:47 +0200, Marcel Apfelbaum wrote:
Removed the assumption that the system has only one primary
On Mon, 2014-11-24 at 13:01 -0500, Kevin O'Connor wrote:
On Mon, Nov 24, 2014 at 12:21:31PM -0500, Kevin O'Connor wrote:
On Mon, Nov 24, 2014 at 03:28:52PM +0100, Gerd Hoffmann wrote:
I think I would try to reuse the existing code which does the same for
bridges. Reuse struct pci_bus to
On Mon, 2014-11-24 at 15:18 -0500, Kevin O'Connor wrote:
On Mon, Nov 24, 2014 at 09:38:38PM +0200, Marcel Apfelbaum wrote:
On Mon, 2014-11-24 at 13:01 -0500, Kevin O'Connor wrote:
On Mon, Nov 24, 2014 at 12:21:31PM -0500, Kevin O'Connor wrote:
On Mon, Nov 24, 2014 at 03:28:52PM +0100
Commit c6e298e1f12e0f4ca02b6da5e42919ae055f6830
hw/pci: reserve IO and mem for pci-2-pci bridges with no devices attached
introduced support for hot-plugging devices behind pci-2-pci bridges.
Extend hotplug support also for pci express downstream ports.
Signed-off-by: Marcel Apfelbaum marce
On Thu, 2014-06-19 at 17:21 +0300, Michael S. Tsirkin wrote:
On Thu, Jun 19, 2014 at 04:52:17PM +0300, Marcel Apfelbaum wrote:
commit c6e298e1f12e0f4ca02b6da5e42919ae055f6830
hw/pci: reserve IO and mem for pci-2-pci bridges with no devices
attached
introduced support for hot
commit c6e298e1f12e0f4ca02b6da5e42919ae055f6830
hw/pci: reserve IO and mem for pci-2-pci bridges with no devices attached
introduced support for hot-plugging devices behind pci-2-pci bridges.
Extend hotplug support also for pci express downstream ports.
Signed-off-by: Marcel Apfelbaum marce
commit c6e298e1f12e0f4ca02b6da5e42919ae055f6830
hw/pci: reserve IO and mem for pci-2-pci bridges with no devices attached
introduced support for hot-plugging devices behind pci-2-pci bridges.
Extend hotplug support also for pci express downstream ports.
Signed-off-by: Marcel Apfelbaum marce
If a pci-2-pci bridge supports hot-plug functionality but there are no devices
connected to it, reserve IO/mem in order to be able to attach devices
later. Do not waste space, use minimum allowed.
Signed-off-by: Marcel Apfelbaum marce...@redhat.com
---
src/fw/pciinit.c | 3 +++
src/hw/pci.c
I/O Base Register, I/O Limit Register pair and
Prefetchable Memory Base Register, Prefetchable Memory Limit Register pair
are both optional.
Do not reserve ranges if the above registers are not implemented.
Signed-off-by: Marcel Apfelbaum marce...@redhat.com
---
src/fw/pciinit.c | 9
in order to be able to attach devices
later. Do not waste space, use minimum allowed.
Marcel Apfelbaum (2):
hw/pci: reserve IO and mem for pci-2-pci bridges with no devices
attached
hw/pci: check if pci2pci bridges implement optional limit registers
src/fw/pciinit.c | 12 +-
src/hw
On Thu, 2014-04-10 at 18:46 +0300, Michael S. Tsirkin wrote:
On Thu, Apr 10, 2014 at 04:29:41PM +0300, Marcel Apfelbaum wrote:
I/O Base Register, I/O Limit Register pair and
Prefetchable Memory Base Register, Prefetchable Memory Limit Register pair
are both optional.
Do not reserve ranges
On Thu, 2014-04-10 at 12:45 -0400, Kevin O'Connor wrote:
On Thu, Apr 10, 2014 at 04:29:40PM +0300, Marcel Apfelbaum wrote:
[...]
+for (i = 0, cap = pci_config_readb(pci-bdf, PCI_CAPABILITY_LIST);
+ (i = 0xff) cap;
+ i++, cap = pci_config_readb(pci-bdf, cap
to 256 iterations, to make sure we
don't get into an infinite loop with a broken device.
If a pci-2-pci bridge supports hot-plug functionality but there are no devices
connected to it, reserve IO/mem in order to be able to attach devices
later. Do not waste space, use minimum allowed.
Marcel
If a pci-2-pci bridge supports hot-plug functionality but there are no devices
connected to it, reserve IO/mem in order to be able to attach devices
later. Do not waste space, use minimum allowed.
Reviewed-by: Michael S. Tsirkin m...@redhat.com
Signed-off-by: Marcel Apfelbaum marce...@redhat.com
I/O Base Register, I/O Limit Register pair and
Prefetchable Memory Base Register, Prefetchable Memory Limit Register pair
are both optional.
Do not reserve ranges if the above registers are not implemented.
Signed-off-by: Marcel Apfelbaum marce...@redhat.com
---
src/fw/pciinit.c | 9
to it, reserve IO/mem in order to be able to attach devices
later. Do not waste space, use minimum allowed.
Marcel Apfelbaum (2):
hw/pci: reserve IO and mem for pci-2-pci bridges with no devices
attached
hw/pci: check if pci2pci bridges implement optional limit registers
src/fw/pciinit.c | 12
If a pci-2-pci bridge supports hot-plug functionality but there are no devices
connected to it, reserve IO/mem in order to be able to attach devices
later. Do not waste space, use minimum allowed.
Reviewed-by: Michael S. Tsirkin m...@redhat.com
Signed-off-by: Marcel Apfelbaum marce...@redhat.com
I/O Base Register, I/O Limit Register pair and
Prefetchable Memory Base Register, Prefetchable Memory Limit Register pair
are both optional.
Do not reserve ranges if the above registers are not implemented.
Signed-off-by: Marcel Apfelbaum marce...@redhat.com
---
src/fw/pciinit.c | 9
functionality but there are no devices
connected to it, reserve IO/mem in order to be able to attach devices
later. Do not waste space, use minimum allowed.
Marcel Apfelbaum (2):
hw/pci: reserve IO and mem for pci-2-pci bridges with no devices
attached
hw/pci: check if pci2pci bridges implement
I/O Base Register, I/O Limit Register pair and
Prefetchable Memory Base Register, Prefetchable Memory Limit Register pair
are both optional.
Do not reserve ranges if the above registers are not implemented.
Signed-off-by: Marcel Apfelbaum marce...@redhat.com
---
src/fw/pciinit.c | 9
If a pci-2-pci bridge supports hot-plug functionality but there are no devices
connected to it, reserve IO/mem in order to be able to attach devices
later. Do not waste space, use minimum allowed.
Signed-off-by: Marcel Apfelbaum marce...@redhat.com
---
src/fw/pciinit.c | 3 +++
src/hw/pci.c
On Mon, 2014-04-07 at 15:11 +0300, Michael S. Tsirkin wrote:
On Mon, Apr 07, 2014 at 02:01:41PM +0200, Gerd Hoffmann wrote:
On Mo, 2014-04-07 at 13:59 +0300, Marcel Apfelbaum wrote:
If a pci-2-pci bridge supports hot-plug functionality but there are no
devices
connected to it, reserve
On Mon, 2014-04-07 at 16:34 +0300, Michael S. Tsirkin wrote:
On Mon, Apr 07, 2014 at 02:44:06PM +0200, Gerd Hoffmann wrote:
Hi,
+u8 shpc_cap = pci_find_capability(s-bus_dev, PCI_CAP_ID_SHPC);
One thing I'd do is maybe check that the relevant memory type is
enabled in
On Mon, 2014-04-07 at 16:51 +0300, Marcel Apfelbaum wrote:
On Mon, 2014-04-07 at 16:34 +0300, Michael S. Tsirkin wrote:
On Mon, Apr 07, 2014 at 02:44:06PM +0200, Gerd Hoffmann wrote:
Hi,
+u8 shpc_cap = pci_find_capability(s-bus_dev,
PCI_CAP_ID_SHPC);
One
On Mon, 2014-04-07 at 17:09 +0300, Michael S. Tsirkin wrote:
On Mon, Apr 07, 2014 at 04:51:54PM +0300, Marcel Apfelbaum wrote:
[...]
I don't think we'll need that for the SHPC bridge.
Why not?
Because has shpc = not an PCIe port. (as far as I know)
Anyway, why have shpc capability
is configured correctly. (During suspend, the piix pm
configuration space is lost).
Note: For 'ordinary' pci devices the config space is
saved by the OS on sleep and restored on resume.
Signed-off-by: Marcel Apfelbaum marce...@redhat.com
---
v1 - v2:
Addressed Kevin O'Connor comments
On Mon, 2014-01-13 at 16:39 -0500, Kevin O'Connor wrote:
On Mon, Jan 13, 2014 at 07:46:33PM +0200, Marcel Apfelbaum wrote:
On Mon, 2014-01-13 at 11:31 -0500, Kevin O'Connor wrote:
Thanks. SeaBIOS isn't responsible for PCI setup on CSM/coreboot, so
the patch must check for CONFIG_QEMU
On Wed, 2014-01-15 at 14:20 +0200, Marcel Apfelbaum wrote:
On resume, the OS queries the power management event that
caused it. In order to complete this task, it executes some
reads to the piix pm io space. This all happens before the
OS has a chance to restore the PCI config space
On Wed, 2014-01-15 at 11:04 -0500, Kevin O'Connor wrote:
On Wed, Jan 15, 2014 at 02:24:40PM +0200, Marcel Apfelbaum wrote:
On Wed, 2014-01-15 at 14:20 +0200, Marcel Apfelbaum wrote:
On resume, the OS queries the power management event that
caused it. In order to complete this task
On Mon, 2014-01-13 at 09:58 +0100, Gerd Hoffmann wrote:
On Fr, 2013-12-20 at 00:40 +0200, Michael S. Tsirkin wrote:
On Thu, Dec 19, 2013 at 11:32:03PM +0100, Laszlo Ersek wrote:
On 12/19/13 23:16, Michael S. Tsirkin wrote:
I suspect we need to init more devices, but I need to look
On Thu, 2014-01-02 at 19:00 +0200, Marcel Apfelbaum wrote:
On resume, the OS queries the power management event that
caused it. In order to complete this task, it executes some
reads to the piix pm io space. This all happens before the
OS has a chance to restore the PCI config space
On Mon, 2014-01-13 at 15:17 +0200, Michael S. Tsirkin wrote:
On Thu, Jan 02, 2014 at 07:00:45PM +0200, Marcel Apfelbaum wrote:
On resume, the OS queries the power management event that
caused it. In order to complete this task, it executes some
reads to the piix pm io space. This all
On Mon, 2014-01-13 at 15:50 +0200, Marcel Apfelbaum wrote:
On Mon, 2014-01-13 at 15:17 +0200, Michael S. Tsirkin wrote:
On Thu, Jan 02, 2014 at 07:00:45PM +0200, Marcel Apfelbaum wrote:
On resume, the OS queries the power management event that
caused it. In order to complete this task
On Mon, 2014-01-13 at 11:31 -0500, Kevin O'Connor wrote:
On Thu, Jan 02, 2014 at 07:00:45PM +0200, Marcel Apfelbaum wrote:
On resume, the OS queries the power management event that
caused it. In order to complete this task, it executes some
reads to the piix pm io space. This all happens
is configured correctly. (During suspend, the piix pm
configuration space is lost).
Note: For 'ordinary' pci devices the config space is
saved by the OS on sleep and restored on resume.
Signed-off-by: Marcel Apfelbaum marce...@redhat.com
---
This patch is based on Michael S. Tsirkin's patch
On Wed, 2013-12-18 at 19:20 +0200, Michael S. Tsirkin wrote:
On Wed, Dec 18, 2013 at 06:49:24PM +0200, Marcel Apfelbaum wrote:
On Wed, 2013-12-18 at 18:33 +0200, Michael S. Tsirkin wrote:
On Wed, Dec 18, 2013 at 06:27:12PM +0200, Marcel Apfelbaum wrote:
On Wed, 2013-12-18 at 17:22 +0200
On Thu, 2013-12-19 at 11:37 +0200, Marcel Apfelbaum wrote:
On Wed, 2013-12-18 at 19:20 +0200, Michael S. Tsirkin wrote:
On Wed, Dec 18, 2013 at 06:49:24PM +0200, Marcel Apfelbaum wrote:
On Wed, 2013-12-18 at 18:33 +0200, Michael S. Tsirkin wrote:
On Wed, Dec 18, 2013 at 06:27:12PM +0200
On Thu, 2013-12-19 at 11:06 -0500, Kevin O'Connor wrote:
On Wed, Dec 18, 2013 at 06:55:24PM +0200, Marcel Apfelbaum wrote:
On Wed, 2013-12-18 at 11:34 -0500, Paolo Bonzini wrote:
Or put an array of (bdf, offset, size, value) tuples somewhere in low
memory,
fill it at startup
: Mercoledì, 18 dicembre 2013 17:33:06
Oggetto: Re: [Qemu-devel] [PATCH] piix: do not reset APIC base address
(0x80) on piix4_reset.
On Wed, Dec 18, 2013 at 06:27:12PM +0200, Marcel Apfelbaum wrote:
On Wed, 2013-12-18 at 17:22 +0200, Michael S. Tsirkin wrote:
On Wed, Dec 18, 2013 at 03
On Wed, 2013-12-18 at 18:33 +0200, Michael S. Tsirkin wrote:
On Wed, Dec 18, 2013 at 06:27:12PM +0200, Marcel Apfelbaum wrote:
On Wed, 2013-12-18 at 17:22 +0200, Michael S. Tsirkin wrote:
On Wed, Dec 18, 2013 at 03:22:59PM +0100, Paolo Bonzini wrote:
Il 11/12/2013 10:21, Gal Hammer ha
On Mon, 2013-08-05 at 20:24 +0800, Hu Tao wrote:
On Mon, Aug 05, 2013 at 06:13:39AM -0400, Paolo Bonzini wrote:
for example: in Windows(let's say XP) the Device manager will open a
new device wizard and the device will appear as an unrecognized
device. On a cluster with hundreds of
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