Re: [SeaBIOS] [PATCH v4 2/3] pci: add QEMU-specific PCI capability structure

2017-08-07 Thread Marcel Apfelbaum
On 07/08/2017 19:02, Alexander Bezzubikov wrote: 2017-08-07 18:52 GMT+03:00 Marcel Apfelbaum : On 05/08/2017 23:29, Aleksandr Bezzubikov wrote: On PCI init PCI bridge devices may need some extra info about bus number to reserve, IO, memory and prefetchable memory limits.

Re: [SeaBIOS] [PATCH v4 2/3] pci: add QEMU-specific PCI capability structure

2017-08-07 Thread Alexander Bezzubikov
2017-08-07 18:52 GMT+03:00 Marcel Apfelbaum : > On 05/08/2017 23:29, Aleksandr Bezzubikov wrote: >> >> On PCI init PCI bridge devices may need some >> extra info about bus number to reserve, IO, memory and >> prefetchable memory limits. QEMU can provide this >> with special

Re: [SeaBIOS] [PATCH v4 2/3] pci: add QEMU-specific PCI capability structure

2017-08-07 Thread Marcel Apfelbaum
On 05/08/2017 23:29, Aleksandr Bezzubikov wrote: On PCI init PCI bridge devices may need some extra info about bus number to reserve, IO, memory and prefetchable memory limits. QEMU can provide this with special vendor-specific PCI capability. This capability is intended to be used only for Red

[SeaBIOS] [PATCH v4 2/3] pci: add QEMU-specific PCI capability structure

2017-08-05 Thread Aleksandr Bezzubikov
On PCI init PCI bridge devices may need some extra info about bus number to reserve, IO, memory and prefetchable memory limits. QEMU can provide this with special vendor-specific PCI capability. This capability is intended to be used only for Red Hat PCI bridges, i.e. QEMU cooperation.