[SeaBIOS] [PATCH v2 4/4] ahci: set controller id

Fill the controller id in the drive struct with the port number so we get a sane boot menu ordering with multiple hard disks attached. Signed-off-by: Gerd Hoffmann kra...@redhat.com --- src/ahci.c |1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/src/ahci.c b/src/ahci.c

[SeaBIOS] [PATCH v2 1/4] ahci: set dma feature flag

Signed-off-by: Gerd Hoffmann kra...@redhat.com --- src/ahci.c |2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/src/ahci.c b/src/ahci.c index 6c3127a..ee50e8f 100644 --- a/src/ahci.c +++ b/src/ahci.c @@ -50,6 +50,7 @@ static void sata_prep_readwrite(struct sata_cmd_fis

[SeaBIOS] [PATCH v2 0/4] ahci: a bunch of small fixes.

Hi, Here is a bunch of small fixes for the ahci driver which accumulated over the last week. [ v2: use pci_config_maskw, one patch updated ] cheers, Gerd Gerd Hoffmann (4): ahci: set dma feature flag ahci: enable io/mem/dma ahci: fix off-by-one in port count ahci: set controller id

Re: [SeaBIOS] [PATCH v2 2/4] ahci: enable io/mem/dma

Hi, +u16 cmd; You have an unused variable here. Ah, right. Howcome gcc didn't warn me on this, usually it does ... Is that warning turned off for seabios? The patch series looks fine to me. If there's no further comments I'll commit this weekend. Want me respin? Do do you just

Re: [SeaBIOS] Next version

Hi, The current PCI memory space is limited to 236MB. It would be good to increase it to at-least 512MB. KVM supports for device assignment to the VM. For most of the PCI devices the 236MB memory might be enough, but when you pass-through a graphics device, this memory is very limited. I

[SeaBIOS] [PATCH] Make pci memory window configurable.

This patch makes the memory window for PCI memory bars configurable via Kconfig. Signed-off-by: Gerd Hoffmann kra...@redhat.com --- src/Kconfig |6 ++ src/config.h |4 ++-- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 6d55b23

[SeaBIOS] [PATCH v2] Make pci memory window configurable.

This patch makes the memory window for PCI memory bars configurable via Kconfig. [ v2: handle old pcimem assignment method ] Signed-off-by: Gerd Hoffmann kra...@redhat.com --- src/Kconfig | 10 ++ src/config.h |9 - 2 files changed, 14 insertions(+), 5 deletions(-) diff

Re: [SeaBIOS] [PATCH v2] Make pci memory window configurable.

Hi, Is there any reason why there is a fixed split, other than making the code simpler (i.e. need only one instead of two passes over all pci devices)? Because pci-to-pci bridge handles memory access and preferchable memory access differently. Sure. The reason for the two regions is

Re: [SeaBIOS] Xen Hypervisor and Disk Drive Layer

Hi, I am going to write new code to allow SeaBios to use the split-driver model of Xen to write directly to the back-end device of Xen using shared memory, but was wondering if I could leverage the drive abstraction layer that SeaBIOS has for hard drives? I strongly recommend doing that.

Re: [SeaBIOS] [PATCH] Support more than one vga card

Hi, But supporting multiple VGA cards is something we want anyway since I think Spice uses this to have multiple heads. Gerd? The secondary qxl devices are a bit different. They are not vga compatible. They register as generic display class device. They have no vga bios. You need qxl

Re: [SeaBIOS] [RfC PATCH 1/2] pci: move to two-pass pci initialization

On 05/25/11 06:33, Isaku Yamahata wrote: The patch doesn't check any overflows. And it assumes that BAR assignment is always possible. However it isn't true. Some people complained about it before, so I added overflow check. Indeed, there is no error handling at all yet. Some devices have

Re: [SeaBIOS] non-emulated AHCI hardware

Thanks Scott, I'd like to commit these fixes. Is there any chance you could break them up into separate patches - one per fix? That would be great for review too. thanks, Gerd ___ SeaBIOS mailing list SeaBIOS@seabios.org

Re: [SeaBIOS] non-emulated AHCI hardware

patch. Works nicely in qemu. Can you give it a spin on real hardware? cheers, Gerd From 4be00033adb966eb40c1ca2700cc770db0ff682a Mon Sep 17 00:00:00 2001 From: Gerd Hoffmann kra...@redhat.com Date: Thu, 26 May 2011 13:39:26 +0200 Subject: [PATCH] ahci: use interrupt status register Poll

Re: [SeaBIOS] Graphics card pass-through working with two pass pci-initialization

Hi, 0xE000 is hard-coded in the DSDT for both piix and q35 as below. If the range is determined dynamically, the area also needs to be updated somehow dynamically. ... Name (_CRS, ResourceTemplate () ... DWordMemory (ResourceProducer, PosDecode, MinFixed,

Re: [SeaBIOS] [PATCH 0/4] Use 'struct pci_device' to limit option rom execution.

Hi, This patch series extends the proliferation of 'struct pci_device' which was introduced in the last patch series. The objective of this series is to ensure that ATA devices configured to use the native ATA driver don't attempt to run an option rom on the device. This can become complex

[SeaBIOS] [PATCH 0/4] pci: two-pass initilaization.

Hi, Removed the dust from the two-pass pci initialization code and posting the bits for review to move forward. Rebased from q35 tree to latest upstream master. Uses the new pci_device struct now. cheers, Gerd Gerd Hoffmann (4): pci: add two-pass pci initialization code pci: activate

[SeaBIOS] [PATCH 2/4] pci: activate two-pass pci initialization code

This patch actually enables the two-pass pci initialization and deactivates the old pci initialization bits. Signed-off-by: Gerd Hoffmann kra...@redhat.com --- src/pciinit.c | 36 ++-- 1 files changed, 34 insertions(+), 2 deletions(-) diff --git a/src/pciinit.c

[SeaBIOS] [PATCH 1/4] pci: add two-pass pci initialization code

to make debugging easier. Signed-off-by: Gerd Hoffmann kra...@redhat.com --- src/pci.h |8 + src/pciinit.c | 416 - 2 files changed, 421 insertions(+), 3 deletions(-) diff --git a/src/pci.h b/src/pci.h index a21a1fd..868752d 100644

[SeaBIOS] [PATCH 3/4] pci: remove old pci initilaization code

Signed-off-by: Gerd Hoffmann kra...@redhat.com --- Makefile |2 +- src/pci_region.c | 77 - src/pciinit.c| 197 -- src/util.h | 29 4 files changed, 1 insertions(+), 304 deletions

Re: [SeaBIOS] [PATCH 1/4] pci: add two-pass pci initialization code

Hi, +static struct pci_bus { +/* pci region stats */ +u32 io_count[16 - PCI_IO_INDEX_SHIFT]; +u32 mem_count[32 - PCI_MEM_INDEX_SHIFT]; +u32 prefmem_count[32 - PCI_MEM_INDEX_SHIFT]; +u32 io_sum, io_max; +u32 mem_sum, mem_max; +u32 prefmem_sum, prefmem_max; +/*

[SeaBIOS] [PATCH v2 0/4] pci: two-pass initialization

. cheers, Gerd PS: also available here: http://www.kraxel.org/cgit/seabios/log/?h=pci.2 Gerd Hoffmann (4): pci: add two-pass pci initialization code pci: activate two-pass pci initialization code pci: remove old pci initilaization code pci: init boot devices only on address space

[SeaBIOS] [PATCH v2 4/4] pci: init boot devices only on address space shortage

Try to handle address space shortage by skipping any device which isn't essential for boot. Signed-off-by: Gerd Hoffmann kra...@redhat.com --- src/pci.c |3 +++ src/pciinit.c | 51 +-- src/util.h|2 ++ 3 files changed, 54

[SeaBIOS] [PATCH v3 0/6] pci: two-pass initialization

Hi, Next round of the two-pass initialization patches, addressing the review comments from Kevin. cheers, Gerd Gerd Hoffmann (6): pci: add two-pass pci initialization code pci: activate two-pass pci initialization code pci: remove old pci initilaization code pci: init boot devices

[SeaBIOS] [PATCH v3 1/6] pci: add two-pass pci initialization code

to make debugging easier. Signed-off-by: Gerd Hoffmann kra...@redhat.com --- src/pci.h |8 ++ src/pciinit.c | 312 - 2 files changed, 317 insertions(+), 3 deletions(-) diff --git a/src/pci.h b/src/pci.h index a21a1fd..e9e191a

[SeaBIOS] [PATCH v3 3/6] pci: remove old pci initilaization code

Signed-off-by: Gerd Hoffmann kra...@redhat.com --- Makefile |2 +- src/pci_region.c | 77 - src/pciinit.c| 197 -- src/util.h | 29 4 files changed, 1 insertions(+), 304 deletions

[SeaBIOS] [PATCH v3 6/6] pci: set BUILD_PCIMEM_START to 0xe0000000

... and make it match with the declarations in acpi-dsdt.dsl. Signed-off-by: Gerd Hoffmann kra...@redhat.com --- src/config.h |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/config.h b/src/config.h index 687cac6..f2fce89 100644 --- a/src/config.h +++ b/src/config.h

[SeaBIOS] [PATCH v3 5/6] pci: cleanup config.h

Signed-off-by: Gerd Hoffmann kra...@redhat.com --- src/config.h | 14 -- src/pciinit.c |2 +- 2 files changed, 1 insertions(+), 15 deletions(-) diff --git a/src/config.h b/src/config.h index e6e07c9..687cac6 100644 --- a/src/config.h +++ b/src/config.h @@ -40,23 +40,9

Re: [SeaBIOS] [PATCH v3 4/6] pci: init boot devices only on address space shortage

On 07/05/11 18:23, Michael S. Tsirkin wrote: On Tue, Jul 05, 2011 at 05:27:03PM +0200, Gerd Hoffmann wrote: Try to handle address space shortage by skipping any device which isn't essential for boot. Signed-off-by: Gerd Hoffmannkra...@redhat.com At least in a virt setup, it's much easier

Re: [SeaBIOS] [PATCH] pci: capability scanning function'

On 07/06/11 16:57, Michael S. Tsirkin wrote: On Wed, Jul 06, 2011 at 05:03:21PM +0300, Michael S. Tsirkin wrote: Add pci_find_capability to scan capability list. Return 0 on error, capability offset if found. Signed-off-by: Michael S. Tsirkinm...@redhat.com --- Not useful by itself, but

[SeaBIOS] [PATCH 2/5] pci: activate two-pass pci initialization code

This patch actually enables the two-pass pci initialization and deactivates the old pci initialization bits. Signed-off-by: Gerd Hoffmann kra...@redhat.com --- src/pciinit.c | 38 ++ 1 files changed, 34 insertions(+), 4 deletions(-) diff --git a/src

[SeaBIOS] [PATCH 5/5] pci: set BUILD_PCIMEM_START to 0xe0000000

... and make it match with the declarations in acpi-dsdt.dsl. Signed-off-by: Gerd Hoffmann kra...@redhat.com --- src/config.h |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/config.h b/src/config.h index 687cac6..f2fce89 100644 --- a/src/config.h +++ b/src/config.h

[SeaBIOS] [PATCH 0/5] pci: two-pass initialization

Hi, Next (and hopefully final) version of the two-pass pci initialization patches. Addressed review comments, fixed some bugs, especially the io range setup for bridges. cheers, Gerd Gerd Hoffmann (5): pci: add two-pass pci initialization code pci: activate two-pass pci initialization

[SeaBIOS] [PATCH 3/5] pci: remove old pci initilaization code

Signed-off-by: Gerd Hoffmann kra...@redhat.com --- Makefile |2 +- src/pci_region.c | 77 - src/pciinit.c| 197 -- src/util.h | 29 4 files changed, 1 insertions(+), 304 deletions

[SeaBIOS] [PATCH 4/5] pci: cleanup config.h

Signed-off-by: Gerd Hoffmann kra...@redhat.com --- src/config.h | 14 -- src/pciinit.c |2 +- 2 files changed, 1 insertions(+), 15 deletions(-) diff --git a/src/config.h b/src/config.h index e6e07c9..687cac6 100644 --- a/src/config.h +++ b/src/config.h @@ -40,23 +40,9

Re: [SeaBIOS] [PATCH 5/5] pci: set BUILD_PCIMEM_START to 0xe0000000

Hi, -#define BUILD_PCIMEM_START0xf000 +#define BUILD_PCIMEM_START0xe000 I thought there was some dependency on 0xe000 in the VGA BIOS. Has that been cleared up now? Yes, the magic bochs vga lfb @ 0xe000 is gone in recent qemu (version 0.14 + newer). The

[SeaBIOS] [PATCH 5/7] ahci: don't expect ATA_CB_STAT_DRQ being clear

Signed-off-by: Gerd Hoffmann kra...@redhat.com --- src/ahci.c |5 ++--- 1 files changed, 2 insertions(+), 3 deletions(-) diff --git a/src/ahci.c b/src/ahci.c index e2ec07a..7279199 100644 --- a/src/ahci.c +++ b/src/ahci.c @@ -158,7 +158,7 @@ static int ahci_command(struct ahci_port_s *port

[SeaBIOS] [PATCH 0/7] ahci update

The following changes since commit 77b8536e5c9908fbe99c88d01462a36a3deb05b1: pci: set BUILD_PCIMEM_START to 0xe000 (2011-07-12 21:14:53 -0400) are available in the git repository at: git://git.kraxel.org/seabios ahci Gerd Hoffmann (6): ahci/sata: Fix FIS setup. ahci: use interrupt

[SeaBIOS] [PATCH 1/7] ahci/sata: Fix FIS setup.

FIS setup does't follow the SATA specs, fix it. Credits go to Jonathan Kollasch and Scott Duplichan for finding those. Signed-off-by: Gerd Hoffmann kra...@redhat.com --- src/ahci.c |7 +++ 1 files changed, 3 insertions(+), 4 deletions(-) diff --git a/src/ahci.c b/src/ahci.c index

[SeaBIOS] [PATCH 7/7] ahci: bootprio support

Wind up bootprio support in the ahci driver so boot device ordering works for ahci disks too. No extra work needed on qemu side. Signed-off-by: Gerd Hoffmann kra...@redhat.com --- src/ahci.c | 15 ++- src/ahci.h |3 ++- 2 files changed, 12 insertions(+), 6 deletions(-) diff

[SeaBIOS] [PATCH 2/7] ahci: use interrupt status register

Poll interrupt status register to figure when the device has updated the status and possibly finished the request, continue polling until BSY is clear as we might see multiple status updates per request. Signed-off-by: Gerd Hoffmann kra...@redhat.com --- src/ahci.c | 43

[SeaBIOS] [PATCH 4/7] ahci: handle unaligned buffers.

From: Scott Duplichan sc...@notabs.org This change allows unaligned buffers to be used for reads or writes to non-atapi devices. Currently only MS-DOS boot is known to need unaligned buffer support. Signed-off-by: Scott Duplichan sc...@notabs.org Signed-off-by: Gerd Hoffmann kra...@redhat.com

[SeaBIOS] [PATCH 3/7] ahci: add error recovery code

By Scott Duplichan. Signed-off-by: Gerd Hoffmann kra...@redhat.com --- src/ahci.c | 50 +++--- 1 files changed, 47 insertions(+), 3 deletions(-) diff --git a/src/ahci.c b/src/ahci.c index 9ff1324..ec698ef 100644 --- a/src/ahci.c +++ b/src/ahci.c

[SeaBIOS] [PATCH 6/7] ahci: rework init workflow fix timeout handling

it when no drive is present. In case we detect a drive we have to free and realloc the memory with malloc_low() so it is available after POST when the boot loader wants read stuff via int13. Also use TSC to calculate timeout instead of delays and loop counts. Signed-off-by: Gerd Hoffmann kra

Re: [SeaBIOS] [PATCH 0/7] ahci update

On 07/17/11 16:16, Kevin O'Connor wrote: On Thu, Jul 14, 2011 at 04:23:58PM +0200, Gerd Hoffmann wrote: Hi, Finally the update for the ahci code, featuring: * A bunch of bugfixes, which makes the code work on real hardware (additionally to the qemu emulated ahci adapter

Re: [SeaBIOS] [PATCH 0/7] ahci update

Hi, Finally found the time to look at this. I do have some comments, but I think they can be addressed on top if needed. In patch 2 - there is a nested loop - the inside looping checking for an interrupt and the outside loop checking for BSY. I don't see how an interrupt could fire when

[SeaBIOS] [PATCH 2/5] ahci: probe each port in its own thread

Instead if creating a single thread which probes all ports one after another kick one thread per port, so ports are probed in parallel. Signed-off-by: Gerd Hoffmann kra...@redhat.com --- src/ahci.c | 41 - 1 files changed, 20 insertions(+), 21 deletions

[SeaBIOS] [PATCH 0/5] ahci fixups

Hi, Here comes a bumnch of fixes for the ahci code, see the individual patches for details. cheers, Gerd Gerd Hoffmann (5): ahci/cdrom: shared bounce buffer ahci: probe each port in its own thread ahci: ignore atapi devices which are not cdroms ahci: move device registration ahci

[SeaBIOS] [PATCH 1/5] ahci/cdrom: shared bounce buffer

This patch creates a common bounce buffer in block.c which is shared by the cdrom and ahci drivers. Signed-off-by: Gerd Hoffmann kra...@redhat.com --- src/ahci.c |7 +++ src/block.c | 14 ++ src/cdrom.c | 10 -- src/disk.h |2 ++ 4 files changed, 23

[SeaBIOS] [PATCH 4/5] ahci: move device registration

Stick description and boot priority into the port struct, so it holds everything needed to register the device, so we can do the registration after ahci_port_init returned. Signed-off-by: Gerd Hoffmann kra...@redhat.com --- src/ahci.c | 27 ++- src/ahci.h |2 ++ 2

[SeaBIOS] [PATCH 3/5] ahci: ignore atapi devices which are not cdroms

Also simplify the code a bit further down the road as we know iscd must be true ;) Signed-off-by: Gerd Hoffmann kra...@redhat.com --- src/ahci.c | 15 --- 1 files changed, 8 insertions(+), 7 deletions(-) diff --git a/src/ahci.c b/src/ahci.c index 55ada5f..c1b436d 100644 --- a/src

[SeaBIOS] [PATCH] ahci: enable by default

Lack of real hardware testing was the main reason to turn it off by default. The AHCI has been fixed to work on both qemu and real hardware, so lets flip the switch now. Signed-off-by: Gerd Hoffmann kra...@redhat.com --- src/Kconfig |2 +- 1 files changed, 1 insertions(+), 1 deletions

[SeaBIOS] Time to cut a new release?

Hi, A bunch of new stuff has been added to master since the last version, time to release a new one? Especially I'd like to see qemu get a seabios update, and anthony prefers a release instead of a git snapshot for that. cheers, Gerd ___

[SeaBIOS] [PATCH] pci: re-add isa bridge setup

The switch to the two-pass pci initialization dropped the isa bridge initialization by accident. That broke interrupts on FreeBSD 4.4 and maybe also other older guests which don't use ACPI for IRQ routing setup. Add the bits back in. Cc: Bjørn Mork bj...@mork.no Signed-off-by: Gerd Hoffmann kra

Re: [SeaBIOS] Help with 16bit and 32bitFlat

Hi, The disk access code is called from 16bit mode, and thus it needs to be compiled in 16bit mode. The link errors you are seeing are there to force a build error (instead of failing mysterously at run time). What does your driver do that requires 32bit mode? Access special pages for

Re: [SeaBIOS] Status of SeaBIOS VGA bios.

Hi, I started converting the VGA bios from the lgpl vga bios project ( http://savannah.nongnu.org/projects/vgabios/ ) a couple of years ago. I converted the base code, but did not have time to convert the VBE or the cirrus code. qemu uses the lgpl vga bios too, slightly modified version,

Re: [SeaBIOS] Status of SeaBIOS VGA bios.

Hi, I havn't tried to run the ROM yet. Could you be more precise about what works (or what is supposed to be working), what's not, and what exactly remains to be translated ? I'd like to make an idea of the amount of work required to have a ROM equivalent to vgabios. If you look at the

Re: [SeaBIOS] [Qemu-devel] [BUG] [Seabios] PCI 64bit BARs on Win2008 - unable to start the device. (ACPI lacks the _DSM method)

Hi, PCI: map device bus 0, bfd 0x28 bar 0, addr febe, size 1 [mem] bar 1, addr 0, size 2000 [mem] Somehow seabios didn't recognise the bar correctly it seems (both 512 and 256 MB cases look the same). For the 256 MB case seabios should have mapped the bar @ 0xe000.

Re: [SeaBIOS] [BUG] [Seabios] PCI 64bit BARs on Win2008 - unable to start the device. (ACPI lacks the _DSM method)

Hi, Two possible ideas: 1. Pass the value in from qemu Do you mean to create the 64bit region dynamically? I've tried to obtain RAM size somehow inside DSL code, but the ACPI spec doesn't tell how to do that. There is a global variable IIRC. You could also check the e820 table passed in

Re: [SeaBIOS] [Qemu-devel] [BUG] [Seabios] PCI 64bit BARs on Win2008 - unable to start the device. (ACPI lacks the _DSM method)

On 12/14/11 05:30, Alexey Korolev wrote: Hi, It shouldn't be that hard to add the latter though. seabios needs two more pci_region_type (PCI_REGION_TYPE_MEM_64 and PCI_REGION_TYPE_PREFMEM_64) to track and map 64bit bars separately. And a address space window where it can map 64bit bars to.

Re: [SeaBIOS] Error booting from USB Storage Device in QEMU-KVM GIT MASTER

On 01/19/12 13:57, Dyweni - Qemu-Devel wrote: Hi, I am unable to boot KVM using a usb flash drive. I'm using QEMU-KVM built from GIT MASTER as of this morning. Start bios (version 1.6.3) USB MSC vendor='QEMU' product='QEMU HARDDISK' rev='1.0.' type=0 removable=0 Unable to configure USB

Re: [SeaBIOS] S3 resume is broken on QEMU

On 01/20/12 02:40, Kevin O'Connor wrote: On Thu, Jan 19, 2012 at 12:16:25PM +0200, Gleb Natapov wrote: There is absolutely nothing that vgabios may attempt to do that is illegal on resume and may cause this kind of hang. The only thing that is illegal on resume is to use non reserved RAM, but

Re: [SeaBIOS] S3 resume is broken on QEMU

to handle on the qemu side, see attached patch. cheers, Gerd From 311be2fd346b75c296856299250ada7c5ffbf207 Mon Sep 17 00:00:00 2001 From: Gerd Hoffmann kra...@redhat.com Date: Thu, 19 Jan 2012 11:46:55 +0100 Subject: [PATCH] enable s3-resume-vga-init Signed-off-by: Gerd Hoffmann kra

Re: [SeaBIOS] S3 resume is broken on QEMU

Hi, I'm 99% sure that wont work. Option roms have to be copied from PCI You 99% sure it wont work on real HW or on QEMU? IIRC QEMU puts vgabios into 0xc directly. That is long history, it went away about the same time qemu switched from bochs bios to seabios. These

[SeaBIOS] [PATCH 0/5] vgabios: build variants for qemu

different variants in one go. Patches #2 .. #5 enable more qemu virtual hardware support on top of that. Gerd Hoffmann (5): vgabios: support building multiple variants. bochsvga: handle vmware vga. bochsvga: build bios variant for vmware. bochsvga: build bios variant for qxl. bochsvga

[SeaBIOS] [PATCH 4/5] bochsvga: build bios variant for qxl.

Signed-off-by: Gerd Hoffmann kra...@redhat.com --- Makefile |4 vgasrc/Kconfig |7 +++ 2 files changed, 11 insertions(+), 0 deletions(-) diff --git a/Makefile b/Makefile index 8090ae9..8e85ba4 100644 --- a/Makefile +++ b/Makefile @@ -71,6 +71,7 @@ target-y = $(OUT) $(OUT

Re: [SeaBIOS] [PATCH 0/5] vgabios: build variants for qemu

On 01/24/12 01:23, Kevin O'Connor wrote: On Mon, Jan 23, 2012 at 12:30:29PM +0100, Gerd Hoffmann wrote: Hi, This patch series prepares vgabios for being used as qemu vga bios. Are you thinking of driving an effort to replace the default vga bios in qemu? (Assistance would be helpful

[SeaBIOS] [RFC PATCH 0/4] vgabios runtime hardware detection

Hi, This adds runtime hardware detection to vgabios. Survived light (vga text mode) testing. The isa bits are completely untested as qemu -M isapc is foobar atm. Comments on the approach? cheers, Gerd Gerd Hoffmann (4): vga: move code to vgahw.c vga: add pci hardware detection vga

[SeaBIOS] [RFC PATCH 4/4] vga: adapt kconfig

With support for multiple vga hardware types being selectable it isn't a choice any more. --- vgasrc/Kconfig | 61 --- 1 files changed, 27 insertions(+), 34 deletions(-) diff --git a/vgasrc/Kconfig b/vgasrc/Kconfig index 881e9ec..fc7fec4

[SeaBIOS] [RFC PATCH 3/4] vga: add isa hardware detection

Try to find isa vga cards in case pci probe found nothing. Signed-off-by: Gerd Hoffmann kra...@redhat.com --- vgasrc/bochsvga.c |7 +++ vgasrc/bochsvga.h |1 + vgasrc/clext.c|6 ++ vgasrc/clext.h|1 + vgasrc/vgahw.c| 20 +++- 5 files changed

[SeaBIOS] [RFC PATCH 1/4] vga: move code to vgahw.c

Create vgahw.c, move code from vgahw.h there, soon we will add more bits there which will make inlining less useful. Signed-off-by: Gerd Hoffmann kra...@redhat.com --- Makefile |2 +- vgasrc/vgahw.c | 37 + vgasrc/vgahw.h | 38

Re: [SeaBIOS] [RFC PATCH 0/4] vgabios runtime hardware detection

On 01/26/12 02:58, Kevin O'Connor wrote: Thinking on that further, though, should we end up supporting the 32bit VBE calls, then function pointers would likely get confusing. I think we can get away with *not* supporting them. First, the lgpl vgabios supports them only for the bochs dispi

Re: [SeaBIOS] [RFC PATCH 0/4] vgabios runtime hardware detection

Hi, It's an interesting question - is it better to compile a vgabios for a specific hardware or to make a vgabios compatible with several different pieces of hardware. I don't know what the right answer is. Alot of stuff seems to be shared, the size doesn't go up much: -rw-rw-r--. 1

[SeaBIOS] [PATCH 4/7] vga: adapt kconfig

With support for multiple vga hardware types being selectable it isn't a choice any more. Signed-off-by: Gerd Hoffmann kra...@redhat.com --- vgasrc/Kconfig | 61 --- 1 files changed, 27 insertions(+), 34 deletions(-) diff --git a/vgasrc

[SeaBIOS] [PATCH 6/7] vga: add qxl

Add QXL vga to the device list. Signed-off-by: Gerd Hoffmann kra...@redhat.com --- vgasrc/vgahw.c |6 ++ 1 files changed, 6 insertions(+), 0 deletions(-) diff --git a/vgasrc/vgahw.c b/vgasrc/vgahw.c index 48fb070..92c2472 100644 --- a/vgasrc/vgahw.c +++ b/vgasrc/vgahw.c @@ -34,6 +34,12

[SeaBIOS] [PATCH 2/7] vga: add pci hardware detection

Add support for pci hardware detection (using pci id lookup), so we can create a unified rom with support for different pieces of hardware. Signed-off-by: Gerd Hoffmann kra...@redhat.com --- vgasrc/vgahw.c | 109 --- vgasrc/vgahw.h | 20

[SeaBIOS] [PATCH 5/7] vga: add vmware

Add vmware vga to the device list. Signed-off-by: Gerd Hoffmann kra...@redhat.com --- vgasrc/vgahw.c |6 ++ 1 files changed, 6 insertions(+), 0 deletions(-) diff --git a/vgasrc/vgahw.c b/vgasrc/vgahw.c index 1401fba..48fb070 100644 --- a/vgasrc/vgahw.c +++ b/vgasrc/vgahw.c @@ -28,6

[SeaBIOS] [PATCH 1/7] vga: move code to vgahw.c

Create vgahw.c, move code from vgahw.h there, soon we will add more bits there which will make inlining less useful. Signed-off-by: Gerd Hoffmann kra...@redhat.com --- Makefile |2 +- vgasrc/vgahw.c | 95 vgasrc/vgahw.h | 93

Re: [SeaBIOS] [PATCH 0/7] vgabios runtime hardware detection

On 02/07/12 01:38, Kevin O'Connor wrote: On Mon, Feb 06, 2012 at 03:51:36PM +0100, Gerd Hoffmann wrote: Hi, Here is the runtime vga hardware detection patch series, rebased and adapted to latest master. Thinking about this further, if multiple drivers are compiled in, I'm not sure what

[SeaBIOS] [PATCH 2/3] vga: add pci hardware detection

Add support for pci hardware detection (using pci id lookup), so we can create a unified rom with support for different pieces of hardware. Signed-off-by: Gerd Hoffmann kra...@redhat.com --- vgasrc/Kconfig | 12 ++ vgasrc/vgabios.c |2 +- vgasrc/vgahw.c | 114

[SeaBIOS] [PATCH 0/3] runtime hardware detection series.

Hi, Next round, this time introducing a CONFIG_VGA_QEMU and doing the hardware detection for qemu-emulated hardware only. Also clarifies Kconfig (cirrus is for emulated hardware only) as side effect. cheers, Gerd Gerd Hoffmann (3): vga: move code to vgahw.c vga: add pci hardware

[SeaBIOS] [PATCH 1/3] vga: move code to vgahw.c

Create vgahw.c, move code from vgahw.h there, soon we will add more bits there which will make inlining less useful. Signed-off-by: Gerd Hoffmann kra...@redhat.com --- Makefile |2 +- vgasrc/vgahw.c | 136 vgasrc/vgahw.h | 134

Re: [SeaBIOS] [PATCH 0/3] runtime hardware detection series.

On 02/09/12 02:06, Kevin O'Connor wrote: On Wed, Feb 08, 2012 at 05:38:56PM +0100, Gerd Hoffmann wrote: Hi, Next round, this time introducing a CONFIG_VGA_QEMU and doing the hardware detection for qemu-emulated hardware only. Also clarifies Kconfig (cirrus is for emulated hardware only

[SeaBIOS] [PATCH 0/5] rom build scripting, switch vgabios implementation

are updated. Tests, comments etc, are welcome. cheers, Gerd The following changes since commit cf4dc461a4cfc3e056ee24edb26154f4d34a6278: Restore consistent formatting (2012-02-07 22:11:04 +0400) are available in the git repository at: git://git.kraxel.org/qemu bios.1 Gerd Hoffmann (5

[SeaBIOS] [PATCH 2/5] Add vgabios build scripts to roms/

Signed-off-by: Gerd Hoffmann kra...@redhat.com --- roms/Makefile | 17 + roms/config.vga.cirrus|3 +++ roms/config.vga.isavga|3 +++ roms/config.vga.qxl |6 ++ roms/config.vga.stdvga|3 +++ roms/config.vga.vmware|6

[SeaBIOS] [PATCH 1/5] update seabios to latest master [feb 9th]

Signed-off-by: Gerd Hoffmann kra...@redhat.com --- pc-bios/vgabios-cirrus.bin | Bin 35840 - 35328 bytes roms/seabios |2 +- 2 files changed, 1 insertions(+), 1 deletions(-) diff --git a/pc-bios/vgabios-cirrus.bin b/pc-bios/vgabios-cirrus.bin index

Re: [SeaBIOS] Time for a new release?

On 02/14/12 14:35, Kevin O'Connor wrote: On Thu, Feb 09, 2012 at 01:22:23PM +0100, Fred . wrote: Lots of stuff have been happening lately (namely VGA and VBE related stuff). Also some fixes. Perhaps it is time for a new release soon? It's a good question. I have some USB fixes I want to

[SeaBIOS] [PATCH 1/5] 64bit hex printf support

Add support for printing 64bit hex numbers to src/output.c Signed-off-by: Gerd Hoffmann kra...@redhat.com --- src/output.c | 32 ++-- 1 files changed, 26 insertions(+), 6 deletions(-) diff --git a/src/output.c b/src/output.c index bdde7cc..0873776 100644 --- a/src

[SeaBIOS] [PATCH 0/5] pci: 64bit support

for ressource allocation above 4G. The remaining patches carry bugfixes and little bits such as support for printing 64bit hex numbers. cheers, Gerd Gerd Hoffmann (5): 64bit hex printf support pci: split device discovery into multiple steps pci: 64bit support. pci: bridges can have two

[SeaBIOS] [PATCH 5/5] pci: add prefmem64 region type.

looking at drivers/pci/setup-bus.c in the linux kernel source tree). It also avoids assigning ressources for both prefmem and prefmem64 ;) With this patch applied seabios is able to map 64bit bars above 4G. TODO: detect 64bit capable bridges. Signed-off-by: Gerd Hoffmann kra...@redhat.com --- src

[SeaBIOS] [PATCH 4/5] pci: bridges can have two regions too

Signed-off-by: Gerd Hoffmann kra...@redhat.com --- src/pciinit.c | 20 1 files changed, 8 insertions(+), 12 deletions(-) diff --git a/src/pciinit.c b/src/pciinit.c index 7de72f4..a98f6e3 100644 --- a/src/pciinit.c +++ b/src/pciinit.c @@ -402,7 +402,7 @@ static void

[SeaBIOS] [PATCH 3/5] pci: 64bit support.

Makes pciinit.c 64bit aware. Use 64bit everywhere. Support discovery and configuration of 64bit bars, with non-zero upper32 bits. While being at it introduce a struct pci_bar which can be passed easily. Signed-off-by: Gerd Hoffmann kra...@redhat.com --- src/pci.h | 14 +--- src

Re: [SeaBIOS] [PATCH 0/5] pci: 64bit support

On 02/16/12 18:21, Gerd Hoffmann wrote: Hi, The effort to add support for 64bit pci bars to qemu seems to have stalled somehow. Lets resume it ;) Here is a patch collection, largely rewritten from scratch, which improves seabios 64bit support. One big patch (#3) adds 64bit math

Re: [SeaBIOS] [PATCH 0/5] pci: 64bit support

Hi, I haven't really had a chance to review it. Initial thoughts were - on patch 1, I'm not sure how that will impact stack usage which is quite tight when running in 16bit mode; Stack usage doesn't grow much I think. struct pci_dev becomes larger, but I doubt you can find those on the

Re: [SeaBIOS] [PATCH 0/5] pci: 64bit support

On 02/22/12 14:38, Kevin O'Connor wrote: On Wed, Feb 22, 2012 at 11:55:53AM +0100, Gerd Hoffmann wrote: I haven't really had a chance to review it. Initial thoughts were - on patch 1, I'm not sure how that will impact stack usage which is quite tight when running in 16bit mode; Stack usage

[SeaBIOS] [PATCH v2 6/6] pci: add prefmem64

This patch adds a prefmem64 region for 64bit pci prefmem bars which we'll go map above 4G. This will happen when either the device is on the root bus or it is behind a bridge supporting 64bit memory windows and all prefmem bars of all devices hooked up using that bridge are 64bit capable. ---

[SeaBIOS] [PATCH v2 2/6] pci: split device discovery into multiple steps

First bridge init, next pci bar discovery, finally pci bar ressource allocation. Needed because we need to figure whenever we can map 64bit bars above 4G before doing ressource allocation. Signed-off-by: Gerd Hoffmann kra...@redhat.com --- src/pciinit.c | 39

[SeaBIOS] [PATCH v2 0/6] pci: 64bit support

) more readable. * full support for bridges with 64bit memory windows, even nested. Also availabe from: git://git.kraxel.org/seabios pci64 enjoy, Gerd Gerd Hoffmann (6): output: add 64bit hex print support pci: split device discovery into multiple steps pci: 64bit support. pci

[SeaBIOS] [PATCH v2 4/6] pci: bridges can have two regions too

Signed-off-by: Gerd Hoffmann kra...@redhat.com --- src/pciinit.c | 20 1 files changed, 8 insertions(+), 12 deletions(-) diff --git a/src/pciinit.c b/src/pciinit.c index aa391a0..33b9bf7 100644 --- a/src/pciinit.c +++ b/src/pciinit.c @@ -402,7 +402,7 @@ static void

[SeaBIOS] [PATCH v2 3/6] pci: 64bit support.

Makes pciinit.c 64bit aware. Use 64bit everywhere. Support discovery and configuration of 64bit bars, with non-zero upper32 bits. While being at it introduce a struct pci_bar which can be passed easily. Signed-off-by: Gerd Hoffmann kra...@redhat.com --- src/pci.h | 14 -- src

Re: [SeaBIOS] [Seabios] [PATCH 0/6] 64bit PCI BARs allocations (take 2)

Hi, a) Provide 64bit bar support for PCI BARs and bridges with 64bit memory window. Bridge support seems to be completely untested. /me has a test setup using mst's bridge patches which looks like this: [root@fedora ~]# lspci -tv -[:00]-+-00.0 Intel Corporation 440FX - 82441FX PMC

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