Hi Folks,
Could anyone give me a 101 lesson on what is two-pass PCI initialization?
I tried some time ago to pass a LSI megaraid to a rhel5 guest, but the
initialization of the pci device inside the VM fails (because, I think, it
was already initialized in the host).
Just wondering could that
Hi,
0xE000 is hard-coded in the DSDT for both piix and q35 as below.
If the range is determined dynamically, the area also needs to be
updated somehow dynamically.
...
Name (_CRS, ResourceTemplate ()
...
DWordMemory (ResourceProducer, PosDecode, MinFixed,
On 01.06.2011, at 09:30, Gerd Hoffmann wrote:
Hi,
0xE000 is hard-coded in the DSDT for both piix and q35 as below.
If the range is determined dynamically, the area also needs to be
updated somehow dynamically.
...
Name (_CRS, ResourceTemplate ()
...
Sorry I forgot to include all addresses.
I don't know how much work it would be to generate the DSDT dynamically from
Qemu, but IMHO that's the sanest way to make things flexible. We could
probably even extract most information from the Qdev tree.
Well I have written for coreboot a ACPI
On 06/01/2011 12:56 PM, Alexander Graf wrote:
On 01.06.2011, at 09:30, Gerd Hoffmann wrote:
Hi,
0xE000 is hard-coded in the DSDT for both piix and q35 as below.
If the range is determined dynamically, the area also needs to be
updated somehow dynamically.
...
Name
On 01.06.2011, at 13:13, Avi Kivity wrote:
On 06/01/2011 12:56 PM, Alexander Graf wrote:
On 01.06.2011, at 09:30, Gerd Hoffmann wrote:
Hi,
0xE000 is hard-coded in the DSDT for both piix and q35 as below.
If the range is determined dynamically, the area also needs to be
On 2011-06-01 16:20, Isaku Yamahata wrote:
On Wed, Jun 01, 2011 at 09:30:12AM +0200, Gerd Hoffmann wrote:
Hi,
0xE000 is hard-coded in the DSDT for both piix and q35 as below.
If the range is determined dynamically, the area also needs to be
updated somehow dynamically.
...
Having a brief look at the coreboot code it seems static stuff (compiled by
iasl) and dynamic bits are combined into the final dsdt table, is that correct?
Yes the dsdt is static, it has just external references to ssdt which is
dynamically generated using the acpigen.
Acpigen can generate
On Wed, Jun 01, 2011 at 04:40:15PM +0200, Rudolf Marek wrote:
Having a brief look at the coreboot code it seems static stuff (compiled by
iasl) and dynamic bits are combined into the final dsdt table, is that
correct?
Yes the dsdt is static, it has just external references to ssdt
which is
On Wed, Jun 01, 2011 at 11:20:29PM +0900, Isaku Yamahata wrote:
On Wed, Jun 01, 2011 at 09:30:12AM +0200, Gerd Hoffmann wrote:
Hi,
0xE000 is hard-coded in the DSDT for both piix and q35 as below.
If the range is determined dynamically, the area also needs to be
updated somehow
On 2010-05-28 20:49, André Weidemann wrote:
Hi,
On 28.05.2011 10:18, Jan Kiszka wrote:
On 2011-05-26 23:19, André Weidemann wrote:
On 27.05.2011 21:50, André Weidemann wrote:
On 27.05.2011 21:40, André Weidemann wrote:
If I am not mistaken then the graphics card needs 2 bars, one with
Hi,
On 29.05.2011 17:22, Jan Kiszka wrote:
On 2010-05-28 20:49, André Weidemann wrote:
Hi,
On 28.05.2011 10:18, Jan Kiszka wrote:
On 2011-05-26 23:19, André Weidemann wrote:
On 27.05.2011 21:50, André Weidemann wrote:
On 27.05.2011 21:40, André Weidemann wrote:
If I am not mistaken then
On 2011-05-29 21:30, André Weidemann wrote:
Hi,
On 29.05.2011 17:22, Jan Kiszka wrote:
On 2010-05-28 20:49, André Weidemann wrote:
Hi,
On 28.05.2011 10:18, Jan Kiszka wrote:
On 2011-05-26 23:19, André Weidemann wrote:
On 27.05.2011 21:50, André Weidemann wrote:
On 27.05.2011 21:40,
On 2011-05-26 23:19, André Weidemann wrote:
On 27.05.2011 21:50, André Weidemann wrote:
On 27.05.2011 21:40, André Weidemann wrote:
If I am not mistaken then the graphics card needs 2 bars, one with 256MB
and one with 128K. The sound card then needs 1 bar with 16K of PCI
memory.
How big is
Hi,
On 28.05.2011 10:18, Jan Kiszka wrote:
On 2011-05-26 23:19, André Weidemann wrote:
On 27.05.2011 21:50, André Weidemann wrote:
On 27.05.2011 21:40, André Weidemann wrote:
If I am not mistaken then the graphics card needs 2 bars, one with 256MB
and one with 128K. The sound card then
On 2011-05-27 07:32, André Weidemann wrote:
Hi Gerd,
I managed to pass through a graphics card to a Windows7 VM using your
kraxel.q35 seabios branch
(http://www.kraxel.org/cgit/seabios/log/?h=kraxel.q35).
Here is my setup:
Intel DX58SO
Core i7 920
Radeon HD 6950
Kernel 2.6.35.7
On 27.05.2011 21:40, André Weidemann wrote:
If I am not mistaken then the graphics card needs 2 bars, one with 256MB
and one with 128K. The sound card then needs 1 bar with 16K of PCI memory.
How big is the PCI memory with seabios?
Is there really not enough space to squeeze in those extra 16K?
Hi,
On 27.05.2011 13:09, Jan Kiszka wrote:
On 2011-05-27 07:32, André Weidemann wrote:
Here is my setup:
Intel DX58SO
Core i7 920
Radeon HD 6950
Kernel 2.6.35.7
qemu-kvm git pull from May 26th
One thing that is not working is the pass-through of a second device, a
sound card in my case.
On 27.05.2011 21:50, André Weidemann wrote:
On 27.05.2011 21:40, André Weidemann wrote:
If I am not mistaken then the graphics card needs 2 bars, one with 256MB
and one with 128K. The sound card then needs 1 bar with 16K of PCI
memory.
How big is the PCI memory with seabios?
Is there really
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