Module Name:src
Committed By: skrll
Date: Fri May 31 13:11:41 UTC 2024
Modified Files:
src/sys/arch/riscv/include: mcontext.h
Log Message:
Add more ABI register defines - should have been committed with previous
change.
To generate a diff of this commit:
cvs rdiff -u
Module Name:src
Committed By: skrll
Date: Fri May 31 13:11:41 UTC 2024
Modified Files:
src/sys/arch/riscv/include: mcontext.h
Log Message:
Add more ABI register defines - should have been committed with previous
change.
To generate a diff of this commit:
cvs rdiff -u
Module Name:src
Committed By: skrll
Date: Tue May 28 06:57:03 UTC 2024
Modified Files:
src/sys/arch/riscv/include: netbsd32_machdep.h
Log Message:
Change MIPS to RISC-V.
To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2
Module Name:src
Committed By: skrll
Date: Tue May 28 06:57:03 UTC 2024
Modified Files:
src/sys/arch/riscv/include: netbsd32_machdep.h
Log Message:
Change MIPS to RISC-V.
To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2
Module Name:src
Committed By: riastradh
Date: Tue May 14 15:17:57 UTC 2024
Modified Files:
src/sys/arch/riscv/include: sysreg.h
Log Message:
riscv: No volatile needed on asm to _read_ rounding mode, exceptions.
These instructions can be omitted if the return values are
Module Name:src
Committed By: riastradh
Date: Tue May 14 15:17:57 UTC 2024
Modified Files:
src/sys/arch/riscv/include: sysreg.h
Log Message:
riscv: No volatile needed on asm to _read_ rounding mode, exceptions.
These instructions can be omitted if the return values are
Module Name:src
Committed By: riastradh
Date: Tue May 14 15:16:51 UTC 2024
Modified Files:
src/sys/arch/riscv/include: sysreg.h
Log Message:
riscv: Fix reading and writing frm and fflags.
The FRRM/FSRM and FRFLAGS/FSFLAGS instructions do all the masking and
shifting
Module Name:src
Committed By: riastradh
Date: Tue May 14 15:16:51 UTC 2024
Modified Files:
src/sys/arch/riscv/include: sysreg.h
Log Message:
riscv: Fix reading and writing frm and fflags.
The FRRM/FSRM and FRFLAGS/FSFLAGS instructions do all the masking and
shifting
Module Name:src
Committed By: riastradh
Date: Sun May 12 20:04:12 UTC 2024
Modified Files:
src/sys/arch/riscv/include: fenv.h
Log Message:
riscv fenv.h: Make sure FE_* exception constants have type int.
This may not be formally required by the standard, but the values
Module Name:src
Committed By: riastradh
Date: Sun May 12 20:04:12 UTC 2024
Modified Files:
src/sys/arch/riscv/include: fenv.h
Log Message:
riscv fenv.h: Make sure FE_* exception constants have type int.
This may not be formally required by the standard, but the values
Module Name:src
Committed By: skrll
Date: Fri May 10 08:20:37 UTC 2024
Modified Files:
src/sys/arch/riscv/include: fenv.h
Log Message:
Use __BIT and fix FE_INEXACT
To generate a diff of this commit:
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/riscv/include/fenv.h
Please note
Module Name:src
Committed By: skrll
Date: Fri May 10 08:20:37 UTC 2024
Modified Files:
src/sys/arch/riscv/include: fenv.h
Log Message:
Use __BIT and fix FE_INEXACT
To generate a diff of this commit:
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/riscv/include/fenv.h
Please note
Module Name:src
Committed By: skrll
Date: Sat May 4 12:42:09 UTC 2024
Modified Files:
src/sys/arch/riscv/include: mcontext.h
Log Message:
Fix the __greg_t typedef for riscv32
To generate a diff of this commit:
cvs rdiff -u -r1.7 -r1.8
Module Name:src
Committed By: skrll
Date: Sat May 4 12:42:09 UTC 2024
Modified Files:
src/sys/arch/riscv/include: mcontext.h
Log Message:
Fix the __greg_t typedef for riscv32
To generate a diff of this commit:
cvs rdiff -u -r1.7 -r1.8
Module Name:src
Committed By: skrll
Date: Fri May 3 07:11:14 UTC 2024
Modified Files:
src/sys/arch/riscv/include: ptrace.h
Log Message:
Use the _X_FOO register macros instead of magic numbers.
To generate a diff of this commit:
cvs rdiff -u -r1.5 -r1.6
Module Name:src
Committed By: skrll
Date: Fri May 3 07:11:14 UTC 2024
Modified Files:
src/sys/arch/riscv/include: ptrace.h
Log Message:
Use the _X_FOO register macros instead of magic numbers.
To generate a diff of this commit:
cvs rdiff -u -r1.5 -r1.6
Module Name:src
Committed By: skrll
Date: Mon Dec 25 13:31:01 UTC 2023
Modified Files:
src/sys/arch/riscv/include: sysreg.h
Log Message:
G/C ununsed and incorrect SIE_IM
To generate a diff of this commit:
cvs rdiff -u -r1.29 -r1.30 src/sys/arch/riscv/include/sysreg.h
Module Name:src
Committed By: skrll
Date: Mon Dec 25 13:31:01 UTC 2023
Modified Files:
src/sys/arch/riscv/include: sysreg.h
Log Message:
G/C ununsed and incorrect SIE_IM
To generate a diff of this commit:
cvs rdiff -u -r1.29 -r1.30 src/sys/arch/riscv/include/sysreg.h
Module Name:src
Committed By: skrll
Date: Fri Oct 6 08:48:49 UTC 2023
Modified Files:
src/sys/arch/riscv/include: pmap.h
Log Message:
Not all RISC-V CPUs have ASIDs
To generate a diff of this commit:
cvs rdiff -u -r1.21 -r1.22 src/sys/arch/riscv/include/pmap.h
Please
Module Name:src
Committed By: skrll
Date: Fri Oct 6 08:48:49 UTC 2023
Modified Files:
src/sys/arch/riscv/include: pmap.h
Log Message:
Not all RISC-V CPUs have ASIDs
To generate a diff of this commit:
cvs rdiff -u -r1.21 -r1.22 src/sys/arch/riscv/include/pmap.h
Please
Module Name:src
Committed By: rin
Date: Thu Sep 14 03:25:31 UTC 2023
Modified Files:
src/sys/arch/riscv/include: ptrace.h
Log Message:
riscv: ptrace: Add PTRACE_ILLEGAL_ASM for ATF
All related tests successfully pass.
To generate a diff of this commit:
cvs rdiff -u
Module Name:src
Committed By: rin
Date: Thu Sep 14 03:25:31 UTC 2023
Modified Files:
src/sys/arch/riscv/include: ptrace.h
Log Message:
riscv: ptrace: Add PTRACE_ILLEGAL_ASM for ATF
All related tests successfully pass.
To generate a diff of this commit:
cvs rdiff -u
Module Name:src
Committed By: skrll
Date: Sat Sep 2 09:27:09 UTC 2023
Modified Files:
src/sys/arch/riscv/include: db_machdep.h
Log Message:
Fix a comment and enable RISC-V ddb mach commands
To generate a diff of this commit:
cvs rdiff -u -r1.8 -r1.9
Module Name:src
Committed By: skrll
Date: Sat Sep 2 09:27:09 UTC 2023
Modified Files:
src/sys/arch/riscv/include: db_machdep.h
Log Message:
Fix a comment and enable RISC-V ddb mach commands
To generate a diff of this commit:
cvs rdiff -u -r1.8 -r1.9
Module Name:src
Committed By: rin
Date: Thu Aug 24 05:40:08 UTC 2023
Modified Files:
src/sys/arch/riscv/include: ptrace.h
Log Message:
riscv: Add PTRACE_BREAKPOINT and friends for ATF
Since its size must be determined a priori, explicitly use
c.ebreak for sure.
Now,
Module Name:src
Committed By: rin
Date: Thu Aug 24 05:40:08 UTC 2023
Modified Files:
src/sys/arch/riscv/include: ptrace.h
Log Message:
riscv: Add PTRACE_BREAKPOINT and friends for ATF
Since its size must be determined a priori, explicitly use
c.ebreak for sure.
Now,
Module Name:src
Committed By: skrll
Date: Sat Aug 12 07:48:12 UTC 2023
Modified Files:
src/sys/arch/riscv/include: pmap.h
Log Message:
risc-v: Use 'onproc' for 2nd arg of pmap_md_page_syncicache
Match other definitions of pmap_md_page_syncicache argument naming by
Module Name:src
Committed By: skrll
Date: Sat Aug 12 07:48:12 UTC 2023
Modified Files:
src/sys/arch/riscv/include: pmap.h
Log Message:
risc-v: Use 'onproc' for 2nd arg of pmap_md_page_syncicache
Match other definitions of pmap_md_page_syncicache argument naming by
Module Name:src
Committed By: skrll
Date: Sat Jul 29 06:59:47 UTC 2023
Modified Files:
src/sys/arch/riscv/include: cpu.h
Log Message:
Slight reformatting. NFCI.
To generate a diff of this commit:
cvs rdiff -u -r1.12 -r1.13 src/sys/arch/riscv/include/cpu.h
Please note
Module Name:src
Committed By: skrll
Date: Sat Jul 29 06:59:47 UTC 2023
Modified Files:
src/sys/arch/riscv/include: cpu.h
Log Message:
Slight reformatting. NFCI.
To generate a diff of this commit:
cvs rdiff -u -r1.12 -r1.13 src/sys/arch/riscv/include/cpu.h
Please note
Module Name:src
Committed By: riastradh
Date: Tue Jul 4 01:02:50 UTC 2023
Modified Files:
src/sys/arch/riscv/include: int_const.h
Log Message:
riscv: Fix (U)INT64_C suffix to match gcc's built-in idea of types.
XXX pullup-10
To generate a diff of this commit:
cvs
Module Name:src
Committed By: riastradh
Date: Tue Jul 4 01:02:50 UTC 2023
Modified Files:
src/sys/arch/riscv/include: int_const.h
Log Message:
riscv: Fix (U)INT64_C suffix to match gcc's built-in idea of types.
XXX pullup-10
To generate a diff of this commit:
cvs
Module Name:src
Committed By: skrll
Date: Fri Jun 23 12:11:22 UTC 2023
Modified Files:
src/sys/arch/riscv/include: frame.h
Log Message:
Pad the trapframe so it's a multiple of 16 bytes so that when a trapframe
is created on the stack SP remains 16-byte aligned as per the
Module Name:src
Committed By: skrll
Date: Fri Jun 23 12:11:22 UTC 2023
Modified Files:
src/sys/arch/riscv/include: frame.h
Log Message:
Pad the trapframe so it's a multiple of 16 bytes so that when a trapframe
is created on the stack SP remains 16-byte aligned as per the
Module Name:src
Committed By: skrll
Date: Thu May 25 06:17:18 UTC 2023
Modified Files:
src/sys/arch/riscv/include: cpu.h
Log Message:
Fix CLKF_INTR so that not all time is shown as being spent in interrupts.
To generate a diff of this commit:
cvs rdiff -u -r1.10 -r1.11
Module Name:src
Committed By: skrll
Date: Thu May 25 06:17:18 UTC 2023
Modified Files:
src/sys/arch/riscv/include: cpu.h
Log Message:
Fix CLKF_INTR so that not all time is shown as being spent in interrupts.
To generate a diff of this commit:
cvs rdiff -u -r1.10 -r1.11
Module Name:src
Committed By: skrll
Date: Mon May 8 20:51:53 UTC 2023
Modified Files:
src/sys/arch/riscv/include: proc.h
Log Message:
Don't expose vaddr_t or register_t to userland. The gdb configure script
needs this so it can detect struct lwp correctly.
To generate
Module Name:src
Committed By: skrll
Date: Mon May 8 20:51:53 UTC 2023
Modified Files:
src/sys/arch/riscv/include: proc.h
Log Message:
Don't expose vaddr_t or register_t to userland. The gdb configure script
needs this so it can detect struct lwp correctly.
To generate
Module Name:src
Committed By: skrll
Date: Mon May 8 08:07:36 UTC 2023
Modified Files:
src/sys/arch/riscv/include: pmap.h
Log Message:
Remove some #if 0'ed code
To generate a diff of this commit:
cvs rdiff -u -r1.16 -r1.17 src/sys/arch/riscv/include/pmap.h
Please note
Module Name:src
Committed By: skrll
Date: Mon May 8 08:07:36 UTC 2023
Modified Files:
src/sys/arch/riscv/include: pmap.h
Log Message:
Remove some #if 0'ed code
To generate a diff of this commit:
cvs rdiff -u -r1.16 -r1.17 src/sys/arch/riscv/include/pmap.h
Please note
Module Name:src
Committed By: skrll
Date: Mon May 8 07:56:08 UTC 2023
Modified Files:
src/sys/arch/riscv/include: pmap.h
Log Message:
KNF
To generate a diff of this commit:
cvs rdiff -u -r1.15 -r1.16 src/sys/arch/riscv/include/pmap.h
Please note that diffs are not
Module Name:src
Committed By: skrll
Date: Mon May 8 07:56:08 UTC 2023
Modified Files:
src/sys/arch/riscv/include: pmap.h
Log Message:
KNF
To generate a diff of this commit:
cvs rdiff -u -r1.15 -r1.16 src/sys/arch/riscv/include/pmap.h
Please note that diffs are not
Module Name:src
Committed By: skrll
Date: Sat Apr 22 10:03:53 UTC 2023
Modified Files:
src/sys/arch/riscv/include: pte.h
Log Message:
G/C pte_index
To generate a diff of this commit:
cvs rdiff -u -r1.11 -r1.12 src/sys/arch/riscv/include/pte.h
Please note that diffs are
Module Name:src
Committed By: skrll
Date: Sat Apr 22 10:03:53 UTC 2023
Modified Files:
src/sys/arch/riscv/include: pte.h
Log Message:
G/C pte_index
To generate a diff of this commit:
cvs rdiff -u -r1.11 -r1.12 src/sys/arch/riscv/include/pte.h
Please note that diffs are
Module Name:src
Committed By: skrll
Date: Tue Dec 13 22:25:08 UTC 2022
Modified Files:
src/sys/arch/riscv/include: reg.h
Log Message:
KNF
To generate a diff of this commit:
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/riscv/include/reg.h
Please note that diffs are not public
Module Name:src
Committed By: skrll
Date: Tue Dec 13 22:25:08 UTC 2022
Modified Files:
src/sys/arch/riscv/include: reg.h
Log Message:
KNF
To generate a diff of this commit:
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/riscv/include/reg.h
Please note that diffs are not public
Module Name:src
Committed By: skrll
Date: Sat Dec 3 11:09:59 UTC 2022
Modified Files:
src/sys/arch/riscv/include: sysreg.h
Log Message:
leading whitespace... oops
To generate a diff of this commit:
cvs rdiff -u -r1.27 -r1.28 src/sys/arch/riscv/include/sysreg.h
Please
Module Name:src
Committed By: skrll
Date: Sat Dec 3 11:09:59 UTC 2022
Modified Files:
src/sys/arch/riscv/include: sysreg.h
Log Message:
leading whitespace... oops
To generate a diff of this commit:
cvs rdiff -u -r1.27 -r1.28 src/sys/arch/riscv/include/sysreg.h
Please
Module Name:src
Committed By: skrll
Date: Sat Dec 3 08:54:39 UTC 2022
Modified Files:
src/sys/arch/riscv/include: elf_machdep.h
Log Message:
Correct some pre-existing relocations and add some new ones.
To generate a diff of this commit:
cvs rdiff -u -r1.8 -r1.9
Module Name:src
Committed By: skrll
Date: Sat Dec 3 08:54:39 UTC 2022
Modified Files:
src/sys/arch/riscv/include: elf_machdep.h
Log Message:
Correct some pre-existing relocations and add some new ones.
To generate a diff of this commit:
cvs rdiff -u -r1.8 -r1.9
Module Name:src
Committed By: skrll
Date: Sat Nov 19 12:16:03 UTC 2022
Modified Files:
src/sys/arch/riscv/include: bus_defs.h bus_funcs.h
Log Message:
Fix some types
To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/riscv/include/bus_defs.h \
Module Name:src
Committed By: skrll
Date: Sat Nov 19 12:16:03 UTC 2022
Modified Files:
src/sys/arch/riscv/include: bus_defs.h bus_funcs.h
Log Message:
Fix some types
To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/riscv/include/bus_defs.h \
Module Name:src
Committed By: skrll
Date: Fri Nov 18 06:53:06 UTC 2022
Modified Files:
src/sys/arch/riscv/include: sysreg.h
Log Message:
Fix SR_WPRI.
Tweak csr_cycle_read and csr_asid_write for code style, and add some
KNF whitespace.
To generate a diff of this commit:
Module Name:src
Committed By: skrll
Date: Fri Nov 18 06:53:06 UTC 2022
Modified Files:
src/sys/arch/riscv/include: sysreg.h
Log Message:
Fix SR_WPRI.
Tweak csr_cycle_read and csr_asid_write for code style, and add some
KNF whitespace.
To generate a diff of this commit:
Module Name:src
Committed By: simonb
Date: Thu Nov 17 13:10:43 UTC 2022
Modified Files:
src/sys/arch/riscv/include: sysreg.h
Log Message:
Document lots of bits.
Remove bits no longer in the RISC-V supervisor spec.
Update defines for the user-mode sstatus value.
To
Module Name:src
Committed By: simonb
Date: Thu Nov 17 13:10:43 UTC 2022
Modified Files:
src/sys/arch/riscv/include: sysreg.h
Log Message:
Document lots of bits.
Remove bits no longer in the RISC-V supervisor spec.
Update defines for the user-mode sstatus value.
To
Module Name:src
Committed By: simonb
Date: Thu Nov 17 09:50:23 UTC 2022
Modified Files:
src/sys/arch/riscv/include: cpu.h
Log Message:
Use better types and struct member names in the clockframe.
Avoid a magic number in CLKF_USERMODE().
To generate a diff of this commit:
Module Name:src
Committed By: simonb
Date: Thu Nov 17 09:50:23 UTC 2022
Modified Files:
src/sys/arch/riscv/include: cpu.h
Log Message:
Use better types and struct member names in the clockframe.
Avoid a magic number in CLKF_USERMODE().
To generate a diff of this commit:
Module Name:src
Committed By: skrll
Date: Sun Nov 13 08:13:55 UTC 2022
Modified Files:
src/sys/arch/riscv/include: sysreg.h
Log Message:
Comment fix
To generate a diff of this commit:
cvs rdiff -u -r1.23 -r1.24 src/sys/arch/riscv/include/sysreg.h
Please note that diffs
Module Name:src
Committed By: skrll
Date: Sun Nov 13 08:13:55 UTC 2022
Modified Files:
src/sys/arch/riscv/include: sysreg.h
Log Message:
Comment fix
To generate a diff of this commit:
cvs rdiff -u -r1.23 -r1.24 src/sys/arch/riscv/include/sysreg.h
Please note that diffs
Module Name:src
Committed By: skrll
Date: Sat Nov 12 07:34:18 UTC 2022
Modified Files:
src/sys/arch/riscv/include: pte.h
Log Message:
Note some SV39 PTE bits defined in extensions.
Fix pte_nv_entry for the kernel.
Fix pte_pde_ptpage. PTE.{X,W,R} must be zero for pointer
Module Name:src
Committed By: skrll
Date: Sat Nov 12 07:34:18 UTC 2022
Modified Files:
src/sys/arch/riscv/include: pte.h
Log Message:
Note some SV39 PTE bits defined in extensions.
Fix pte_nv_entry for the kernel.
Fix pte_pde_ptpage. PTE.{X,W,R} must be zero for pointer
Module Name:src
Committed By: skrll
Date: Sat Nov 12 07:05:41 UTC 2022
Modified Files:
src/sys/arch/riscv/include: sysreg.h
Log Message:
Use uintptr_t consistently rather than register_t
To generate a diff of this commit:
cvs rdiff -u -r1.22 -r1.23
Module Name:src
Committed By: skrll
Date: Sat Nov 12 07:05:41 UTC 2022
Modified Files:
src/sys/arch/riscv/include: sysreg.h
Log Message:
Use uintptr_t consistently rather than register_t
To generate a diff of this commit:
cvs rdiff -u -r1.22 -r1.23
Module Name:src
Committed By: simonb
Date: Fri Nov 11 01:18:32 UTC 2022
Modified Files:
src/sys/arch/riscv/include: sysreg.h
Log Message:
The supervisor status register is the native word width, not fixed
at 32 bits.
To generate a diff of this commit:
cvs rdiff -u
Module Name:src
Committed By: simonb
Date: Fri Nov 11 01:18:32 UTC 2022
Modified Files:
src/sys/arch/riscv/include: sysreg.h
Log Message:
The supervisor status register is the native word width, not fixed
at 32 bits.
To generate a diff of this commit:
cvs rdiff -u
Module Name:src
Committed By: simonb
Date: Tue Nov 8 13:47:09 UTC 2022
Modified Files:
src/sys/arch/riscv/include: sysreg.h
Log Message:
Parentheses police.
To generate a diff of this commit:
cvs rdiff -u -r1.20 -r1.21 src/sys/arch/riscv/include/sysreg.h
Please note
Module Name:src
Committed By: simonb
Date: Tue Nov 8 13:47:09 UTC 2022
Modified Files:
src/sys/arch/riscv/include: sysreg.h
Log Message:
Parentheses police.
To generate a diff of this commit:
cvs rdiff -u -r1.20 -r1.21 src/sys/arch/riscv/include/sysreg.h
Please note
Module Name:src
Committed By: simonb
Date: Tue Nov 8 13:35:32 UTC 2022
Modified Files:
src/sys/arch/riscv/include: sysreg.h
Log Message:
Add cause register trap types, and some macros to access cause register
fields.
To generate a diff of this commit:
cvs rdiff -u
Module Name:src
Committed By: simonb
Date: Tue Nov 8 13:35:32 UTC 2022
Modified Files:
src/sys/arch/riscv/include: sysreg.h
Log Message:
Add cause register trap types, and some macros to access cause register
fields.
To generate a diff of this commit:
cvs rdiff -u
Module Name:src
Committed By: simonb
Date: Tue Nov 8 13:34:18 UTC 2022
Modified Files:
src/sys/arch/riscv/include: types.h
Log Message:
Add a #define for XLEN, the RISC-V native base integer ISA width.
To generate a diff of this commit:
cvs rdiff -u -r1.14 -r1.15
Module Name:src
Committed By: simonb
Date: Tue Nov 8 13:34:18 UTC 2022
Modified Files:
src/sys/arch/riscv/include: types.h
Log Message:
Add a #define for XLEN, the RISC-V native base integer ISA width.
To generate a diff of this commit:
cvs rdiff -u -r1.14 -r1.15
Module Name:src
Committed By: skrll
Date: Tue Nov 8 12:48:28 UTC 2022
Modified Files:
src/sys/arch/riscv/include: sysreg.h
Log Message:
whitepsace nit
To generate a diff of this commit:
cvs rdiff -u -r1.18 -r1.19 src/sys/arch/riscv/include/sysreg.h
Please note that
Module Name:src
Committed By: skrll
Date: Tue Nov 8 12:48:28 UTC 2022
Modified Files:
src/sys/arch/riscv/include: sysreg.h
Log Message:
whitepsace nit
To generate a diff of this commit:
cvs rdiff -u -r1.18 -r1.19 src/sys/arch/riscv/include/sysreg.h
Please note that
Module Name:src
Committed By: skrll
Date: Thu Oct 20 07:18:11 UTC 2022
Modified Files:
src/sys/arch/riscv/include: pmap.h
Log Message:
Add the "memory" clobber in two places that it's needed.
To generate a diff of this commit:
cvs rdiff -u -r1.12 -r1.13
Module Name:src
Committed By: skrll
Date: Thu Oct 20 07:18:11 UTC 2022
Modified Files:
src/sys/arch/riscv/include: pmap.h
Log Message:
Add the "memory" clobber in two places that it's needed.
To generate a diff of this commit:
cvs rdiff -u -r1.12 -r1.13
Module Name:src
Committed By: skrll
Date: Tue Oct 18 07:07:51 UTC 2022
Modified Files:
src/sys/arch/riscv/include: types.h
Log Message:
VSXLEN=64 supports 16-bit ASID space so change tlb_asid_t to be big
enough. Spotted by Simon.
To generate a diff of this commit:
cvs
Module Name:src
Committed By: skrll
Date: Tue Oct 18 07:07:51 UTC 2022
Modified Files:
src/sys/arch/riscv/include: types.h
Log Message:
VSXLEN=64 supports 16-bit ASID space so change tlb_asid_t to be big
enough. Spotted by Simon.
To generate a diff of this commit:
cvs
Module Name:src
Committed By: skrll
Date: Tue Oct 18 06:44:43 UTC 2022
Modified Files:
src/sys/arch/riscv/include: pte.h
Log Message:
Some fixes from Simon.
To generate a diff of this commit:
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/riscv/include/pte.h
Please note that
Module Name:src
Committed By: skrll
Date: Tue Oct 18 06:44:43 UTC 2022
Modified Files:
src/sys/arch/riscv/include: pte.h
Log Message:
Some fixes from Simon.
To generate a diff of this commit:
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/riscv/include/pte.h
Please note that
Module Name:src
Committed By: skrll
Date: Tue Oct 18 04:39:38 UTC 2022
Modified Files:
src/sys/arch/riscv/include: pmap.h
Log Message:
Correct XSEGSHIFT for RV32 case
To generate a diff of this commit:
cvs rdiff -u -r1.11 -r1.12 src/sys/arch/riscv/include/pmap.h
Please
Module Name:src
Committed By: skrll
Date: Tue Oct 18 04:39:38 UTC 2022
Modified Files:
src/sys/arch/riscv/include: pmap.h
Log Message:
Correct XSEGSHIFT for RV32 case
To generate a diff of this commit:
cvs rdiff -u -r1.11 -r1.12 src/sys/arch/riscv/include/pmap.h
Please
Module Name:src
Committed By: skrll
Date: Sat Oct 15 06:53:49 UTC 2022
Modified Files:
src/sys/arch/riscv/include: sysreg.h
Log Message:
Fix typo in SATP_MODE_SV64
To generate a diff of this commit:
cvs rdiff -u -r1.17 -r1.18 src/sys/arch/riscv/include/sysreg.h
Please
Module Name:src
Committed By: skrll
Date: Sat Oct 15 06:53:49 UTC 2022
Modified Files:
src/sys/arch/riscv/include: sysreg.h
Log Message:
Fix typo in SATP_MODE_SV64
To generate a diff of this commit:
cvs rdiff -u -r1.17 -r1.18 src/sys/arch/riscv/include/sysreg.h
Please
Module Name:src
Committed By: simonb
Date: Sat Oct 15 06:52:35 UTC 2022
Modified Files:
src/sys/arch/riscv/include: sysreg.h
Log Message:
Consistency nit: use "__volatile" instead of "volatile" with asm()s.
To generate a diff of this commit:
cvs rdiff -u -r1.16 -r1.17
Module Name:src
Committed By: simonb
Date: Sat Oct 15 06:52:35 UTC 2022
Modified Files:
src/sys/arch/riscv/include: sysreg.h
Log Message:
Consistency nit: use "__volatile" instead of "volatile" with asm()s.
To generate a diff of this commit:
cvs rdiff -u -r1.16 -r1.17
Module Name:src
Committed By: simonb
Date: Sat Oct 15 06:48:31 UTC 2022
Modified Files:
src/sys/arch/riscv/include: sysreg.h
Log Message:
Add SATP modes for bare, SV57 and SV64.
To generate a diff of this commit:
cvs rdiff -u -r1.15 -r1.16
Module Name:src
Committed By: simonb
Date: Sat Oct 15 06:48:31 UTC 2022
Modified Files:
src/sys/arch/riscv/include: sysreg.h
Log Message:
Add SATP modes for bare, SV57 and SV64.
To generate a diff of this commit:
cvs rdiff -u -r1.15 -r1.16
Module Name:src
Committed By: simonb
Date: Sat Oct 15 06:46:41 UTC 2022
Modified Files:
src/sys/arch/riscv/include: cpu_counter.h
Log Message:
Use __volatile so the compiler doesn't optimise out successive calls
to cpu_counter().
Add a 64-bit cycle counter on _LP64.
To
Module Name:src
Committed By: simonb
Date: Sat Oct 15 06:46:41 UTC 2022
Modified Files:
src/sys/arch/riscv/include: cpu_counter.h
Log Message:
Use __volatile so the compiler doesn't optimise out successive calls
to cpu_counter().
Add a 64-bit cycle counter on _LP64.
To
Module Name:src
Committed By: skrll
Date: Sat Oct 15 06:07:04 UTC 2022
Modified Files:
src/sys/arch/riscv/include: vmparam.h
Log Message:
Update a comment
To generate a diff of this commit:
cvs rdiff -u -r1.11 -r1.12 src/sys/arch/riscv/include/vmparam.h
Please note
Module Name:src
Committed By: skrll
Date: Sat Oct 15 06:07:04 UTC 2022
Modified Files:
src/sys/arch/riscv/include: vmparam.h
Log Message:
Update a comment
To generate a diff of this commit:
cvs rdiff -u -r1.11 -r1.12 src/sys/arch/riscv/include/vmparam.h
Please note
Module Name:src
Committed By: simonb
Date: Wed Oct 12 07:53:15 UTC 2022
Modified Files:
src/sys/arch/riscv/include: vmparam.h
Log Message:
Set RISCV_DIRECTMAP_SIZE to 2^64-PAGESIZE, since 2^64 is effectively 0
for a 64bit constant.
Bump VM_PHYSSEG_MAX from 1 to 16.
To
Module Name:src
Committed By: simonb
Date: Wed Oct 12 07:53:15 UTC 2022
Modified Files:
src/sys/arch/riscv/include: vmparam.h
Log Message:
Set RISCV_DIRECTMAP_SIZE to 2^64-PAGESIZE, since 2^64 is effectively 0
for a 64bit constant.
Bump VM_PHYSSEG_MAX from 1 to 16.
To
Module Name:src
Committed By: simonb
Date: Wed Oct 12 07:50:57 UTC 2022
Modified Files:
src/sys/arch/riscv/include: reg.h
Log Message:
Fix a tyop regname in a comment.
To generate a diff of this commit:
cvs rdiff -u -r1.8 -r1.9 src/sys/arch/riscv/include/reg.h
Please
Module Name:src
Committed By: simonb
Date: Wed Oct 12 07:50:57 UTC 2022
Modified Files:
src/sys/arch/riscv/include: reg.h
Log Message:
Fix a tyop regname in a comment.
To generate a diff of this commit:
cvs rdiff -u -r1.8 -r1.9 src/sys/arch/riscv/include/reg.h
Please
Module Name:src
Committed By: simonb
Date: Wed Oct 12 07:50:00 UTC 2022
Modified Files:
src/sys/arch/riscv/include: param.h
Log Message:
NKMEMPAGES_MIN_DEFAULT is in pages not bytes (hint is in the name).
Also set NKMEMPAGES_MAX_UNLIMITED while we're here.
To generate a
Module Name:src
Committed By: simonb
Date: Wed Oct 12 07:50:00 UTC 2022
Modified Files:
src/sys/arch/riscv/include: param.h
Log Message:
NKMEMPAGES_MIN_DEFAULT is in pages not bytes (hint is in the name).
Also set NKMEMPAGES_MAX_UNLIMITED while we're here.
To generate a
Module Name:src
Committed By: skrll
Date: Wed Sep 21 06:34:30 UTC 2022
Modified Files:
src/sys/arch/riscv/include: pte.h
Log Message:
Use c99 types. NFC.
To generate a diff of this commit:
cvs rdiff -u -r1.6 -r1.7 src/sys/arch/riscv/include/pte.h
Please note that diffs
Module Name:src
Committed By: skrll
Date: Wed Sep 21 06:34:30 UTC 2022
Modified Files:
src/sys/arch/riscv/include: pte.h
Log Message:
Use c99 types. NFC.
To generate a diff of this commit:
cvs rdiff -u -r1.6 -r1.7 src/sys/arch/riscv/include/pte.h
Please note that diffs
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