CVS commit: src/sys/arch/arm
Module Name:src
Committed By: jmcneill
Date: Sat Nov 13 01:48:12 UTC 2021
Modified Files:
src/sys/arch/arm/arm: cpufunc.c
src/sys/arch/arm/include: armreg.h
Log Message:
Set ACTLR.SMP=1 on Cortex-A17
To generate a diff of this commit:
cvs rdiff -u -r1.181 -r1.182 src/sys/arch/arm/arm/cpufunc.c
cvs rdiff -u -r1.132 -r1.133 src/sys/arch/arm/include/armreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm/cpufunc.c
diff -u src/sys/arch/arm/arm/cpufunc.c:1.181 src/sys/arch/arm/arm/cpufunc.c:1.182
--- src/sys/arch/arm/arm/cpufunc.c:1.181 Fri Jul 2 07:15:35 2021
+++ src/sys/arch/arm/arm/cpufunc.c Sat Nov 13 01:48:12 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: cpufunc.c,v 1.181 2021/07/02 07:15:35 skrll Exp $ */
+/* $NetBSD: cpufunc.c,v 1.182 2021/11/13 01:48:12 jmcneill Exp $ */
/*
* arm7tdmi support code Copyright (c) 2001 John Fremlin
@@ -49,7 +49,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.181 2021/07/02 07:15:35 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.182 2021/11/13 01:48:12 jmcneill Exp $");
#include "opt_arm_start.h"
#include "opt_compat_netbsd.h"
@@ -3005,12 +3005,9 @@ armv7_setup(char *args)
CORTEXA15_ACTLR_SMP |
CORTEXA15_ACTLR_SDEH |
0;
-#if 0
} else if (CPU_ID_CORTEX_A12_P(lcputype) ||
- CPU_ID_CORTEX_A17_P(lcputype)) {
- actlr_set =
- CORTEXA17_ACTLR_SMP;
-#endif
+ CPU_ID_CORTEX_A17_P(lcputype)) {
+ actlr_set = CORTEXA17_ACTLR_SMP;
} else if (CPU_ID_CORTEX_A53_P(lcputype)) {
} else if (CPU_ID_CORTEX_A57_P(lcputype)) {
} else if (CPU_ID_CORTEX_A72_P(lcputype)) {
Index: src/sys/arch/arm/include/armreg.h
diff -u src/sys/arch/arm/include/armreg.h:1.132 src/sys/arch/arm/include/armreg.h:1.133
--- src/sys/arch/arm/include/armreg.h:1.132 Sun Oct 10 08:36:49 2021
+++ src/sys/arch/arm/include/armreg.h Sat Nov 13 01:48:12 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: armreg.h,v 1.132 2021/10/10 08:36:49 skrll Exp $ */
+/* $NetBSD: armreg.h,v 1.133 2021/11/13 01:48:12 jmcneill Exp $ */
/*
* Copyright (c) 1998, 2001 Ben Harris
@@ -312,6 +312,12 @@
#define CORTEXA15_ACTLR_IOBEU __BIT(15) /* In order issue in Branch Exec Unit */
#define CORTEXA15_ACTLR_SDEH __BIT(31) /* snoop-delayed exclusive handling */
+/* Cortex-A17 Auxiliary Control Register (CP15 register 1, opcode 1) */
+#define CORTEXA17_ACTLR_SMP __BIT(6) /* SMP */
+#define CORTEXA17_ACTLR_ASSE __BIT(3) /* ACE STREX Signaling Enable */
+#define CORTEXA17_ACTLR_L2PF __BIT(2) /* Enable L2 prefetch */
+#define CORTEXA17_ACTLR_L1PF __BIT(1) /* Enable L1 prefetch */
+
/* Marvell Feroceon Extra Features Register (CP15 register 1, opcode2 0) */
#define FC_DCACHE_REPL_LOCK 0x8000 /* Replace DCache Lock */
#define FC_DCACHE_STREAM_EN 0x2000 /* DCache Streaming Switch */
CVS commit: src/sys/arch/arm
Module Name:src Committed By: jmcneill Date: Sat Nov 13 01:48:12 UTC 2021 Modified Files: src/sys/arch/arm/arm: cpufunc.c src/sys/arch/arm/include: armreg.h Log Message: Set ACTLR.SMP=1 on Cortex-A17 To generate a diff of this commit: cvs rdiff -u -r1.181 -r1.182 src/sys/arch/arm/arm/cpufunc.c cvs rdiff -u -r1.132 -r1.133 src/sys/arch/arm/include/armreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/evbarm/conf
Module Name:src Committed By: jmcneill Date: Sat Nov 13 01:29:21 UTC 2021 Modified Files: src/sys/arch/evbarm/conf: GENERIC Log Message: Add rkpwm, rkspi To generate a diff of this commit: cvs rdiff -u -r1.102 -r1.103 src/sys/arch/evbarm/conf/GENERIC Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/evbarm/conf/GENERIC diff -u src/sys/arch/evbarm/conf/GENERIC:1.102 src/sys/arch/evbarm/conf/GENERIC:1.103 --- src/sys/arch/evbarm/conf/GENERIC:1.102 Sat Nov 13 00:34:24 2021 +++ src/sys/arch/evbarm/conf/GENERIC Sat Nov 13 01:29:21 2021 @@ -1,5 +1,5 @@ # -# $NetBSD: GENERIC,v 1.102 2021/11/13 00:34:24 jmcneill Exp $ +# $NetBSD: GENERIC,v 1.103 2021/11/13 01:29:21 jmcneill Exp $ # # GENERIC ARM (aarch32) kernel # @@ -275,6 +275,7 @@ tegrapinmux* at fdt? # NVIDIA Tegra M # PWM controller expwm* at fdt? pass 4 # PWM imxpwm* at fdt? # i.MX PWM +rkpwm* at fdt? pass 3 # Rockchip PWM sunxipwm* at fdt? pass 3 # Allwinner PWM # Backlight @@ -395,6 +396,7 @@ sunxican* at fdt? # A10/A20 CAN contr # SPI imxspi* at fdt? # i.MX SPI +rkspi* at fdt? # Rockchip SPI sun4ispi* at fdt? sun6ispi* at fdt? spi* at spibus?
CVS commit: src/sys/arch/evbarm/conf
Module Name:src Committed By: jmcneill Date: Sat Nov 13 01:29:21 UTC 2021 Modified Files: src/sys/arch/evbarm/conf: GENERIC Log Message: Add rkpwm, rkspi To generate a diff of this commit: cvs rdiff -u -r1.102 -r1.103 src/sys/arch/evbarm/conf/GENERIC Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/rockchip
Module Name:src Committed By: jmcneill Date: Sat Nov 13 01:29:08 UTC 2021 Modified Files: src/sys/arch/arm/rockchip: rk3288_cru.c Log Message: Add pwm and spi clocks To generate a diff of this commit: cvs rdiff -u -r1.3 -r1.4 src/sys/arch/arm/rockchip/rk3288_cru.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/rockchip
Module Name:src Committed By: jmcneill Date: Sat Nov 13 01:29:08 UTC 2021 Modified Files: src/sys/arch/arm/rockchip: rk3288_cru.c Log Message: Add pwm and spi clocks To generate a diff of this commit: cvs rdiff -u -r1.3 -r1.4 src/sys/arch/arm/rockchip/rk3288_cru.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/rockchip/rk3288_cru.c diff -u src/sys/arch/arm/rockchip/rk3288_cru.c:1.3 src/sys/arch/arm/rockchip/rk3288_cru.c:1.4 --- src/sys/arch/arm/rockchip/rk3288_cru.c:1.3 Sat Nov 13 01:07:09 2021 +++ src/sys/arch/arm/rockchip/rk3288_cru.c Sat Nov 13 01:29:08 2021 @@ -1,4 +1,4 @@ -/* $NetBSD: rk3288_cru.c,v 1.3 2021/11/13 01:07:09 jmcneill Exp $ */ +/* $NetBSD: rk3288_cru.c,v 1.4 2021/11/13 01:29:08 jmcneill Exp $ */ /*- * Copyright (c) 2021 Jared McNeill @@ -28,7 +28,7 @@ #include -__KERNEL_RCSID(1, "$NetBSD: rk3288_cru.c,v 1.3 2021/11/13 01:07:09 jmcneill Exp $"); +__KERNEL_RCSID(1, "$NetBSD: rk3288_cru.c,v 1.4 2021/11/13 01:29:08 jmcneill Exp $"); #include #include @@ -240,6 +240,29 @@ static struct rk_cru_clk rk3288_cru_clks __BIT(4), /* gate_mask */ 0), + /* SPI */ + RK_COMPOSITE(RK3288_SCLK_SPI0, "sclk_spi0", mux_2plls_parents, + CLKSEL_CON(25), /* muxdiv_reg */ + __BIT(7), /* mux_mask */ + __BITS(6,0), /* div_mask */ + CLKGATE_CON(2), /* gate_reg */ + __BIT(9), /* gate_mask */ + 0), + RK_COMPOSITE(RK3288_SCLK_SPI1, "sclk_spi1", mux_2plls_parents, + CLKSEL_CON(25), /* muxdiv_reg */ + __BIT(15), /* mux_mask */ + __BITS(14,8), /* div_mask */ + CLKGATE_CON(2), /* gate_reg */ + __BIT(10), /* gate_mask */ + 0), + RK_COMPOSITE(RK3288_SCLK_SPI2, "sclk_spi2", mux_2plls_parents, + CLKSEL_CON(39), /* muxdiv_reg */ + __BIT(7), /* mux_mask */ + __BITS(6,0), /* div_mask */ + CLKGATE_CON(2), /* gate_reg */ + __BIT(11), /* gate_mask */ + 0), + RK_DIV(0, "aclk_cpu_pre", "aclk_cpu_src", CLKSEL_CON(1), __BITS(2,0), 0), RK_DIV(0, "clk_24m", "xin24m", CLKSEL_CON(2), __BITS(12,8), 0), RK_DIV(0, "pclk_pd_alive", "gpll", CLKSEL_CON(33), __BITS(12,8), 0), @@ -260,6 +283,9 @@ static struct rk_cru_clk rk3288_cru_clks RK_GATE(RK3288_SCLK_MAC_TX, "sclk_mac_tx", "mac_clk", CLKGATE_CON(5), 1), RK_GATE(RK3288_SCLK_MACREF, "sclk_macref", "mac_clk", CLKGATE_CON(5), 2), RK_GATE(RK3288_SCLK_MACREF_OUT, "sclk_macref_out", "mac_clk", CLKGATE_CON(5), 3), + RK_GATE(RK3288_PCLK_SPI0, "pclk_spi0", "pclk_peri", CLKGATE_CON(6), 4), + RK_GATE(RK3288_PCLK_SPI1, "pclk_spi1", "pclk_peri", CLKGATE_CON(6), 5), + RK_GATE(RK3288_PCLK_SPI2, "pclk_spi2", "pclk_peri", CLKGATE_CON(6), 6), RK_GATE(RK3288_PCLK_I2C1, "pclk_i2c1", "pclk_peri", CLKGATE_CON(6), 13), RK_GATE(RK3288_PCLK_I2C3, "pclk_i2c3", "pclk_peri", CLKGATE_CON(6), 14), RK_GATE(RK3288_PCLK_I2C4, "pclk_i2c4", "pclk_peri", CLKGATE_CON(6), 15), @@ -279,6 +305,7 @@ static struct rk_cru_clk rk3288_cru_clks RK_GATE(RK3288_ACLK_CRYPTO, "aclk_crypto", "aclk_cpu", CLKGATE_CON(11), 6), RK_GATE(RK3288_HCLK_CRYPTO, "hclk_crypto", "hclk_cpu", CLKGATE_CON(11), 7), RK_GATE(RK3288_PCLK_UART2, "pclk_uart2", "pclk_cpu", CLKGATE_CON(11), 9), + RK_GATE(RK3288_PCLK_RKPWM, "pclk_rkpwm", "pclk_cpu", CLKGATE_CON(11), 11), RK_GATE(RK3288_SCLK_OTGPHY0, "sclk_otgphy0", "xin24m", CLKGATE_CON(13), 4), RK_GATE(RK3288_SCLK_OTGPHY1, "sclk_otgphy1", "xin24m", CLKGATE_CON(13), 5), RK_GATE(RK3288_SCLK_OTGPHY2, "sclk_otgphy2", "xin24m", CLKGATE_CON(13), 6),
CVS commit: src/sys/arch/arm/include
Module Name:src Committed By: simonb Date: Sat Nov 13 01:09:51 UTC 2021 Modified Files: src/sys/arch/arm/include: cputypes.h Log Message: Fix tyop in a comment. To generate a diff of this commit: cvs rdiff -u -r1.15 -r1.16 src/sys/arch/arm/include/cputypes.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/include/cputypes.h diff -u src/sys/arch/arm/include/cputypes.h:1.15 src/sys/arch/arm/include/cputypes.h:1.16 --- src/sys/arch/arm/include/cputypes.h:1.15 Fri Nov 12 06:44:46 2021 +++ src/sys/arch/arm/include/cputypes.h Sat Nov 13 01:09:51 2021 @@ -1,4 +1,4 @@ -/* $NetBSD: cputypes.h,v 1.15 2021/11/12 06:44:46 skrll Exp $ */ +/* $NetBSD: cputypes.h,v 1.16 2021/11/13 01:09:51 simonb Exp $ */ /* * Copyright (c) 1998, 2001 Ben Harris @@ -209,7 +209,7 @@ #define CPU_ID_THUNDERX2RX 0x43000af0 /* - * Chip-specific errata. This defines are intended to be + * Chip-specific errata. These defines are intended to be * booleans used within if statements. When an appropriate * kernel option is disabled, these defines must be defined * as 0 to allow the compiler to remove a dead code thus
CVS commit: src/sys/arch/arm/include
Module Name:src Committed By: simonb Date: Sat Nov 13 01:09:51 UTC 2021 Modified Files: src/sys/arch/arm/include: cputypes.h Log Message: Fix tyop in a comment. To generate a diff of this commit: cvs rdiff -u -r1.15 -r1.16 src/sys/arch/arm/include/cputypes.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/rockchip
Module Name:src
Committed By: jmcneill
Date: Sat Nov 13 01:08:15 UTC 2021
Modified Files:
src/sys/arch/arm/rockchip: rk_i2c.c
Log Message:
Match rockchip,rk3288-i2c
To generate a diff of this commit:
cvs rdiff -u -r1.11 -r1.12 src/sys/arch/arm/rockchip/rk_i2c.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/rockchip/rk_i2c.c
diff -u src/sys/arch/arm/rockchip/rk_i2c.c:1.11 src/sys/arch/arm/rockchip/rk_i2c.c:1.12
--- src/sys/arch/arm/rockchip/rk_i2c.c:1.11 Fri Nov 12 22:02:08 2021
+++ src/sys/arch/arm/rockchip/rk_i2c.c Sat Nov 13 01:08:15 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: rk_i2c.c,v 1.11 2021/11/12 22:02:08 jmcneill Exp $ */
+/* $NetBSD: rk_i2c.c,v 1.12 2021/11/13 01:08:15 jmcneill Exp $ */
/*-
* Copyright (c) 2018 Jared McNeill
@@ -28,7 +28,7 @@
#include
-__KERNEL_RCSID(0, "$NetBSD: rk_i2c.c,v 1.11 2021/11/12 22:02:08 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: rk_i2c.c,v 1.12 2021/11/13 01:08:15 jmcneill Exp $");
#include
#include
@@ -104,9 +104,7 @@ __KERNEL_RCSID(0, "$NetBSD: rk_i2c.c,v 1
#define RKI2C_HAS_PCLK __BIT(0)
static const struct device_compatible_entry compat_data[] = {
-#if notyet
{ .compat = "rockchip,rk3288-i2c", .value = 0 },
-#endif
{ .compat = "rockchip,rk3399-i2c", .value = RKI2C_HAS_PCLK },
DEVICE_COMPAT_EOL
};
CVS commit: src/sys/arch/arm/rockchip
Module Name:src Committed By: jmcneill Date: Sat Nov 13 01:08:15 UTC 2021 Modified Files: src/sys/arch/arm/rockchip: rk_i2c.c Log Message: Match rockchip,rk3288-i2c To generate a diff of this commit: cvs rdiff -u -r1.11 -r1.12 src/sys/arch/arm/rockchip/rk_i2c.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/rockchip
Module Name:src Committed By: jmcneill Date: Sat Nov 13 01:07:09 UTC 2021 Modified Files: src/sys/arch/arm/rockchip: rk3288_cru.c Log Message: Fix width of aclk_cpu_pre divider field To generate a diff of this commit: cvs rdiff -u -r1.2 -r1.3 src/sys/arch/arm/rockchip/rk3288_cru.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/rockchip/rk3288_cru.c diff -u src/sys/arch/arm/rockchip/rk3288_cru.c:1.2 src/sys/arch/arm/rockchip/rk3288_cru.c:1.3 --- src/sys/arch/arm/rockchip/rk3288_cru.c:1.2 Sat Nov 13 00:34:07 2021 +++ src/sys/arch/arm/rockchip/rk3288_cru.c Sat Nov 13 01:07:09 2021 @@ -1,4 +1,4 @@ -/* $NetBSD: rk3288_cru.c,v 1.2 2021/11/13 00:34:07 jmcneill Exp $ */ +/* $NetBSD: rk3288_cru.c,v 1.3 2021/11/13 01:07:09 jmcneill Exp $ */ /*- * Copyright (c) 2021 Jared McNeill @@ -28,7 +28,7 @@ #include -__KERNEL_RCSID(1, "$NetBSD: rk3288_cru.c,v 1.2 2021/11/13 00:34:07 jmcneill Exp $"); +__KERNEL_RCSID(1, "$NetBSD: rk3288_cru.c,v 1.3 2021/11/13 01:07:09 jmcneill Exp $"); #include #include @@ -240,7 +240,7 @@ static struct rk_cru_clk rk3288_cru_clks __BIT(4), /* gate_mask */ 0), - RK_DIV(0, "aclk_cpu_pre", "aclk_cpu_src", CLKSEL_CON(1), __BITS(3,0), 0), + RK_DIV(0, "aclk_cpu_pre", "aclk_cpu_src", CLKSEL_CON(1), __BITS(2,0), 0), RK_DIV(0, "clk_24m", "xin24m", CLKSEL_CON(2), __BITS(12,8), 0), RK_DIV(0, "pclk_pd_alive", "gpll", CLKSEL_CON(33), __BITS(12,8), 0),
CVS commit: src/sys/arch/arm/rockchip
Module Name:src Committed By: jmcneill Date: Sat Nov 13 01:07:09 UTC 2021 Modified Files: src/sys/arch/arm/rockchip: rk3288_cru.c Log Message: Fix width of aclk_cpu_pre divider field To generate a diff of this commit: cvs rdiff -u -r1.2 -r1.3 src/sys/arch/arm/rockchip/rk3288_cru.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/evbarm/conf
Module Name:src Committed By: jmcneill Date: Sat Nov 13 00:34:24 UTC 2021 Modified Files: src/sys/arch/evbarm/conf: GENERIC Log Message: add rkv1crypto To generate a diff of this commit: cvs rdiff -u -r1.101 -r1.102 src/sys/arch/evbarm/conf/GENERIC Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/evbarm/conf/GENERIC diff -u src/sys/arch/evbarm/conf/GENERIC:1.101 src/sys/arch/evbarm/conf/GENERIC:1.102 --- src/sys/arch/evbarm/conf/GENERIC:1.101 Fri Nov 12 22:02:08 2021 +++ src/sys/arch/evbarm/conf/GENERIC Sat Nov 13 00:34:24 2021 @@ -1,5 +1,5 @@ # -# $NetBSD: GENERIC,v 1.101 2021/11/12 22:02:08 jmcneill Exp $ +# $NetBSD: GENERIC,v 1.102 2021/11/13 00:34:24 jmcneill Exp $ # # GENERIC ARM (aarch32) kernel # @@ -408,6 +408,7 @@ m25p* at spi? slave ? bcmrng* at fdt? # Broadcom BCM283x RNG mesonrng* at fdt? # Amlogic Meson RNG tirng* at fdt? # TI RNG +rkv1crypto* at fdt? # Rockchip Crypto v1 sun8icrypto* at fdt? # Allwinner Crypto Engine # Security ID EFUSE
CVS commit: src/sys/arch/evbarm/conf
Module Name:src Committed By: jmcneill Date: Sat Nov 13 00:34:24 UTC 2021 Modified Files: src/sys/arch/evbarm/conf: GENERIC Log Message: add rkv1crypto To generate a diff of this commit: cvs rdiff -u -r1.101 -r1.102 src/sys/arch/evbarm/conf/GENERIC Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/rockchip
Module Name:src Committed By: jmcneill Date: Sat Nov 13 00:34:07 UTC 2021 Modified Files: src/sys/arch/arm/rockchip: rk3288_cru.c Log Message: rk3288: add watchdog and rng clocks To generate a diff of this commit: cvs rdiff -u -r1.1 -r1.2 src/sys/arch/arm/rockchip/rk3288_cru.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/rockchip/rk3288_cru.c diff -u src/sys/arch/arm/rockchip/rk3288_cru.c:1.1 src/sys/arch/arm/rockchip/rk3288_cru.c:1.2 --- src/sys/arch/arm/rockchip/rk3288_cru.c:1.1 Fri Nov 12 22:02:08 2021 +++ src/sys/arch/arm/rockchip/rk3288_cru.c Sat Nov 13 00:34:07 2021 @@ -1,4 +1,4 @@ -/* $NetBSD: rk3288_cru.c,v 1.1 2021/11/12 22:02:08 jmcneill Exp $ */ +/* $NetBSD: rk3288_cru.c,v 1.2 2021/11/13 00:34:07 jmcneill Exp $ */ /*- * Copyright (c) 2021 Jared McNeill @@ -28,7 +28,7 @@ #include -__KERNEL_RCSID(1, "$NetBSD: rk3288_cru.c,v 1.1 2021/11/12 22:02:08 jmcneill Exp $"); +__KERNEL_RCSID(1, "$NetBSD: rk3288_cru.c,v 1.2 2021/11/13 00:34:07 jmcneill Exp $"); #include #include @@ -102,6 +102,12 @@ static struct rk_cru_clk rk3288_cru_clks __BIT(15), /* mux_mask */ __BITS(7,3), /* div_mask */ 0), + RK_COMPOSITE_NOMUX(RK3288_ACLK_CPU, "aclk_cpu", "aclk_cpu_pre", + CLKSEL_CON(1), /* div_reg */ + __BITS(9,8), /* div_mask */ + CLKGATE_CON(0), /* gate_reg */ + __BIT(4), /* gate_mask */ + 0), RK_COMPOSITE_NOMUX(RK3288_PCLK_CPU, "pclk_cpu", "aclk_cpu_pre", CLKSEL_CON(1), /* div_reg */ __BITS(14,12), /* div_mask */ @@ -226,6 +232,14 @@ static struct rk_cru_clk rk3288_cru_clks __BIT(5), /* gate_mask */ 0), + /* Crypto */ + RK_COMPOSITE_NOMUX(RK3288_SCLK_CRYPTO, "crypto", "aclk_cpu_pre", + CLKSEL_CON(26), /* div_reg */ + __BITS(7,6), /* div_mask */ + CLKGATE_CON(5), /* gate_reg */ + __BIT(4), /* gate_mask */ + 0), + RK_DIV(0, "aclk_cpu_pre", "aclk_cpu_src", CLKSEL_CON(1), __BITS(3,0), 0), RK_DIV(0, "clk_24m", "xin24m", CLKSEL_CON(2), __BITS(12,8), 0), RK_DIV(0, "pclk_pd_alive", "gpll", CLKSEL_CON(33), __BITS(12,8), 0), @@ -238,6 +252,7 @@ static struct rk_cru_clk rk3288_cru_clks RK_MUX(0, "uart_src", mux_2plls_parents, CLKSEL_CON(15), __BIT(15)), RK_MUX(RK3288_SCLK_MAC, "mac_clk", mac_parents, CLKSEL_CON(21), __BIT(4)), + RK_GATE(RK3288_ACLK_CPU, "aclk_cpu", "aclk_cpu_pre", CLKGATE_CON(0), 3), RK_GATE(0, "gpll_aclk_cpu", "gpll", CLKGATE_CON(0), 10), RK_GATE(0, "cpll_aclk_cpu", "cpll", CLKGATE_CON(0), 11), RK_GATE(RK3288_ACLK_PERI, "aclk_peri", "aclk_peri_src", CLKGATE_CON(2), 1), @@ -260,6 +275,9 @@ static struct rk_cru_clk rk3288_cru_clks RK_GATE(RK3288_HCLK_EMMC, "hclk_emmc", "hclk_peri", CLKGATE_CON(8), 6), RK_GATE(RK3288_PCLK_I2C0, "pclk_i2c0", "pclk_cpu", CLKGATE_CON(10), 2), RK_GATE(RK3288_PCLK_I2C2, "pclk_i2c2", "pclk_cpu", CLKGATE_CON(10), 3), + RK_GATE(RK3288_ACLK_DMAC1, "aclk_dmac1", "aclk_cpu", CLKGATE_CON(10), 12), + RK_GATE(RK3288_ACLK_CRYPTO, "aclk_crypto", "aclk_cpu", CLKGATE_CON(11), 6), + RK_GATE(RK3288_HCLK_CRYPTO, "hclk_crypto", "hclk_cpu", CLKGATE_CON(11), 7), RK_GATE(RK3288_PCLK_UART2, "pclk_uart2", "pclk_cpu", CLKGATE_CON(11), 9), RK_GATE(RK3288_SCLK_OTGPHY0, "sclk_otgphy0", "xin24m", CLKGATE_CON(13), 4), RK_GATE(RK3288_SCLK_OTGPHY1, "sclk_otgphy1", "xin24m", CLKGATE_CON(13), 5), @@ -273,6 +291,7 @@ static struct rk_cru_clk rk3288_cru_clks RK_GATE(RK3288_PCLK_GPIO7, "pclk_gpio7", "pclk_pd_alive", CLKGATE_CON(14), 7), RK_GATE(RK3288_PCLK_GPIO8, "pclk_gpio8", "pclk_pd_alive", CLKGATE_CON(14), 8), RK_GATE(RK3288_PCLK_GPIO0, "pclk_gpio0", "pclk_pd_pmu", CLKGATE_CON(17), 4), + RK_SECURE_GATE(RK3288_PCLK_WDT, "pclk_wdt", "pclk_pd_alive"), }; static int
CVS commit: src/sys/arch/arm/rockchip
Module Name:src Committed By: jmcneill Date: Sat Nov 13 00:34:07 UTC 2021 Modified Files: src/sys/arch/arm/rockchip: rk3288_cru.c Log Message: rk3288: add watchdog and rng clocks To generate a diff of this commit: cvs rdiff -u -r1.1 -r1.2 src/sys/arch/arm/rockchip/rk3288_cru.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/arm32
Module Name:src
Committed By: jmcneill
Date: Sat Nov 13 00:13:17 UTC 2021
Modified Files:
src/sys/arch/arm/arm32: arm32_machdep.c
Log Message:
Support 'boot -1' on arm
To generate a diff of this commit:
cvs rdiff -u -r1.141 -r1.142 src/sys/arch/arm/arm32/arm32_machdep.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm32/arm32_machdep.c
diff -u src/sys/arch/arm/arm32/arm32_machdep.c:1.141 src/sys/arch/arm/arm32/arm32_machdep.c:1.142
--- src/sys/arch/arm/arm32/arm32_machdep.c:1.141 Sun Oct 31 16:23:47 2021
+++ src/sys/arch/arm/arm32/arm32_machdep.c Sat Nov 13 00:13:17 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: arm32_machdep.c,v 1.141 2021/10/31 16:23:47 skrll Exp $ */
+/* $NetBSD: arm32_machdep.c,v 1.142 2021/11/13 00:13:17 jmcneill Exp $ */
/*
* Copyright (c) 1994-1998 Mark Brinicombe.
@@ -42,7 +42,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: arm32_machdep.c,v 1.141 2021/10/31 16:23:47 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: arm32_machdep.c,v 1.142 2021/11/13 00:13:17 jmcneill Exp $");
#include "opt_arm_debug.h"
#include "opt_arm_start.h"
@@ -558,6 +558,9 @@ parse_mi_bootargs(char *args)
{
int integer;
+ if (get_bootconf_option(args, "-1", BOOTOPT_TYPE_BOOLEAN, ))
+ if (integer)
+ boothowto |= RB_MD1;
if (get_bootconf_option(args, "single", BOOTOPT_TYPE_BOOLEAN, )
|| get_bootconf_option(args, "-s", BOOTOPT_TYPE_BOOLEAN, ))
if (integer)
CVS commit: src/sys/arch/arm/arm32
Module Name:src Committed By: jmcneill Date: Sat Nov 13 00:13:17 UTC 2021 Modified Files: src/sys/arch/arm/arm32: arm32_machdep.c Log Message: Support 'boot -1' on arm To generate a diff of this commit: cvs rdiff -u -r1.141 -r1.142 src/sys/arch/arm/arm32/arm32_machdep.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/rockchip
Module Name:src
Committed By: jmcneill
Date: Fri Nov 12 22:53:21 UTC 2021
Modified Files:
src/sys/arch/arm/rockchip: rk3288_iomux.c
Log Message:
Fix register accesses to PMU registers. Unlike the GRF ones, a RMW cycle
is required to update settings here.
To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/arm/rockchip/rk3288_iomux.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/rockchip/rk3288_iomux.c
diff -u src/sys/arch/arm/rockchip/rk3288_iomux.c:1.1 src/sys/arch/arm/rockchip/rk3288_iomux.c:1.2
--- src/sys/arch/arm/rockchip/rk3288_iomux.c:1.1 Fri Nov 12 22:02:08 2021
+++ src/sys/arch/arm/rockchip/rk3288_iomux.c Fri Nov 12 22:53:20 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: rk3288_iomux.c,v 1.1 2021/11/12 22:02:08 jmcneill Exp $ */
+/* $NetBSD: rk3288_iomux.c,v 1.2 2021/11/12 22:53:20 jmcneill Exp $ */
/*-
* Copyright (c) 2018 Jared McNeill
@@ -27,7 +27,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: rk3288_iomux.c,v 1.1 2021/11/12 22:02:08 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: rk3288_iomux.c,v 1.2 2021/11/12 22:53:20 jmcneill Exp $");
#include
#include
@@ -84,6 +84,8 @@ struct rk3288_iomux_reg {
syscon_read_4((reg)->syscon, (off))
#define WR4(reg, off, val) \
syscon_write_4((reg)->syscon, (off), (val))
+#define ISPMU(sc, reg) \
+ ((reg)->syscon == (sc)->sc_pmu)
static int rk3288_iomux_match(device_t, cfdata_t, void *);
static void rk3288_iomux_attach(device_t, device_t, void *);
@@ -178,17 +180,13 @@ rk3288_iomux_set_bias(struct rk3288_iomu
return;
}
- val = GPIO_P_CTL_MASK << (reg->pull_bit + 16);
+ if (ISPMU(sc, reg)) {
+ val = RD4(reg, reg->pull_reg);
+ val &= ~(GPIO_P_CTL_MASK << reg->pull_bit);
+ } else {
+ val = GPIO_P_CTL_MASK << (reg->pull_bit + 16);
+ }
val |= p << reg->pull_bit;
-
-#ifdef RK3288_IOMUX_DEBUG
- const uint32_t oval = RD4(reg, reg->pull_reg);
- printf("%s: wr %#x -> %#x (%#x)\n", __func__,
- oval & (GPIO_P_CTL_MASK << reg->pull_bit),
- val & 0x,
- GPIO_P_CTL_MASK << reg->pull_bit);
-#endif
-
WR4(reg, reg->pull_reg, val);
}
@@ -216,8 +214,13 @@ rk3288_iomux_set_drive_strength(struct r
return;
}
- val = GPIO_E_CTL_MASK << (reg->drv_bit + 16);
- val |= e << reg->drv_bit;
+ if (ISPMU(sc, reg)) {
+ val = RD4(reg, reg->drv_reg);
+ val &= ~(GPIO_E_CTL_MASK << reg->drv_bit);
+ } else {
+ val = GPIO_E_CTL_MASK << (reg->drv_bit + 16);
+ }
+ val = e << reg->drv_bit;
WR4(reg, reg->drv_reg, val);
}
@@ -229,9 +232,14 @@ rk3288_iomux_set_mux(struct rk3288_iomux
KASSERT(reg->mux_reg != -1);
- val = ((reg->flags & IOMUX_4BIT) ? 0xf : 0x3) << (reg->mux_bit + 16);
+ const uint32_t mask = (reg->flags & IOMUX_4BIT) ? 0xf : 0x3;
+ if (ISPMU(sc, reg)) {
+ val = RD4(reg, reg->mux_reg);
+ val &= ~(mask << reg->mux_bit);
+ } else {
+ val = mask << (reg->mux_bit + 16);
+ }
val |= mux << reg->mux_bit;
-
WR4(reg, reg->mux_reg, val);
}
@@ -254,14 +262,6 @@ rk3288_iomux_config(struct rk3288_iomux_
printf(" bias %d drv %d mux %u\n", bias, drv, mux);
#endif
- /* XXX
- * ASUS Tinkerboard goes nuts if we update any PMU bias fields.
- * Skip them until we figure out why.
- */
- if (reg->syscon == sc->sc_pmu) {
- bias = -1;
- }
-
LOCK(reg);
if (bias != -1) {
CVS commit: src/sys/arch/arm/rockchip
Module Name:src Committed By: jmcneill Date: Fri Nov 12 22:53:21 UTC 2021 Modified Files: src/sys/arch/arm/rockchip: rk3288_iomux.c Log Message: Fix register accesses to PMU registers. Unlike the GRF ones, a RMW cycle is required to update settings here. To generate a diff of this commit: cvs rdiff -u -r1.1 -r1.2 src/sys/arch/arm/rockchip/rk3288_iomux.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/dev/i2c
Module Name:src
Committed By: christos
Date: Fri Nov 12 22:16:28 UTC 2021
Modified Files:
src/sys/dev/i2c: sht3x.c
Log Message:
simplify the code and remove unused (it is in CVS anyway). Try to merge
duplicate code. Follow KNF. Brad, please test!
To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/sys/dev/i2c/sht3x.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/dev/i2c/sht3x.c
diff -u src/sys/dev/i2c/sht3x.c:1.1 src/sys/dev/i2c/sht3x.c:1.2
--- src/sys/dev/i2c/sht3x.c:1.1 Sat Nov 6 09:34:40 2021
+++ src/sys/dev/i2c/sht3x.c Fri Nov 12 17:16:27 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: sht3x.c,v 1.1 2021/11/06 13:34:40 brad Exp $ */
+/* $NetBSD: sht3x.c,v 1.2 2021/11/12 22:16:27 christos Exp $ */
/*
* Copyright (c) 2021 Brad Spencer
@@ -17,7 +17,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: sht3x.c,v 1.1 2021/11/06 13:34:40 brad Exp $");
+__KERNEL_RCSID(0, "$NetBSD: sht3x.c,v 1.2 2021/11/12 22:16:27 christos Exp $");
/*
Driver for the Sensirion SHT30/SHT31/SHT35
@@ -52,17 +52,6 @@ static int sht3x_match(device_t, cfdata
static void sht3x_attach(device_t, device_t, void *);
static int sht3x_detach(device_t, int);
static void sht3x_refresh(struct sysmon_envsys *, envsys_data_t *);
-/* The chip that I had would not allow the limits to actually be set
- * for reasons which are not obvious. The chip took the command just
- * fine, but a read back of the limit registers showed that no change
- * was made, so disable limits for now.
- */
-#ifdef __did_not_work
-static void sht3x_get_limits(struct sysmon_envsys *, envsys_data_t *,
- sysmon_envsys_lim_t *, uint32_t *);
-static void sht3x_set_limits(struct sysmon_envsys *, envsys_data_t *,
- sysmon_envsys_lim_t *, uint32_t *);
-#endif
static int sht3x_verify_sysctl(SYSCTLFN_ARGS);
static int sht3x_verify_sysctl_heateron(SYSCTLFN_ARGS);
static int sht3x_verify_sysctl_modes(SYSCTLFN_ARGS);
@@ -338,8 +327,8 @@ sht3x_take_break(void *aux, bool have_bu
if (! have_bus) {
error = iic_acquire_bus(sc->sc_tag, 0);
if (error) {
- DPRINTF(sc, 2, ("%s: Could not acquire iic bus for breaking %d\n",
- device_xname(sc->sc_dev), error));
+ DPRINTF(sc, 2, ("%s: Could not acquire iic bus for "
+ "breaking %d\n", device_xname(sc->sc_dev), error));
goto out;
}
}
@@ -348,13 +337,13 @@ sht3x_take_break(void *aux, bool have_bu
DPRINTF(sc, 2, ("%s: Error breaking: %d\n",
device_xname(sc->sc_dev), error));
}
- out:
+out:
if (! have_bus) {
iic_release_bus(sc->sc_tag, 0);
}
sc->sc_isperiodic = false;
- strlcpy(sc->sc_mode,"single-shot",SHT3X_MODE_NAME);
+ strlcpy(sc->sc_mode, "single-shot", SHT3X_MODE_NAME);
return error;
}
@@ -362,56 +351,53 @@ sht3x_take_break(void *aux, bool have_bu
static int
sht3x_get_status_register(void *aux, uint16_t *reg, bool have_bus)
{
- struct sht3x_sc *sc;
- sc = aux;
+ struct sht3x_sc *sc = aux;
uint8_t buf[3];
- int error = 0;
+ int error;
if (! have_bus) {
error = iic_acquire_bus(sc->sc_tag, 0);
if (error) {
- DPRINTF(sc, 2, ("%s: Could not acquire iic bus for getting status %d\n",
- device_xname(sc->sc_dev), error));
- goto out;
+ DPRINTF(sc, 2, ("%s: Could not acquire iic bus for "
+ "getting status %d\n", device_xname(sc->sc_dev),
+ error));
+ return error;
}
}
error = sht3x_cmdr(sc, SHT3X_GET_STATUS_REGISTER, buf, 3);
if (error) {
DPRINTF(sc, 2, ("%s: Error getting status: %d\n",
device_xname(sc->sc_dev), error));
+ goto out;
}
- out:
+
+ uint8_t c = sht3x_crc([0], 2);
+ if (c == buf[2]) {
+ *reg = buf[0] << 8 | buf[1];
+ } else {
+ error = EINVAL;
+ }
+out:
if (! have_bus) {
iic_release_bus(sc->sc_tag, 0);
}
- if (!error) {
- uint8_t c;
-
- c = sht3x_crc([0],2);
- if (c == buf[2]) {
- *reg = buf[0] << 8 | buf[1];
- } else {
- error = EINVAL;
- }
- }
-
return error;
}
static int
sht3x_clear_status_register(void *aux, bool have_bus)
{
- struct sht3x_sc *sc;
- sc = aux;
- int error = 0;
+ struct sht3x_sc *sc = aux;
+ int error;
if (! have_bus) {
error = iic_acquire_bus(sc->sc_tag, 0);
if (error) {
- DPRINTF(sc, 2, ("%s: Could not acquire iic bus for clearing status %d\n",
- device_xname(sc->sc_dev), error));
- goto out;
+ DPRINTF(sc, 2, ("%s: Could not acquire iic bus for "
+ "clearing status %d\n", device_xname(sc->sc_dev),
+ error));
+ return error;
}
}
error = sht3x_cmdr(sc, SHT3X_CLEAR_STATUS_REGISTER, NULL, 0);
@@ -419,7 +405,6 @@ sht3x_clear_status_register(void *aux, b
DPRINTF(sc, 2, ("%s: Error clear status register: %d\n",
device_xname(sc->sc_dev), error));
}
- out:
if (! have_bus) {
iic_release_bus(sc->sc_tag, 0);
}
@@ -438,16 +423,18 @@ sht3x_thread(void *aux)
while (!sc->sc_stopping && !sc->sc_dying) {
if (sc->sc_initperiodic) {
- error =
CVS commit: src/sys/dev/i2c
Module Name:src Committed By: christos Date: Fri Nov 12 22:16:28 UTC 2021 Modified Files: src/sys/dev/i2c: sht3x.c Log Message: simplify the code and remove unused (it is in CVS anyway). Try to merge duplicate code. Follow KNF. Brad, please test! To generate a diff of this commit: cvs rdiff -u -r1.1 -r1.2 src/sys/dev/i2c/sht3x.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/doc
Module Name:src Committed By: jmcneill Date: Fri Nov 12 22:02:49 UTC 2021 Modified Files: src/doc: CHANGES Log Message: evbarm: Add support for Rockchip RK3288 SoCs. To generate a diff of this commit: cvs rdiff -u -r1.2849 -r1.2850 src/doc/CHANGES Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/doc/CHANGES diff -u src/doc/CHANGES:1.2849 src/doc/CHANGES:1.2850 --- src/doc/CHANGES:1.2849 Sun Nov 7 17:17:24 2021 +++ src/doc/CHANGES Fri Nov 12 22:02:49 2021 @@ -1,4 +1,4 @@ -# LIST OF CHANGES FROM LAST RELEASE: <$Revision: 1.2849 $> +# LIST OF CHANGES FROM LAST RELEASE: <$Revision: 1.2850 $> # # # [Note: This file does not mention every change made to the NetBSD source tree. @@ -453,3 +453,4 @@ Changes from NetBSD 9.0 to NetBSD 10.0: sht3xtemp(4): Driver for the Sensirion SHT30/SHT31/SHT35 temperature and humidity sensor [brad 20211106] dts: Import dts files from Linux 5.15. [jmcneill 20211107] + evbarm: Add support for Rockchip RK3288 SoCs. [jmcneill 2022]
CVS commit: src/doc
Module Name:src Committed By: jmcneill Date: Fri Nov 12 22:02:49 UTC 2021 Modified Files: src/doc: CHANGES Log Message: evbarm: Add support for Rockchip RK3288 SoCs. To generate a diff of this commit: cvs rdiff -u -r1.2849 -r1.2850 src/doc/CHANGES Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch
Module Name:src
Committed By: jmcneill
Date: Fri Nov 12 22:02:08 UTC 2021
Modified Files:
src/sys/arch/arm/rockchip: files.rockchip rk3328_cru.c rk3399_cru.c
rk_cru.h rk_cru_composite.c rk_cru_pll.c rk_gmac.c rk_i2c.c
rk_platform.c
src/sys/arch/evbarm/conf: GENERIC files.generic
Added Files:
src/sys/arch/arm/rockchip: rk3066_smp.c rk3288_cru.c rk3288_cru.h
rk3288_iomux.c rk3288_platform.h rk3288_usb.c
Log Message:
arm: rockchip: Add support for RK3288 SoC.
The Rockchip RK3288 is a quad core Cortex-A17 SoC.
To generate a diff of this commit:
cvs rdiff -u -r1.24 -r1.25 src/sys/arch/arm/rockchip/files.rockchip
cvs rdiff -u -r0 -r1.1 src/sys/arch/arm/rockchip/rk3066_smp.c \
src/sys/arch/arm/rockchip/rk3288_cru.c \
src/sys/arch/arm/rockchip/rk3288_cru.h \
src/sys/arch/arm/rockchip/rk3288_iomux.c \
src/sys/arch/arm/rockchip/rk3288_platform.h \
src/sys/arch/arm/rockchip/rk3288_usb.c
cvs rdiff -u -r1.8 -r1.9 src/sys/arch/arm/rockchip/rk3328_cru.c
cvs rdiff -u -r1.22 -r1.23 src/sys/arch/arm/rockchip/rk3399_cru.c
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/arm/rockchip/rk_cru.h
cvs rdiff -u -r1.6 -r1.7 src/sys/arch/arm/rockchip/rk_cru_composite.c
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/arm/rockchip/rk_cru_pll.c
cvs rdiff -u -r1.20 -r1.21 src/sys/arch/arm/rockchip/rk_gmac.c
cvs rdiff -u -r1.10 -r1.11 src/sys/arch/arm/rockchip/rk_i2c.c
cvs rdiff -u -r1.14 -r1.15 src/sys/arch/arm/rockchip/rk_platform.c
cvs rdiff -u -r1.100 -r1.101 src/sys/arch/evbarm/conf/GENERIC
cvs rdiff -u -r1.11 -r1.12 src/sys/arch/evbarm/conf/files.generic
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/rockchip/files.rockchip
diff -u src/sys/arch/arm/rockchip/files.rockchip:1.24 src/sys/arch/arm/rockchip/files.rockchip:1.25
--- src/sys/arch/arm/rockchip/files.rockchip:1.24 Sun May 17 19:57:25 2020
+++ src/sys/arch/arm/rockchip/files.rockchip Fri Nov 12 22:02:08 2021
@@ -1,4 +1,4 @@
-# $NetBSD: files.rockchip,v 1.24 2020/05/17 19:57:25 riastradh Exp $
+# $NetBSD: files.rockchip,v 1.25 2021/11/12 22:02:08 jmcneill Exp $
#
# Configuration info for Rockchip family SoCs
#
@@ -6,6 +6,8 @@
file arch/arm/rockchip/rk_platform.c soc_rockchip
+file arch/arm/rockchip/rk3066_smp.c soc_rk3288
+
# Clock and reset unit (CRU)
device rkcru: rk_cru
file arch/arm/rockchip/rk_cru.c rk_cru
@@ -15,6 +17,14 @@ file arch/arm/rockchip/rk_cru_gate.c rk
file arch/arm/rockchip/rk_cru_mux.c rk_cru
file arch/arm/rockchip/rk_cru_pll.c rk_cru
+ifdef arm
+
+# RK3288 clock and reset unit
+attach rkcru at fdt with rk3288_cru
+file arch/arm/rockchip/rk3288_cru.c rk3288_cru & soc_rk3288
+
+else
+
# RK3328 clock and reset unit
attach rkcru at fdt with rk3328_cru
file arch/arm/rockchip/rk3328_cru.c rk3328_cru & soc_rk3328
@@ -25,13 +35,25 @@ file arch/arm/rockchip/rk3399_cru.c rk3
attach rkcru at fdt with rk3399_pmucru
file arch/arm/rockchip/rk3399_pmucru.c rk3399_pmucru & soc_rk3399
+endif
+
# IOMUX control
device rkiomux { }
+
+ifdef arm
+
+attach rkiomux at fdt with rk3288_iomux
+file arch/arm/rockchip/rk3288_iomux.c rk3288_iomux & soc_rk3288
+
+else
+
attach rkiomux at fdt with rk3328_iomux
file arch/arm/rockchip/rk3328_iomux.c rk3328_iomux & soc_rk3328
attach rkiomux at fdt with rk3399_iomux
file arch/arm/rockchip/rk3399_iomux.c rk3399_iomux & soc_rk3399
+endif
+
# GPIO
device rkgpio: gpiobus
attach rkgpio at rkiomux with rk_gpio
@@ -54,6 +76,12 @@ device rkusbphy
attach rkusbphy at rkusb with rk_usbphy
file arch/arm/rockchip/rk_usb.c rk_usb | rk_usbphy
+device rk3288usb { }
+attach rk3288usb at fdt with rk3288_usb
+device rk3288usbphy
+attach rk3288usbphy at rk3288usb with rk3288_usbphy
+file arch/arm/rockchip/rk3288_usb.c rk3288_usb | rk3288_usbphy
+
# GMAC
attach awge at fdt with rk_gmac
file arch/arm/rockchip/rk_gmac.c rk_gmac
@@ -119,5 +147,6 @@ file arch/arm/rockchip/rk_v1crypto.c rk
# SOC parameters
defflag opt_soc.h SOC_ROCKCHIP
+defflag opt_soc.h SOC_RK3288: SOC_ROCKCHIP
defflag opt_soc.h SOC_RK3328: SOC_ROCKCHIP
defflag opt_soc.h SOC_RK3399: SOC_ROCKCHIP
Index: src/sys/arch/arm/rockchip/rk3328_cru.c
diff -u src/sys/arch/arm/rockchip/rk3328_cru.c:1.8 src/sys/arch/arm/rockchip/rk3328_cru.c:1.9
--- src/sys/arch/arm/rockchip/rk3328_cru.c:1.8 Sat May 15 08:46:00 2021
+++ src/sys/arch/arm/rockchip/rk3328_cru.c Fri Nov 12 22:02:08 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: rk3328_cru.c,v 1.8 2021/05/15 08:46:00 mrg Exp $ */
+/* $NetBSD: rk3328_cru.c,v 1.9 2021/11/12 22:02:08 jmcneill Exp $ */
/*-
* Copyright (c) 2018 Jared McNeill
@@ -28,7 +28,7 @@
#include
-__KERNEL_RCSID(1, "$NetBSD: rk3328_cru.c,v 1.8 2021/05/15 08:46:00 mrg Exp $");
+__KERNEL_RCSID(1, "$NetBSD: rk3328_cru.c,v 1.9 2021/11/12 22:02:08 jmcneill Exp $");
#include
#include
@@ -501,6 +501,7 @@ rk3328_cru_attach(device_t parent, devic
CVS commit: src/sys/arch
Module Name:src Committed By: jmcneill Date: Fri Nov 12 22:02:08 UTC 2021 Modified Files: src/sys/arch/arm/rockchip: files.rockchip rk3328_cru.c rk3399_cru.c rk_cru.h rk_cru_composite.c rk_cru_pll.c rk_gmac.c rk_i2c.c rk_platform.c src/sys/arch/evbarm/conf: GENERIC files.generic Added Files: src/sys/arch/arm/rockchip: rk3066_smp.c rk3288_cru.c rk3288_cru.h rk3288_iomux.c rk3288_platform.h rk3288_usb.c Log Message: arm: rockchip: Add support for RK3288 SoC. The Rockchip RK3288 is a quad core Cortex-A17 SoC. To generate a diff of this commit: cvs rdiff -u -r1.24 -r1.25 src/sys/arch/arm/rockchip/files.rockchip cvs rdiff -u -r0 -r1.1 src/sys/arch/arm/rockchip/rk3066_smp.c \ src/sys/arch/arm/rockchip/rk3288_cru.c \ src/sys/arch/arm/rockchip/rk3288_cru.h \ src/sys/arch/arm/rockchip/rk3288_iomux.c \ src/sys/arch/arm/rockchip/rk3288_platform.h \ src/sys/arch/arm/rockchip/rk3288_usb.c cvs rdiff -u -r1.8 -r1.9 src/sys/arch/arm/rockchip/rk3328_cru.c cvs rdiff -u -r1.22 -r1.23 src/sys/arch/arm/rockchip/rk3399_cru.c cvs rdiff -u -r1.7 -r1.8 src/sys/arch/arm/rockchip/rk_cru.h cvs rdiff -u -r1.6 -r1.7 src/sys/arch/arm/rockchip/rk_cru_composite.c cvs rdiff -u -r1.4 -r1.5 src/sys/arch/arm/rockchip/rk_cru_pll.c cvs rdiff -u -r1.20 -r1.21 src/sys/arch/arm/rockchip/rk_gmac.c cvs rdiff -u -r1.10 -r1.11 src/sys/arch/arm/rockchip/rk_i2c.c cvs rdiff -u -r1.14 -r1.15 src/sys/arch/arm/rockchip/rk_platform.c cvs rdiff -u -r1.100 -r1.101 src/sys/arch/evbarm/conf/GENERIC cvs rdiff -u -r1.11 -r1.12 src/sys/arch/evbarm/conf/files.generic Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm
Module Name:src
Committed By: jmcneill
Date: Fri Nov 12 21:59:05 UTC 2021
Modified Files:
src/sys/arch/arm/cortex: gtmr.c gtmr_var.h
src/sys/arch/arm/fdt: gtmr_fdt.c
Log Message:
gtmr: Add support for arm,cpu-registers-not-fw-configured property.
On armv7, arm,cpu-registers-not-fw-configured means that firmware hasn't
bothered to configure any generic timer registers and we need to
initialize cntfrq ourselves.
To generate a diff of this commit:
cvs rdiff -u -r1.46 -r1.47 src/sys/arch/arm/cortex/gtmr.c
cvs rdiff -u -r1.14 -r1.15 src/sys/arch/arm/cortex/gtmr_var.h
cvs rdiff -u -r1.11 -r1.12 src/sys/arch/arm/fdt/gtmr_fdt.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gtmr.c
diff -u src/sys/arch/arm/cortex/gtmr.c:1.46 src/sys/arch/arm/cortex/gtmr.c:1.47
--- src/sys/arch/arm/cortex/gtmr.c:1.46 Sun Oct 31 16:23:47 2021
+++ src/sys/arch/arm/cortex/gtmr.c Fri Nov 12 21:59:04 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: gtmr.c,v 1.46 2021/10/31 16:23:47 skrll Exp $ */
+/* $NetBSD: gtmr.c,v 1.47 2021/11/12 21:59:04 jmcneill Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: gtmr.c,v 1.46 2021/10/31 16:23:47 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gtmr.c,v 1.47 2021/11/12 21:59:04 jmcneill Exp $");
#include
#include
@@ -127,6 +127,13 @@ gtmr_attach(device_t parent, device_t se
aprint_normal(": Generic Timer (%s, %s)\n", freqbuf,
sc->sc_physical ? "physical" : "virtual");
+#if defined(__arm__)
+ if (prop_dictionary_get_bool(dict, "arm,cpu-registers-not-fw-configured", ) && flag) {
+ sc->sc_flags |= GTMR_FLAG_CPU_REGISTERS_NOT_FW_CONFIGURED;
+ aprint_debug_dev(self, "CPU registers not initialized by firmware\n");
+ }
+#endif
+
if (prop_dictionary_get_bool(dict, "sun50i-a64-unstable-timer", ) && flag) {
sc->sc_flags |= GTMR_FLAG_SUN50I_A64_UNSTABLE_TIMER;
aprint_debug_dev(self, "enabling Allwinner A64 timer workaround\n");
@@ -250,6 +257,10 @@ gtmr_init_cpu_clock(struct cpu_info *ci)
/* XXX hmm... called from cpu_hatch which hasn't lowered ipl yet */
int s = splsched();
+ if ((sc->sc_flags & GTMR_FLAG_CPU_REGISTERS_NOT_FW_CONFIGURED) != 0) {
+ armreg_cnt_frq_write(sc->sc_freq);
+ }
+
/*
* Allow the virtual and physical counters to be accessed from
* usermode. (PL0)
Index: src/sys/arch/arm/cortex/gtmr_var.h
diff -u src/sys/arch/arm/cortex/gtmr_var.h:1.14 src/sys/arch/arm/cortex/gtmr_var.h:1.15
--- src/sys/arch/arm/cortex/gtmr_var.h:1.14 Thu Mar 5 15:18:54 2020
+++ src/sys/arch/arm/cortex/gtmr_var.h Fri Nov 12 21:59:04 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: gtmr_var.h,v 1.14 2020/03/05 15:18:54 riastradh Exp $ */
+/* $NetBSD: gtmr_var.h,v 1.15 2021/11/12 21:59:04 jmcneill Exp $ */
/*-
* Copyright (c) 2013 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -38,7 +38,8 @@ struct gtmr_softc {
struct evcnt sc_ev_missing_ticks;
uint32_t sc_freq;
uint32_t sc_flags;
-#define GTMR_FLAG_SUN50I_A64_UNSTABLE_TIMER __BIT(0)
+#define GTMR_FLAG_SUN50I_A64_UNSTABLE_TIMER __BIT(0)
+#define GTMR_FLAG_CPU_REGISTERS_NOT_FW_CONFIGURED __BIT(1)
u_long sc_autoinc;
bool sc_physical;
void *sc_global_ih;
Index: src/sys/arch/arm/fdt/gtmr_fdt.c
diff -u src/sys/arch/arm/fdt/gtmr_fdt.c:1.11 src/sys/arch/arm/fdt/gtmr_fdt.c:1.12
--- src/sys/arch/arm/fdt/gtmr_fdt.c:1.11 Sat Aug 7 16:18:43 2021
+++ src/sys/arch/arm/fdt/gtmr_fdt.c Fri Nov 12 21:59:05 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: gtmr_fdt.c,v 1.11 2021/08/07 16:18:43 thorpej Exp $ */
+/* $NetBSD: gtmr_fdt.c,v 1.12 2021/11/12 21:59:05 jmcneill Exp $ */
/*-
* Copyright (c) 2017 Jared McNeill
@@ -27,7 +27,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: gtmr_fdt.c,v 1.11 2021/08/07 16:18:43 thorpej Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gtmr_fdt.c,v 1.12 2021/11/12 21:59:05 jmcneill Exp $");
#include
#include
@@ -44,6 +44,10 @@ __KERNEL_RCSID(0, "$NetBSD: gtmr_fdt.c,v
#include
#include
+#if defined(__arm__)
+#include
+#endif
+
static int gtmr_fdt_match(device_t, cfdata_t, void *);
static void gtmr_fdt_attach(device_t, device_t, void *);
@@ -95,6 +99,23 @@ gtmr_fdt_attach(device_t parent, device_
}
aprint_normal_dev(self, "interrupting on %s\n", intrstr);
+#if defined(__arm__)
+ /*
+ * If arm,cpu-registers-not-fw-configured is present, we need
+ * to initialize cntfrq from the clock-frequency property. Only
+ * applicable on Armv7.
+ */
+ if (of_hasprop(phandle, "arm,cpu-registers-not-fw-configured")) {
+ uint32_t freq;
+
+ if (of_getprop_uint32(phandle, "clock-frequency", ) == 0) {
+ armreg_cnt_frq_write(freq);
+ prop_dictionary_set_bool(device_properties(self),
+ "arm,cpu-registers-not-fw-configured", true);
+ }
+ }
+#endif
+
config_found(self, , NULL, CFARGS_NONE);
arm_fdt_cpu_hatch_register(self, gtmr_fdt_cpu_hatch);
CVS commit: src/sys/arch/arm
Module Name:src Committed By: jmcneill Date: Fri Nov 12 21:59:05 UTC 2021 Modified Files: src/sys/arch/arm/cortex: gtmr.c gtmr_var.h src/sys/arch/arm/fdt: gtmr_fdt.c Log Message: gtmr: Add support for arm,cpu-registers-not-fw-configured property. On armv7, arm,cpu-registers-not-fw-configured means that firmware hasn't bothered to configure any generic timer registers and we need to initialize cntfrq ourselves. To generate a diff of this commit: cvs rdiff -u -r1.46 -r1.47 src/sys/arch/arm/cortex/gtmr.c cvs rdiff -u -r1.14 -r1.15 src/sys/arch/arm/cortex/gtmr_var.h cvs rdiff -u -r1.11 -r1.12 src/sys/arch/arm/fdt/gtmr_fdt.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/dev/fdt
Module Name:src
Committed By: jmcneill
Date: Fri Nov 12 21:57:44 UTC 2021
Modified Files:
src/sys/dev/fdt: dw_apb_uart.c
Log Message:
dw_apb_uart: Honour reg-io-width property
To generate a diff of this commit:
cvs rdiff -u -r1.10 -r1.11 src/sys/dev/fdt/dw_apb_uart.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/dev/fdt/dw_apb_uart.c
diff -u src/sys/dev/fdt/dw_apb_uart.c:1.10 src/sys/dev/fdt/dw_apb_uart.c:1.11
--- src/sys/dev/fdt/dw_apb_uart.c:1.10 Wed Jan 27 03:10:21 2021
+++ src/sys/dev/fdt/dw_apb_uart.c Fri Nov 12 21:57:44 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: dw_apb_uart.c,v 1.10 2021/01/27 03:10:21 thorpej Exp $ */
+/* $NetBSD: dw_apb_uart.c,v 1.11 2021/11/12 21:57:44 jmcneill Exp $ */
/*-
* Copyright (c) 2017 Jared McNeill
@@ -28,7 +28,7 @@
#include
-__KERNEL_RCSID(1, "$NetBSD: dw_apb_uart.c,v 1.10 2021/01/27 03:10:21 thorpej Exp $");
+__KERNEL_RCSID(1, "$NetBSD: dw_apb_uart.c,v 1.11 2021/11/12 21:57:44 jmcneill Exp $");
#include
#include
@@ -76,27 +76,32 @@ dw_apb_uart_attach(device_t parent, devi
struct dw_apb_uart_softc * const ssc = device_private(self);
struct com_softc * const sc = >ssc_sc;
struct fdt_attach_args * const faa = aux;
+ const int phandle = faa->faa_phandle;
bus_space_tag_t bst = faa->faa_bst;
bus_space_handle_t bsh;
char intrstr[128];
bus_addr_t addr;
bus_size_t size;
- u_int reg_shift;
+ u_int reg_shift, reg_iowidth;
int error;
- if (fdtbus_get_reg(faa->faa_phandle, 0, , ) != 0) {
+ if (fdtbus_get_reg(phandle, 0, , ) != 0) {
aprint_error(": couldn't get registers\n");
return;
}
- if (of_getprop_uint32(faa->faa_phandle, "reg-shift", _shift)) {
+ if (of_getprop_uint32(phandle, "reg-shift", _shift)) {
/* missing or bad reg-shift property, assume 2 */
reg_shift = 2;
}
+ if (of_getprop_uint32(phandle, "reg-io-width", _iowidth)) {
+ /* missing or bad reg-io-width propery, assume 1 */
+ reg_iowidth = 1;
+ }
sc->sc_dev = self;
- ssc->ssc_clk = fdtbus_clock_get_index(faa->faa_phandle, 0);
+ ssc->ssc_clk = fdtbus_clock_get_index(phandle, 0);
if (ssc->ssc_clk == NULL) {
aprint_error(": couldn't get clock\n");
return;
@@ -106,13 +111,13 @@ dw_apb_uart_attach(device_t parent, devi
return;
}
- ssc->ssc_pclk = fdtbus_clock_get(faa->faa_phandle, "apb_pclk");
+ ssc->ssc_pclk = fdtbus_clock_get(phandle, "apb_pclk");
if (ssc->ssc_pclk != NULL && clk_enable(ssc->ssc_pclk) != 0) {
aprint_error(": couldn't enable peripheral clock\n");
return;
}
- ssc->ssc_rst = fdtbus_reset_get_index(faa->faa_phandle, 0);
+ ssc->ssc_rst = fdtbus_reset_get_index(phandle, 0);
if (ssc->ssc_rst && fdtbus_reset_deassert(ssc->ssc_rst) != 0) {
aprint_error(": couldn't de-assert reset\n");
return;
@@ -127,16 +132,16 @@ dw_apb_uart_attach(device_t parent, devi
return;
}
- com_init_regs_stride(>sc_regs, bst, bsh, addr, reg_shift);
+ com_init_regs_stride_width(>sc_regs, bst, bsh, addr, reg_shift, reg_iowidth);
com_attach_subr(sc);
- if (!fdtbus_intr_str(faa->faa_phandle, 0, intrstr, sizeof(intrstr))) {
+ if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) {
aprint_error_dev(self, "failed to decode interrupt\n");
return;
}
- ssc->ssc_ih = fdtbus_intr_establish_xname(faa->faa_phandle, 0,
+ ssc->ssc_ih = fdtbus_intr_establish_xname(phandle, 0,
IPL_SERIAL, FDT_INTR_MPSAFE, comintr, sc, device_xname(self));
if (ssc->ssc_ih == NULL) {
aprint_error_dev(self, "failed to establish interrupt on %s\n",
@@ -164,7 +169,7 @@ dw_apb_uart_console_consinit(struct fdt_
struct com_regs regs;
bus_addr_t addr;
tcflag_t flags;
- u_int reg_shift;
+ u_int reg_shift, reg_iowidth;
int speed;
fdtbus_get_reg(phandle, 0, , NULL);
@@ -177,9 +182,13 @@ dw_apb_uart_console_consinit(struct fdt_
/* missing or bad reg-shift property, assume 2 */
reg_shift = 2;
}
+ if (of_getprop_uint32(phandle, "reg-io-width", _iowidth)) {
+ /* missing or bad reg-io-width propery, assume 1 */
+ reg_iowidth = 1;
+ }
memset(_bsh, 0, sizeof(dummy_bsh));
- com_init_regs_stride(, bst, dummy_bsh, addr, reg_shift);
+ com_init_regs_stride_width(, bst, dummy_bsh, addr, reg_shift, reg_iowidth);
if (comcnattach1(, speed, uart_freq, COM_TYPE_DW_APB, flags))
panic("Cannot initialize dw-apb-uart console");
CVS commit: src/sys/dev/fdt
Module Name:src Committed By: jmcneill Date: Fri Nov 12 21:57:44 UTC 2021 Modified Files: src/sys/dev/fdt: dw_apb_uart.c Log Message: dw_apb_uart: Honour reg-io-width property To generate a diff of this commit: cvs rdiff -u -r1.10 -r1.11 src/sys/dev/fdt/dw_apb_uart.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/dev/ic
Module Name:src
Committed By: jmcneill
Date: Fri Nov 12 21:57:13 UTC 2021
Modified Files:
src/sys/dev/ic: com.c comvar.h
Log Message:
com: Add support for 32-bit IO accesses.
To generate a diff of this commit:
cvs rdiff -u -r1.372 -r1.373 src/sys/dev/ic/com.c
cvs rdiff -u -r1.95 -r1.96 src/sys/dev/ic/comvar.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/dev/ic/com.c
diff -u src/sys/dev/ic/com.c:1.372 src/sys/dev/ic/com.c:1.373
--- src/sys/dev/ic/com.c:1.372 Sat Oct 30 11:43:17 2021
+++ src/sys/dev/ic/com.c Fri Nov 12 21:57:13 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: com.c,v 1.372 2021/10/30 11:43:17 jmcneill Exp $ */
+/* $NetBSD: com.c,v 1.373 2021/11/12 21:57:13 jmcneill Exp $ */
/*-
* Copyright (c) 1998, 1999, 2004, 2008 The NetBSD Foundation, Inc.
@@ -66,7 +66,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: com.c,v 1.372 2021/10/30 11:43:17 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: com.c,v 1.373 2021/11/12 21:57:13 jmcneill Exp $");
#include "opt_com.h"
#include "opt_ddb.h"
@@ -128,17 +128,20 @@ __KERNEL_RCSID(0, "$NetBSD: com.c,v 1.37
#include "ioconf.h"
-#define CSR_WRITE_1(r, o, v) \
- bus_space_write_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v)
#define CSR_READ_1(r, o) \
- bus_space_read_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o])
+ (r)->cr_read((r), (r)->cr_map[o])
+#define CSR_WRITE_1(r, o, v) \
+ (r)->cr_write((r), (r)->cr_map[o], (v))
+#define CSR_WRITE_MULTI(r, o, p, n) \
+ (r)->cr_write_multi((r), (r)->cr_map[o], (p), (n))
+
+/*
+ * XXX COM_TYPE_AU1x00 specific
+ */
#define CSR_WRITE_2(r, o, v) \
bus_space_write_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v)
#define CSR_READ_2(r, o) \
bus_space_read_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o])
-#define CSR_WRITE_MULTI(r, o, p, n) \
- bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], p, n)
-
static void com_enable_debugport(struct com_softc *);
@@ -275,6 +278,70 @@ static const bus_size_t com_std_map[COM_
bus_space_barrier((r)->cr_iot, (r)->cr_ioh, 0, (r)->cr_nports, (f))
/*
+ * com_read_1 --
+ * Default register read callback using single byte accesses.
+ */
+static uint8_t
+com_read_1(struct com_regs *regs, u_int reg)
+{
+ return bus_space_read_1(regs->cr_iot, regs->cr_ioh, reg);
+}
+
+/*
+ * com_write_1 --
+ * Default register write callback using single byte accesses.
+ */
+static void
+com_write_1(struct com_regs *regs, u_int reg, uint8_t val)
+{
+ bus_space_write_1(regs->cr_iot, regs->cr_ioh, reg, val);
+}
+
+/*
+ * com_write_multi_1 --
+ * Default register multi write callback using single byte accesses.
+ */
+static void
+com_write_multi_1(struct com_regs *regs, u_int reg, const uint8_t *datap,
+bus_size_t count)
+{
+ bus_space_write_multi_1(regs->cr_iot, regs->cr_ioh, reg, datap, count);
+}
+
+/*
+ * com_read_4 --
+ * Default register read callback using dword accesses.
+ */
+static uint8_t
+com_read_4(struct com_regs *regs, u_int reg)
+{
+ return bus_space_read_4(regs->cr_iot, regs->cr_ioh, reg) & 0xff;
+}
+
+/*
+ * com_write_4 --
+ * Default register write callback using dword accesses.
+ */
+static void
+com_write_4(struct com_regs *regs, u_int reg, uint8_t val)
+{
+ bus_space_write_4(regs->cr_iot, regs->cr_ioh, reg, val);
+}
+
+/*
+ * com_write_multi_4 --
+ * Default register multi write callback using dword accesses.
+ */
+static void
+com_write_multi_4(struct com_regs *regs, u_int reg, const uint8_t *datap,
+bus_size_t count)
+{
+ while (count-- > 0) {
+ bus_space_write_4(regs->cr_iot, regs->cr_ioh, reg, *datap++);
+ }
+}
+
+/*
* com_init_regs --
* Driver front-ends use this to initialize our register map
* in the standard fashion. They may then tailor the map to
@@ -290,6 +357,9 @@ com_init_regs(struct com_regs *regs, bus
regs->cr_ioh = sh;
regs->cr_iobase = addr;
regs->cr_nports = COM_NPORTS;
+ regs->cr_read = com_read_1;
+ regs->cr_write = com_write_1;
+ regs->cr_write_multi = com_write_multi_1;
memcpy(regs->cr_map, com_std_map, sizeof(regs->cr_map));
}
@@ -310,6 +380,37 @@ com_init_regs_stride(struct com_regs *re
regs->cr_nports <<= regshift;
}
+/*
+ * com_init_regs_stride_width --
+ * Convenience function for front-ends that have a stride between
+ * registers and specific I/O width requirements.
+ */
+void
+com_init_regs_stride_width(struct com_regs *regs, bus_space_tag_t st,
+ bus_space_handle_t sh, bus_addr_t addr,
+ u_int regshift, u_int width)
+{
+
+ com_init_regs(regs, st, sh, addr);
+ for (size_t i = 0; i < __arraycount(regs->cr_map); i++) {
+ regs->cr_map[i] <<= regshift;
+ }
+ regs->cr_nports <<= regshift;
+
+ switch (width) {
+ case 1:
+ /* Already set by com_init_regs */
+ break;
+ case 4:
+ regs->cr_read = com_read_4;
+ regs->cr_write = com_write_4;
+ regs->cr_write_multi = com_write_multi_4;
+ break;
+ default:
+ panic("com: unsupported I/O width %d", width);
+ }
+}
+
/*ARGSUSED*/
int
CVS commit: src/sys/dev/ic
Module Name:src Committed By: jmcneill Date: Fri Nov 12 21:57:13 UTC 2021 Modified Files: src/sys/dev/ic: com.c comvar.h Log Message: com: Add support for 32-bit IO accesses. To generate a diff of this commit: cvs rdiff -u -r1.372 -r1.373 src/sys/dev/ic/com.c cvs rdiff -u -r1.95 -r1.96 src/sys/dev/ic/comvar.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/distrib/sets/lists/dtb
Module Name:src Committed By: jmcneill Date: Fri Nov 12 21:55:46 UTC 2021 Modified Files: src/distrib/sets/lists/dtb: ad.aarch64 ad.aarch64eb ad.earmv6 ad.earmv6eb ad.earmv6hf ad.earmv6hfeb ad.earmv7 ad.earmv7hf ad.earmv7hfeb Log Message: regen To generate a diff of this commit: cvs rdiff -u -r1.8 -r1.9 src/distrib/sets/lists/dtb/ad.aarch64 cvs rdiff -u -r1.7 -r1.8 src/distrib/sets/lists/dtb/ad.aarch64eb \ src/distrib/sets/lists/dtb/ad.earmv7 \ src/distrib/sets/lists/dtb/ad.earmv7hf \ src/distrib/sets/lists/dtb/ad.earmv7hfeb cvs rdiff -u -r1.6 -r1.7 src/distrib/sets/lists/dtb/ad.earmv6 \ src/distrib/sets/lists/dtb/ad.earmv6eb \ src/distrib/sets/lists/dtb/ad.earmv6hf \ src/distrib/sets/lists/dtb/ad.earmv6hfeb Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/distrib/sets/lists/dtb/ad.aarch64 diff -u src/distrib/sets/lists/dtb/ad.aarch64:1.8 src/distrib/sets/lists/dtb/ad.aarch64:1.9 --- src/distrib/sets/lists/dtb/ad.aarch64:1.8 Sun Nov 7 17:11:05 2021 +++ src/distrib/sets/lists/dtb/ad.aarch64 Fri Nov 12 21:55:46 2021 @@ -1,4 +1,4 @@ -# $NetBSD: ad.aarch64,v 1.8 2021/11/07 17:11:05 jmcneill Exp $ +# $NetBSD: ad.aarch64,v 1.9 2021/11/12 21:55:46 jmcneill Exp $ # # DO NOT EDIT THIS FILE MANUALLY # Generated by "make update-sets" in sys/dtb Index: src/distrib/sets/lists/dtb/ad.aarch64eb diff -u src/distrib/sets/lists/dtb/ad.aarch64eb:1.7 src/distrib/sets/lists/dtb/ad.aarch64eb:1.8 --- src/distrib/sets/lists/dtb/ad.aarch64eb:1.7 Sun Nov 7 17:11:05 2021 +++ src/distrib/sets/lists/dtb/ad.aarch64eb Fri Nov 12 21:55:46 2021 @@ -1,4 +1,4 @@ -# $NetBSD: ad.aarch64eb,v 1.7 2021/11/07 17:11:05 jmcneill Exp $ +# $NetBSD: ad.aarch64eb,v 1.8 2021/11/12 21:55:46 jmcneill Exp $ # # DO NOT EDIT THIS FILE MANUALLY # Generated by "make update-sets" in sys/dtb Index: src/distrib/sets/lists/dtb/ad.earmv7 diff -u src/distrib/sets/lists/dtb/ad.earmv7:1.7 src/distrib/sets/lists/dtb/ad.earmv7:1.8 --- src/distrib/sets/lists/dtb/ad.earmv7:1.7 Sun Nov 7 17:11:05 2021 +++ src/distrib/sets/lists/dtb/ad.earmv7 Fri Nov 12 21:55:46 2021 @@ -1,4 +1,4 @@ -# $NetBSD: ad.earmv7,v 1.7 2021/11/07 17:11:05 jmcneill Exp $ +# $NetBSD: ad.earmv7,v 1.8 2021/11/12 21:55:46 jmcneill Exp $ # # DO NOT EDIT THIS FILE MANUALLY # Generated by "make update-sets" in sys/dtb @@ -357,6 +357,44 @@ ./boot/dtb/omap3-thunder.dtb dtb-base-boot dtb ./boot/dtb/omap3-zoom3.dtb dtb-base-boot dtb ./boot/dtb/omap3430-sdp.dtb dtb-base-boot dtb +./boot/dtb/rk3036-evb.dtbdtb-base-boot dtb +./boot/dtb/rk3036-kylin.dtb dtb-base-boot dtb +./boot/dtb/rk3066a-bqcurie2.dtb dtb-base-boot dtb +./boot/dtb/rk3066a-marsboard.dtb dtb-base-boot dtb +./boot/dtb/rk3066a-mk808.dtb dtb-base-boot dtb +./boot/dtb/rk3066a-rayeager.dtb dtb-base-boot dtb +./boot/dtb/rk3188-bqedison2qc.dtbdtb-base-boot dtb +./boot/dtb/rk3188-px3-evb.dtbdtb-base-boot dtb +./boot/dtb/rk3188-radxarock.dtb dtb-base-boot dtb +./boot/dtb/rk3228-evb.dtbdtb-base-boot dtb +./boot/dtb/rk3229-evb.dtbdtb-base-boot dtb +./boot/dtb/rk3229-xms6.dtb dtb-base-boot dtb +./boot/dtb/rk3288-evb-act8846.dtbdtb-base-boot dtb +./boot/dtb/rk3288-evb-rk808.dtb dtb-base-boot dtb +./boot/dtb/rk3288-firefly-beta.dtb dtb-base-boot dtb +./boot/dtb/rk3288-firefly-reload.dtb dtb-base-boot dtb +./boot/dtb/rk3288-firefly.dtbdtb-base-boot dtb +./boot/dtb/rk3288-miqi.dtb dtb-base-boot dtb +./boot/dtb/rk3288-phycore-rdk.dtbdtb-base-boot dtb +./boot/dtb/rk3288-popmetal.dtb dtb-base-boot dtb +./boot/dtb/rk3288-r89.dtbdtb-base-boot dtb +./boot/dtb/rk3288-rock-pi-n8.dtb dtb-base-boot dtb +./boot/dtb/rk3288-rock2-square.dtb dtb-base-boot dtb +./boot/dtb/rk3288-tinker-s.dtb dtb-base-boot dtb +./boot/dtb/rk3288-tinker.dtb dtb-base-boot dtb +./boot/dtb/rk3288-veyron-brain.dtb dtb-base-boot dtb +./boot/dtb/rk3288-veyron-fievel.dtb dtb-base-boot dtb +./boot/dtb/rk3288-veyron-jaq.dtb dtb-base-boot dtb +./boot/dtb/rk3288-veyron-jerry.dtb dtb-base-boot dtb +./boot/dtb/rk3288-veyron-mickey.dtb dtb-base-boot dtb +./boot/dtb/rk3288-veyron-mighty.dtb dtb-base-boot dtb +./boot/dtb/rk3288-veyron-minnie.dtb
CVS commit: src/distrib/sets/lists/dtb
Module Name:src Committed By: jmcneill Date: Fri Nov 12 21:55:46 UTC 2021 Modified Files: src/distrib/sets/lists/dtb: ad.aarch64 ad.aarch64eb ad.earmv6 ad.earmv6eb ad.earmv6hf ad.earmv6hfeb ad.earmv7 ad.earmv7hf ad.earmv7hfeb Log Message: regen To generate a diff of this commit: cvs rdiff -u -r1.8 -r1.9 src/distrib/sets/lists/dtb/ad.aarch64 cvs rdiff -u -r1.7 -r1.8 src/distrib/sets/lists/dtb/ad.aarch64eb \ src/distrib/sets/lists/dtb/ad.earmv7 \ src/distrib/sets/lists/dtb/ad.earmv7hf \ src/distrib/sets/lists/dtb/ad.earmv7hfeb cvs rdiff -u -r1.6 -r1.7 src/distrib/sets/lists/dtb/ad.earmv6 \ src/distrib/sets/lists/dtb/ad.earmv6eb \ src/distrib/sets/lists/dtb/ad.earmv6hf \ src/distrib/sets/lists/dtb/ad.earmv6hfeb Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/dtb/arm
Module Name:src Committed By: jmcneill Date: Fri Nov 12 21:55:17 UTC 2021 Modified Files: src/sys/dtb/arm: Makefile Log Message: Build rockchip dtb files for armv7. To generate a diff of this commit: cvs rdiff -u -r1.4 -r1.5 src/sys/dtb/arm/Makefile Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/dtb/arm
Module Name:src Committed By: jmcneill Date: Fri Nov 12 21:55:17 UTC 2021 Modified Files: src/sys/dtb/arm: Makefile Log Message: Build rockchip dtb files for armv7. To generate a diff of this commit: cvs rdiff -u -r1.4 -r1.5 src/sys/dtb/arm/Makefile Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/dtb/arm/Makefile diff -u src/sys/dtb/arm/Makefile:1.4 src/sys/dtb/arm/Makefile:1.5 --- src/sys/dtb/arm/Makefile:1.4 Sun Nov 7 17:10:23 2021 +++ src/sys/dtb/arm/Makefile Fri Nov 12 21:55:17 2021 @@ -1,4 +1,4 @@ -# $NetBSD: Makefile,v 1.4 2021/11/07 17:10:23 jmcneill Exp $ +# $NetBSD: Makefile,v 1.5 2021/11/12 21:55:17 jmcneill Exp $ DTSARCH= arm DTSGNUARCH= arm @@ -16,6 +16,7 @@ DTSMAKEVARS= CONFIG_SOC_AM33XX=y \ CONFIG_MACH_MESON8=y \ CONFIG_ARCH_OMAP3=y \ CONFIG_ARCH_INTEL_SOCFPGA=y \ + CONFIG_ARCH_ROCKCHIP=y \ CONFIG_MACH_SUN4I=y \ CONFIG_MACH_SUN5I=y \ CONFIG_MACH_SUN6I=y \
CVS commit: xsrc/external/mit/xf86-video-mgx/dist/src
Module Name:xsrc Committed By: macallan Date: Fri Nov 12 19:01:19 UTC 2021 Modified Files: xsrc/external/mit/xf86-video-mgx/dist/src: mgx.h Log Message: fix license To generate a diff of this commit: cvs rdiff -u -r1.1 -r1.2 xsrc/external/mit/xf86-video-mgx/dist/src/mgx.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: xsrc/external/mit/xf86-video-mgx/dist/src
Module Name:xsrc Committed By: macallan Date: Fri Nov 12 19:01:19 UTC 2021 Modified Files: xsrc/external/mit/xf86-video-mgx/dist/src: mgx.h Log Message: fix license To generate a diff of this commit: cvs rdiff -u -r1.1 -r1.2 xsrc/external/mit/xf86-video-mgx/dist/src/mgx.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: xsrc/external/mit/xf86-video-mgx/dist/src/mgx.h diff -u xsrc/external/mit/xf86-video-mgx/dist/src/mgx.h:1.1 xsrc/external/mit/xf86-video-mgx/dist/src/mgx.h:1.2 --- xsrc/external/mit/xf86-video-mgx/dist/src/mgx.h:1.1 Fri Nov 12 18:58:14 2021 +++ xsrc/external/mit/xf86-video-mgx/dist/src/mgx.h Fri Nov 12 19:01:19 2021 @@ -1,7 +1,7 @@ /* - * TCX framebuffer - defines. + * Southland Media MGX - defines and such. * - * Copyright (C) 2000 Jakub Jelinek (ja...@redhat.com) + * Copyright (C) 2021 Michael Lorenz * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -16,7 +16,7 @@ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * JAKUB JELINEK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * MICHAEL LORENZ BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
CVS commit: xsrc/external/mit/xf86-video-mgx/dist
Module Name:xsrc Committed By: macallan Date: Fri Nov 12 18:58:14 UTC 2021 Added Files: xsrc/external/mit/xf86-video-mgx/dist: configure xsrc/external/mit/xf86-video-mgx/dist/src: compat-api.h mgx.h mgx_accel.c mgx_cursor.c mgx_driver.c Log Message: crude beginnings of a driver for the Southland Media / Quantum 3D MGX basic acceleration mostly works in 24bit colour needs native hw cursor code windowmaker produces visible artifacts, but it's good enough to run amiwm and a few xterms To generate a diff of this commit: cvs rdiff -u -r0 -r1.1 xsrc/external/mit/xf86-video-mgx/dist/configure cvs rdiff -u -r0 -r1.1 xsrc/external/mit/xf86-video-mgx/dist/src/compat-api.h \ xsrc/external/mit/xf86-video-mgx/dist/src/mgx.h \ xsrc/external/mit/xf86-video-mgx/dist/src/mgx_accel.c \ xsrc/external/mit/xf86-video-mgx/dist/src/mgx_cursor.c \ xsrc/external/mit/xf86-video-mgx/dist/src/mgx_driver.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Added files: Index: xsrc/external/mit/xf86-video-mgx/dist/configure diff -u /dev/null xsrc/external/mit/xf86-video-mgx/dist/configure:1.1 --- /dev/null Fri Nov 12 18:58:14 2021 +++ xsrc/external/mit/xf86-video-mgx/dist/configure Fri Nov 12 18:58:14 2021 @@ -0,0 +1,8 @@ +#! /bin/sh + +# Identity of this package. +PACKAGE_NAME='xf86-video-mgx' +PACKAGE_TARNAME='xf86-video-mgx' +PACKAGE_VERSION='0.0.1' +PACKAGE_STRING='xf86-video-mgx 0.0.1' +PACKAGE_BUGREPORT='https://bugs.freedesktop.org/enter_bug.cgi?product=xorg' Index: xsrc/external/mit/xf86-video-mgx/dist/src/compat-api.h diff -u /dev/null xsrc/external/mit/xf86-video-mgx/dist/src/compat-api.h:1.1 --- /dev/null Fri Nov 12 18:58:14 2021 +++ xsrc/external/mit/xf86-video-mgx/dist/src/compat-api.h Fri Nov 12 18:58:14 2021 @@ -0,0 +1,99 @@ +/* + * Copyright 2012 Red Hat, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Author: Dave Airlie + */ + +/* this file provides API compat between server post 1.13 and pre it, + it should be reused inside as many drivers as possible */ +#ifndef COMPAT_API_H +#define COMPAT_API_H + +#ifndef GLYPH_HAS_GLYPH_PICTURE_ACCESSOR +#define GetGlyphPicture(g, s) GlyphPicture((g))[(s)->myNum] +#define SetGlyphPicture(g, s, p) GlyphPicture((g))[(s)->myNum] = p +#endif + +#ifndef XF86_HAS_SCRN_CONV +#define xf86ScreenToScrn(s) xf86Screens[(s)->myNum] +#define xf86ScrnToScreen(s) screenInfo.screens[(s)->scrnIndex] +#endif + +#ifndef XF86_SCRN_INTERFACE + +#define SCRN_ARG_TYPE int +#define SCRN_INFO_PTR(arg1) ScrnInfoPtr pScrn = xf86Screens[(arg1)] + +#define SCREEN_ARG_TYPE int +#define SCREEN_PTR(arg1) ScreenPtr pScreen = screenInfo.screens[(arg1)] + +#define SCREEN_INIT_ARGS_DECL int i, ScreenPtr pScreen, int argc, char **argv + +#define BLOCKHANDLER_ARGS_DECL int arg, pointer blockData, pointer pTimeout, pointer pReadmask +#define BLOCKHANDLER_ARGS arg, blockData, pTimeout, pReadmask + +#define CLOSE_SCREEN_ARGS_DECL int scrnIndex, ScreenPtr pScreen +#define CLOSE_SCREEN_ARGS scrnIndex, pScreen + +#define ADJUST_FRAME_ARGS_DECL int arg, int x, int y, int flags +#define ADJUST_FRAME_ARGS(arg, x, y) (arg)->scrnIndex, x, y, 0 + +#define SWITCH_MODE_ARGS_DECL int arg, DisplayModePtr mode, int flags +#define SWITCH_MODE_ARGS(arg, m) (arg)->scrnIndex, m, 0 + +#define FREE_SCREEN_ARGS_DECL int arg, int flags + +#define VT_FUNC_ARGS_DECL int arg, int flags +#define VT_FUNC_ARGS pScrn->scrnIndex, 0 + +#define XF86_SCRN_ARG(x) ((x)->scrnIndex) +#else +#define SCRN_ARG_TYPE ScrnInfoPtr +#define SCRN_INFO_PTR(arg1) ScrnInfoPtr pScrn = (arg1) + +#define SCREEN_ARG_TYPE ScreenPtr +#define SCREEN_PTR(arg1) ScreenPtr pScreen = (arg1) + +#define SCREEN_INIT_ARGS_DECL ScreenPtr pScreen, int argc, char **argv + +#define BLOCKHANDLER_ARGS_DECL ScreenPtr arg, pointer pTimeout, pointer pReadmask +#define BLOCKHANDLER_ARGS arg,
CVS commit: xsrc/external/mit/xf86-video-mgx/dist
Module Name:xsrc Committed By: macallan Date: Fri Nov 12 18:58:14 UTC 2021 Added Files: xsrc/external/mit/xf86-video-mgx/dist: configure xsrc/external/mit/xf86-video-mgx/dist/src: compat-api.h mgx.h mgx_accel.c mgx_cursor.c mgx_driver.c Log Message: crude beginnings of a driver for the Southland Media / Quantum 3D MGX basic acceleration mostly works in 24bit colour needs native hw cursor code windowmaker produces visible artifacts, but it's good enough to run amiwm and a few xterms To generate a diff of this commit: cvs rdiff -u -r0 -r1.1 xsrc/external/mit/xf86-video-mgx/dist/configure cvs rdiff -u -r0 -r1.1 xsrc/external/mit/xf86-video-mgx/dist/src/compat-api.h \ xsrc/external/mit/xf86-video-mgx/dist/src/mgx.h \ xsrc/external/mit/xf86-video-mgx/dist/src/mgx_accel.c \ xsrc/external/mit/xf86-video-mgx/dist/src/mgx_cursor.c \ xsrc/external/mit/xf86-video-mgx/dist/src/mgx_driver.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src
Module Name:src Committed By: brad Date: Fri Nov 12 15:12:11 UTC 2021 Modified Files: src/share/man/man4: si70xxtemp.4 src/sys/dev/i2c: si70xx.c Log Message: Fix the serial number handling of the HTU21D chip and probably others. Increase the number of read attempts as the HTU21D and probably others do not respond as fast the actual SI70xx chip can. To generate a diff of this commit: cvs rdiff -u -r1.6 -r1.7 src/share/man/man4/si70xxtemp.4 cvs rdiff -u -r1.9 -r1.10 src/sys/dev/i2c/si70xx.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src
Module Name:src
Committed By: brad
Date: Fri Nov 12 15:12:11 UTC 2021
Modified Files:
src/share/man/man4: si70xxtemp.4
src/sys/dev/i2c: si70xx.c
Log Message:
Fix the serial number handling of the HTU21D chip and probably others.
Increase the number of read attempts as the HTU21D and probably others
do not respond as fast the actual SI70xx chip can.
To generate a diff of this commit:
cvs rdiff -u -r1.6 -r1.7 src/share/man/man4/si70xxtemp.4
cvs rdiff -u -r1.9 -r1.10 src/sys/dev/i2c/si70xx.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/share/man/man4/si70xxtemp.4
diff -u src/share/man/man4/si70xxtemp.4:1.6 src/share/man/man4/si70xxtemp.4:1.7
--- src/share/man/man4/si70xxtemp.4:1.6 Thu Nov 11 14:24:24 2021
+++ src/share/man/man4/si70xxtemp.4 Fri Nov 12 15:12:11 2021
@@ -1,4 +1,4 @@
-.\" $NetBSD: si70xxtemp.4,v 1.6 2021/11/11 14:24:24 wiz Exp $
+.\" $NetBSD: si70xxtemp.4,v 1.7 2021/11/12 15:12:11 brad Exp $
.\"
.\" Copyright (c) 2017 Brad Spencer
.\"
@@ -72,7 +72,7 @@ and then another read command is sent to
Depending on the resolution, and other factors, the wait time varies.
The driver will attempt to read back the values readattempts number of
times.
-The default is 25 which should be more than enough for most purposes.
+The default is 40 which should be enough for most purposes.
There is an initial wait of 10,500 microseconds followed by
a additional 1,000 microseconds per read attempt.
.El
Index: src/sys/dev/i2c/si70xx.c
diff -u src/sys/dev/i2c/si70xx.c:1.9 src/sys/dev/i2c/si70xx.c:1.10
--- src/sys/dev/i2c/si70xx.c:1.9 Thu Nov 11 14:16:04 2021
+++ src/sys/dev/i2c/si70xx.c Fri Nov 12 15:12:11 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: si70xx.c,v 1.9 2021/11/11 14:16:04 brad Exp $ */
+/* $NetBSD: si70xx.c,v 1.10 2021/11/12 15:12:11 brad Exp $ */
/*
* Copyright (c) 2017 Brad Spencer
@@ -17,7 +17,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: si70xx.c,v 1.9 2021/11/11 14:16:04 brad Exp $");
+__KERNEL_RCSID(0, "$NetBSD: si70xx.c,v 1.10 2021/11/12 15:12:11 brad Exp $");
/*
Driver for the Silicon Labs SI7013/SI7020/SI7021, HTU21D and SHT21
@@ -609,6 +609,7 @@ si70xx_attach(device_t parent, device_t
uint8_t testcrcpt1[4];
uint8_t testcrcpt2[4];
uint8_t crc1 = 0, crc2 = 0;
+ bool validcrcpt1, validcrcpt2;
uint8_t readcrc1 = 0, readcrc2 = 0;
uint8_t fwversion = 0, model, heaterregister;
@@ -622,7 +623,7 @@ si70xx_attach(device_t parent, device_t
#ifdef HAVE_I2C_EXECV
sc->sc_clockstretch = 2048;
#endif
- sc->sc_readattempts = 25;
+ sc->sc_readattempts = 40;
sc->sc_ignorecrc = false;
sc->sc_sme = NULL;
sc->sc_noheater = false;
@@ -665,11 +666,24 @@ si70xx_attach(device_t parent, device_t
testcrcpt1[3] = buf[6];
readcrc1 = buf[7];
crc1 = si70xx_crc(testcrcpt1, 4);
+ /* A "real" SI70xx has the CRC cover the entire first part of the
+ * serial number. An HTU21D has the CRC broken out into each
+ * part of the serial number.
+ */
+ validcrcpt1 = (readcrc1 == crc1);
+ if (! validcrcpt1) {
+ validcrcpt1 = (si70xx_crc([0],1) == buf[1] &&
+ si70xx_crc([1],1) == buf[3] &&
+ si70xx_crc([2],1) == buf[5] &&
+ si70xx_crc([3],1) == buf[7]);
+ DPRINTF(sc, 2, ("%s: Part 1 SN CRC was not valid for real type, "
+ "check clone: %d\n", device_xname(sc->sc_dev), validcrcpt1));
+ }
DPRINTF(sc, 2, ("%s: read 1 values: %02x%02x%02x%02x%02x%02x%02x%02x "
- "- %02x\n", device_xname(sc->sc_dev), buf[0], buf[1],
+ "- %02x -- %d\n", device_xname(sc->sc_dev), buf[0], buf[1],
buf[2], buf[3], buf[4], buf[5], buf[6], buf[7],
- crc1));
+ crc1, validcrcpt1));
error = si70xx_cmd2(sc, SI70XX_READ_ID_PT2A, SI70XX_READ_ID_PT2B,
buf, 8);
@@ -684,16 +698,30 @@ si70xx_attach(device_t parent, device_t
testcrcpt2[3] = buf[4];
readcrc2 = buf[5];
crc2 = si70xx_crc(testcrcpt2, 4);
+ /* It is even stranger for this part of the serial number. A "real"
+ * SI70XX will have a single CRC for the entire second part, but
+ * an HTU21D has a CRC for each word in this case.
+ *
+ * The datasheet actually agrees with the HTU21D case, and not the "real"
+ * chip.
+ */
+ validcrcpt2 = (readcrc2 == crc2);
+ if (! validcrcpt2) {
+ validcrcpt2 = (si70xx_crc([0],2) == buf[2] &&
+ si70xx_crc([2],2) == buf[5]);
+ DPRINTF(sc, 2, ("%s: Part 2 SN CRC was not valid for real type, "
+ "check clone: %d\n", device_xname(sc->sc_dev), validcrcpt2));
+ }
- DPRINTF(sc, 2, ("%s: read 2 values: %02x%02x%02x%02x%02x%02x - %02x\n",
+ DPRINTF(sc, 2, ("%s: read 2 values: %02x%02x%02x%02x%02x%02x - %02x -- %d\n",
device_xname(sc->sc_dev), buf[0], buf[1], buf[2],
- buf[3], buf[4], buf[5], crc2));
+ buf[3], buf[4], buf[5], crc2, validcrcpt2));
error = si70xx_cmd2(sc, SI70XX_READ_FW_VERA, SI70XX_READ_FW_VERB,
buf, 8);
if (error) {
- aprint_error_dev(self, "Failed to read firmware version: %d\n",
+
