CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: simonb Date: Tue Nov 8 13:47:09 UTC 2022 Modified Files: src/sys/arch/riscv/include: sysreg.h Log Message: Parentheses police. To generate a diff of this commit: cvs rdiff -u -r1.20 -r1.21 src/sys/arch/riscv/include/sysreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/include/sysreg.h diff -u src/sys/arch/riscv/include/sysreg.h:1.20 src/sys/arch/riscv/include/sysreg.h:1.21 --- src/sys/arch/riscv/include/sysreg.h:1.20 Tue Nov 8 13:35:32 2022 +++ src/sys/arch/riscv/include/sysreg.h Tue Nov 8 13:47:09 2022 @@ -1,4 +1,4 @@ -/* $NetBSD: sysreg.h,v 1.20 2022/11/08 13:35:32 simonb Exp $ */ +/* $NetBSD: sysreg.h,v 1.21 2022/11/08 13:47:09 simonb Exp $ */ /* * Copyright (c) 2014 The NetBSD Foundation, Inc. @@ -210,8 +210,8 @@ riscvreg_status_set(uint32_t __mask) } // Cause register -#define CAUSE_INTERRUPT_P(cause) ((cause) & __BIT(XLEN-1))) -#define CAUSE_CODE(cause) ((cause) & __BITS((XLEN-2), 0)) +#define CAUSE_INTERRUPT_P(cause) ((cause) & __BIT(XLEN-1)) +#define CAUSE_CODE(cause) ((cause) & __BITS(XLEN-2, 0)) // Cause register - exceptions #define CAUSE_FETCH_MISALIGNED 0
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: simonb Date: Tue Nov 8 13:47:09 UTC 2022 Modified Files: src/sys/arch/riscv/include: sysreg.h Log Message: Parentheses police. To generate a diff of this commit: cvs rdiff -u -r1.20 -r1.21 src/sys/arch/riscv/include/sysreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: simonb Date: Tue Nov 8 13:35:32 UTC 2022 Modified Files: src/sys/arch/riscv/include: sysreg.h Log Message: Add cause register trap types, and some macros to access cause register fields. To generate a diff of this commit: cvs rdiff -u -r1.19 -r1.20 src/sys/arch/riscv/include/sysreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: simonb Date: Tue Nov 8 13:35:32 UTC 2022 Modified Files: src/sys/arch/riscv/include: sysreg.h Log Message: Add cause register trap types, and some macros to access cause register fields. To generate a diff of this commit: cvs rdiff -u -r1.19 -r1.20 src/sys/arch/riscv/include/sysreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/include/sysreg.h diff -u src/sys/arch/riscv/include/sysreg.h:1.19 src/sys/arch/riscv/include/sysreg.h:1.20 --- src/sys/arch/riscv/include/sysreg.h:1.19 Tue Nov 8 12:48:28 2022 +++ src/sys/arch/riscv/include/sysreg.h Tue Nov 8 13:35:32 2022 @@ -1,4 +1,4 @@ -/* $NetBSD: sysreg.h,v 1.19 2022/11/08 12:48:28 skrll Exp $ */ +/* $NetBSD: sysreg.h,v 1.20 2022/11/08 13:35:32 simonb Exp $ */ /* * Copyright (c) 2014 The NetBSD Foundation, Inc. @@ -210,6 +210,10 @@ riscvreg_status_set(uint32_t __mask) } // Cause register +#define CAUSE_INTERRUPT_P(cause) ((cause) & __BIT(XLEN-1))) +#define CAUSE_CODE(cause) ((cause) & __BITS((XLEN-2), 0)) + +// Cause register - exceptions #define CAUSE_FETCH_MISALIGNED 0 #define CAUSE_FETCH_ACCESS 1 #define CAUSE_ILLEGAL_INSTRUCTION 2 @@ -218,8 +222,8 @@ riscvreg_status_set(uint32_t __mask) #define CAUSE_LOAD_ACCESS 5 #define CAUSE_STORE_MISALIGNED 6 #define CAUSE_STORE_ACCESS 7 -#define CAUSE_SYSCALL 8 #define CAUSE_USER_ECALL 8 +#define CAUSE_SYSCALL CAUSE_USER_ECALL /* convenience alias */ #define CAUSE_SUPERVISOR_ECALL 9 /* 10 is reserved */ #define CAUSE_MACHINE_ECALL 11 @@ -227,7 +231,15 @@ riscvreg_status_set(uint32_t __mask) #define CAUSE_LOAD_PAGE_FAULT 13 /* 14 is Reserved */ #define CAUSE_STORE_PAGE_FAULT 15 -/* >= 16 is reserved */ +/* >= 16 is reserved/custom */ + +// Cause register - traps +#define IRQ_SUPERVISOR_SOFTWARE 1 +#define IRQ_MACHINE_SOFTWARE 3 +#define IRQ_SUPERVISOR_TIMER 5 +#define IRQ_MACHINE_TIMER 7 +#define IRQ_SUPERVISOR_EXTERNAL 9 +#define IRQ_MACHINE_EXTERNAL 11 static inline uint64_t riscvreg_cycle_read(void)
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: simonb Date: Tue Nov 8 13:34:18 UTC 2022 Modified Files: src/sys/arch/riscv/include: types.h Log Message: Add a #define for XLEN, the RISC-V native base integer ISA width. To generate a diff of this commit: cvs rdiff -u -r1.14 -r1.15 src/sys/arch/riscv/include/types.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/include/types.h diff -u src/sys/arch/riscv/include/types.h:1.14 src/sys/arch/riscv/include/types.h:1.15 --- src/sys/arch/riscv/include/types.h:1.14 Tue Oct 18 07:07:51 2022 +++ src/sys/arch/riscv/include/types.h Tue Nov 8 13:34:17 2022 @@ -1,4 +1,4 @@ -/* $NetBSD: types.h,v 1.14 2022/10/18 07:07:51 skrll Exp $ */ +/* $NetBSD: types.h,v 1.15 2022/11/08 13:34:17 simonb Exp $ */ /*- * Copyright (c) 2014 The NetBSD Foundation, Inc. @@ -38,6 +38,9 @@ #if defined(_KERNEL) || defined(_KMEMUSER) || defined(_KERNTYPES) || defined(_STANDALONE) +/* XLEN is the native base integer ISA width */ +#define XLEN (sizeof(long) * NBBY) + typedef __uint64_t paddr_t; typedef __uint64_t psize_t; #define PRIxPADDR PRIx64
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: simonb Date: Tue Nov 8 13:34:18 UTC 2022 Modified Files: src/sys/arch/riscv/include: types.h Log Message: Add a #define for XLEN, the RISC-V native base integer ISA width. To generate a diff of this commit: cvs rdiff -u -r1.14 -r1.15 src/sys/arch/riscv/include/types.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/mips/include
Module Name:src Committed By: simonb Date: Tue Nov 8 13:04:49 UTC 2022 Modified Files: src/sys/arch/mips/include: mipsNN.h Log Message: Fix tyop in __BITS for the MIPSNN_MTI_CFG7_PREF_MASK macro. To generate a diff of this commit: cvs rdiff -u -r1.12 -r1.13 src/sys/arch/mips/include/mipsNN.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/mips/include/mipsNN.h diff -u src/sys/arch/mips/include/mipsNN.h:1.12 src/sys/arch/mips/include/mipsNN.h:1.13 --- src/sys/arch/mips/include/mipsNN.h:1.12 Sun Aug 2 23:20:25 2020 +++ src/sys/arch/mips/include/mipsNN.h Tue Nov 8 13:04:49 2022 @@ -1,4 +1,4 @@ -/* $NetBSD: mipsNN.h,v 1.12 2020/08/02 23:20:25 simonb Exp $ */ +/* $NetBSD: mipsNN.h,v 1.13 2022/11/08 13:04:49 simonb Exp $ */ /* * Copyright 2000, 2001 @@ -677,7 +677,7 @@ #define MIPSNN_MTI_CFG7_AR __BIT(16) /* 1: no virt aliases */ /* "PREF" (R/W): Instruction Prefetching (74K, 1074K). */ -#define MIPSNN_MTI_CFG7_PREF_MASK __BITS(12:11) +#define MIPSNN_MTI_CFG7_PREF_MASK __BITS(12,11) #define MIPSNN_MTI_CFG7_PREF_SHIFT 11 #define MIPSNN_MTI_CFG7_PREF_DISABLE 0 #define MIPSNN_MTI_CFG7_PREF_ONELINE 1
CVS commit: src/sys/arch/mips/include
Module Name:src Committed By: simonb Date: Tue Nov 8 13:04:49 UTC 2022 Modified Files: src/sys/arch/mips/include: mipsNN.h Log Message: Fix tyop in __BITS for the MIPSNN_MTI_CFG7_PREF_MASK macro. To generate a diff of this commit: cvs rdiff -u -r1.12 -r1.13 src/sys/arch/mips/include/mipsNN.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: skrll Date: Tue Nov 8 12:48:28 UTC 2022 Modified Files: src/sys/arch/riscv/include: sysreg.h Log Message: whitepsace nit To generate a diff of this commit: cvs rdiff -u -r1.18 -r1.19 src/sys/arch/riscv/include/sysreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/include/sysreg.h diff -u src/sys/arch/riscv/include/sysreg.h:1.18 src/sys/arch/riscv/include/sysreg.h:1.19 --- src/sys/arch/riscv/include/sysreg.h:1.18 Sat Oct 15 06:53:49 2022 +++ src/sys/arch/riscv/include/sysreg.h Tue Nov 8 12:48:28 2022 @@ -1,4 +1,4 @@ -/* $NetBSD: sysreg.h,v 1.18 2022/10/15 06:53:49 skrll Exp $ */ +/* $NetBSD: sysreg.h,v 1.19 2022/11/08 12:48:28 skrll Exp $ */ /* * Copyright (c) 2014 The NetBSD Foundation, Inc. @@ -144,7 +144,7 @@ riscvreg_fcsr_write_frm(uint32_t __new) /* Supervisor interrupt registers */ /* ... interrupt pending register (sip) */ - /* Bit (XLEN-1)-10 is WIRI */ + /* Bit (XLEN-1) - 10 is WIRI */ #define SIP_SEIP __BIT(9) #define SIP_UEIP __BIT(8) /* Bit 7-6 is WIRI */
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: skrll Date: Tue Nov 8 12:48:28 UTC 2022 Modified Files: src/sys/arch/riscv/include: sysreg.h Log Message: whitepsace nit To generate a diff of this commit: cvs rdiff -u -r1.18 -r1.19 src/sys/arch/riscv/include/sysreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/doc
Module Name:src Committed By: nia Date: Tue Nov 8 09:30:11 UTC 2022 Modified Files: src/doc: CHANGES Log Message: doc: various changes from various developers for late october To generate a diff of this commit: cvs rdiff -u -r1.2928 -r1.2929 src/doc/CHANGES Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/doc/CHANGES diff -u src/doc/CHANGES:1.2928 src/doc/CHANGES:1.2929 --- src/doc/CHANGES:1.2928 Sun Oct 30 01:05:47 2022 +++ src/doc/CHANGES Tue Nov 8 09:30:11 2022 @@ -1,4 +1,4 @@ -# LIST OF CHANGES FROM LAST RELEASE: <$Revision: 1.2928 $> +# LIST OF CHANGES FROM LAST RELEASE: <$Revision: 1.2929 $> # # # [Note: This file does not mention every change made to the NetBSD source tree. @@ -702,6 +702,8 @@ Changes from NetBSD 9.0 to NetBSD 10.0: OpenSSH: Import 9.1. [christos 20221005] postfix(1): Import version 3.7.3. [christos 20221008] ntp: Import ntp 4.2.8p15. [christos 20221009] + xhci(4): Support xHCI bus devices with only USB 2 ports. + [msaitoh 20221011] tzdata: updated to 2022e (using the 2022egtz fork) [kre 20221013] tzcode: Updated to 2022e. [christos 20221015] zlib(3): Import 1.2.13 [christos 20221015] @@ -709,8 +711,22 @@ Changes from NetBSD 9.0 to NetBSD 10.0: recent. [mrg 20221015] evbarm: Add support for Oracle Cloud virtual machines. [jmcneill 20221015] + date(1): Add -f option to set the time. From FreeBSD. + [christos 20221022] + tty(4), console(4): Remove the big kernel lock from ttycons. + [riastradh 20221025] + amdccp(4): Add AMD F17/1x and F17/9x CCP(PSP) support. + [msaitoh 20221026] + evbarm: Removed support for legacy (non-FDT) OMAP boards, + including the Gumstix, Hawkboard, Pandaboard, and + TI OMAP 2420, 2430, and 5912 OSK eval boards. + [jmcneill 20221029] + pgrep(1): Add a -q option to not print anything, similar + to grep -q. [simonb 20221029] libc: put reallocarray(3) in the public namespace [wiz 20221028] evbarm: Update Xilinx Zynq-7000 SoC support to use FDT based configuration. [jmcneill 20221028] tzcode: Updated to 2022f. [christos 20221029] tzdata: updated to 2022f (using the 2022fgtz fork) [kre 20221030] + regerror(3): Allow null errbuf if errbuf_size is zero, + as documented and in POSIX. [riastradh 20221105]
CVS commit: src/doc
Module Name:src Committed By: nia Date: Tue Nov 8 09:30:11 UTC 2022 Modified Files: src/doc: CHANGES Log Message: doc: various changes from various developers for late october To generate a diff of this commit: cvs rdiff -u -r1.2928 -r1.2929 src/doc/CHANGES Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
