Re: CVS commit: [matt-nb5-mips64] src/sys/arch/mips
On Wed, Dec 22, 2010 at 06:13:37AM +, Matt Thomas wrote: Log Message: Rework how fixups are processed. Inside of generating a table, we just scan kernel text for jumps to locations between (__stub_start, __stub_end] and if found, we actually decode the instructions in the stub to find out where the stub would eventually jump to and then patch the original jump to jump directly to it bypassing the stub. This is slightly slower than the previous method but it's a simplier and new stubs get automagically handled. Isn't this a bit dangerous if anything other than code ends up in the kernel text ? David -- David Laight: da...@l8s.co.uk
Re: CVS commit: [matt-nb5-mips64] src/sys/arch/mips/mips
Hi Cliff, A couple of things with these changes: Module Name:src Committed By: cliff Date: Thu Jun 10 00:32:11 UTC 2010 Modified Files: src/sys/arch/mips/include [matt-nb5-mips64]: locore.h Log Message: - add lsw_bus_error to struct locoresw, provides hook to call for chip-specific bus error handling/decode from e.g. trap() and Module Name: src Committed By: cliff Date: Thu Jun 10 00:33:51 UTC 2010 Modified Files: src/sys/arch/mips/mips [matt-nb5-mips64]: trap.c Log Message: - in trap(), if traptype is bus error, call chip-specific bus error handler in locoresw: (*mips_locoresw.lsw_bus_error)(cause) 1: It's not obvious to me if you're trying to provide for a replacement bus error handler (as the commit seems to imply) or an assistant to the current bus error handler (which is what the code does). 2: With: if ((TRAPTYPE(cause) == 6) || (TRAPTYPE(cause) == 7)) (void)(*mips_locoresw.lsw_bus_error)(cause); please please avoid magic numbers - the intent of this isn't obvious at all. 3: It appears that only sbmips actually sets the lsw_bus_error handler, so a bus error on any other arch would NULL-deference and panic? 4: With: #ifdef MIPS3_PLUS #define TRAPTYPE(x) (((x) MIPS3_CR_EXC_CODE) MIPS_CR_EXC_CODE_SHIFT) #else #define TRAPTYPE(x) (((x) MIPS1_CR_EXC_CODE) MIPS_CR_EXC_CODE_SHIFT) #endif This looks like it assumes MIPS1 or MIPS3+ at compile time, but we can have one kernel that can run on both. This needs to be a runtime thing. Maybe create a macro/inline function to extract the EXC part of a cause reg in mips/include/cpureg.h too? 5: Is this worth generalising? Someone might want to add other CPU specific trap error handlers so it might be better doing something like: if (mips_locoresw.lsw_trap_error) (void)(*mips_locoresw.lsw_trap_error)(status, cause, vaddr, opc); and letting the handler determine which exception codes to deal with. This isn't in time critical code (it either panics or drops to ddb/kgdb) to the if () check doesn't hurt. This would also fix 3 above. Cheers, Simon.
Re: CVS commit: [matt-nb5-mips64] src/sys/arch/mips/include
Matt Thomas wrote: Module Name: src Committed By: matt Date: Tue May 11 21:51:34 UTC 2010 Modified Files: src/sys/arch/mips/include [matt-nb5-mips64]: locore.h Log Message: Need to turn KX for N32 kernels with mips3_lw_a64 and mips3_sw_a64 +#elif defined(__mips_n32) + uint32_t sr = mips_cp0_status_read(); + mips_cp0_status_write((sr ~MIPS_SR_INT_IE) | MIPS3_SR_KX); + rv = *(const uint32_t *)addr; Erm, doesn't that cast toss away the high 32-bits of the address you're try to load/store from/to? Cheers, Simon.
Re: CVS commit: [matt-nb5-mips64] src/sys/arch/mips/include
Matt Thomas wrote: Module Name: src Committed By: matt Date: Tue May 11 22:08:02 UTC 2010 Modified Files: src/sys/arch/mips/include [matt-nb5-mips64]: locore.h Log Message: Use assembly since deref a 64bit value as a pointer does not make a 32bit compiler happy. Dang, ignore my previous because this code is a little different. + __asm volatile(lw %0, 0(%1) : =r(rv) : d(addr)); d is listed as General-purpose integer register in the gcc docs. Does the new code pass the full 64-bits of addr in when compiled on an ABI where an int is 32-bits even though a full register is 64-bits? Cheers, Simon.
Re: CVS commit: [matt-nb5-mips64] src/sys/arch/mips/include
On May 12, 2010, at 5:19 AM, Simon Burge wrote: Matt Thomas wrote: Module Name: src Committed By:matt Date:Tue May 11 22:08:02 UTC 2010 Modified Files: src/sys/arch/mips/include [matt-nb5-mips64]: locore.h Log Message: Use assembly since deref a 64bit value as a pointer does not make a 32bit compiler happy. Dang, ignore my previous because this code is a little different. + __asm volatile(lw %0, 0(%1) : =r(rv) : d(addr)); d is listed as General-purpose integer register in the gcc docs. Does the new code pass the full 64-bits of addr in when compiled on an ABI where an int is 32-bits even though a full register is 64-bits? Yes.
Re: CVS commit: [matt-nb5-mips64] src/sys/arch/mips/mips
On May 4, 2010, at 5:30 PM, Simon Burge wrote: Matt Thomas wrote: Modified Files: src/sys/arch/mips/mips [matt-nb5-mips64]: pmap_segtab.c Log Message: Cleanup segtab allocation. Add some counters to monitor memory usage. +uint32_t nget_segtab; +uint32_t nput_segtab; +uint32_t npage_segtab; How quickly could these wrap? Not very and they are really intended for short use. 4B lwp creations :) I'm not worried about wrapping.
CVS commit: [matt-nb5-mips64] src/sys/arch/evbmips/rmixl
Module Name:src Committed By: matt Date: Tue Mar 9 02:02:53 UTC 2010 Modified Files: src/sys/arch/evbmips/rmixl [matt-nb5-mips64]: machdep.c Log Message: Use dmfc0 k0,cop0_osscratch if _LP64 To generate a diff of this commit: cvs rdiff -u -r1.1.2.22 -r1.1.2.23 src/sys/arch/evbmips/rmixl/machdep.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/evbmips/rmixl/machdep.c diff -u src/sys/arch/evbmips/rmixl/machdep.c:1.1.2.22 src/sys/arch/evbmips/rmixl/machdep.c:1.1.2.23 --- src/sys/arch/evbmips/rmixl/machdep.c:1.1.2.22 Sat Feb 27 21:26:28 2010 +++ src/sys/arch/evbmips/rmixl/machdep.c Tue Mar 9 02:02:53 2010 @@ -1,4 +1,4 @@ -/* $NetBSD: machdep.c,v 1.1.2.22 2010/02/27 21:26:28 matt Exp $ */ +/* $NetBSD: machdep.c,v 1.1.2.23 2010/03/09 02:02:53 matt Exp $ */ /* * Copyright 2001, 2002 Wasabi Systems, Inc. @@ -112,7 +112,7 @@ */ #include sys/cdefs.h -__KERNEL_RCSID(0, $NetBSD: machdep.c,v 1.1.2.22 2010/02/27 21:26:28 matt Exp $); +__KERNEL_RCSID(0, $NetBSD: machdep.c,v 1.1.2.23 2010/03/09 02:02:53 matt Exp $); #include opt_ddb.h #include opt_com.h @@ -469,8 +469,11 @@ * relative from the start of struct cpu_info. */ - /* [0] = mfc0 rX, $22 (OSScratch) */ + /* [0] = [d]mfc0 rX, $22 (OSScratch) */ new_insns[0] = (020 26) +#ifdef _LP64 + | (1 21) /* double move */ +#endif | (new_insns[0] 0x001f) | (MIPS_COP_0_OSSCRATCH 11) | (0 0);
CVS commit: [matt-nb5-mips64] src/sys/arch/evbmips/rmixl
Module Name:src Committed By: matt Date: Tue Mar 9 02:04:46 UTC 2010 Modified Files: src/sys/arch/evbmips/rmixl [matt-nb5-mips64]: machdep.c Log Message: Use dmtc0 too. To generate a diff of this commit: cvs rdiff -u -r1.1.2.23 -r1.1.2.24 src/sys/arch/evbmips/rmixl/machdep.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/evbmips/rmixl/machdep.c diff -u src/sys/arch/evbmips/rmixl/machdep.c:1.1.2.23 src/sys/arch/evbmips/rmixl/machdep.c:1.1.2.24 --- src/sys/arch/evbmips/rmixl/machdep.c:1.1.2.23 Tue Mar 9 02:02:53 2010 +++ src/sys/arch/evbmips/rmixl/machdep.c Tue Mar 9 02:04:46 2010 @@ -1,4 +1,4 @@ -/* $NetBSD: machdep.c,v 1.1.2.23 2010/03/09 02:02:53 matt Exp $ */ +/* $NetBSD: machdep.c,v 1.1.2.24 2010/03/09 02:04:46 matt Exp $ */ /* * Copyright 2001, 2002 Wasabi Systems, Inc. @@ -112,7 +112,7 @@ */ #include sys/cdefs.h -__KERNEL_RCSID(0, $NetBSD: machdep.c,v 1.1.2.23 2010/03/09 02:02:53 matt Exp $); +__KERNEL_RCSID(0, $NetBSD: machdep.c,v 1.1.2.24 2010/03/09 02:04:46 matt Exp $); #include opt_ddb.h #include opt_com.h @@ -448,7 +448,7 @@ /* * Fix up the exception vector to use COP0 OSSCRATCH0 */ - __asm __volatile(mtc0 %0,$%1 + __asm __volatile(dmtc0 %0,$%1 :: r(cpu_info_store), n(MIPS_COP_0_OSSCRATCH)); mips_fixup_exceptions(rmixl_fixup_cop0_oscratch); #endif
CVS commit: [matt-nb5-mips64] src/sys/arch/mips
Module Name:src Committed By: matt Date: Mon Mar 1 19:26:01 UTC 2010 Modified Files: src/sys/arch/mips/include [matt-nb5-mips64]: locore.h src/sys/arch/mips/mips [matt-nb5-mips64]: mips_fixup.c spl_stubs.c Log Message: Rework fixups support a bit (add a convience macro, require fixups to be sorted). To generate a diff of this commit: cvs rdiff -u -r1.78.36.1.2.18 -r1.78.36.1.2.19 \ src/sys/arch/mips/include/locore.h cvs rdiff -u -r1.1.2.4 -r1.1.2.5 src/sys/arch/mips/mips/mips_fixup.c cvs rdiff -u -r1.1.2.1 -r1.1.2.2 src/sys/arch/mips/mips/spl_stubs.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [matt-nb5-mips64] src/sys/arch/mips
Module Name:src
Committed By: matt
Date: Mon Mar 1 19:26:01 UTC 2010
Modified Files:
src/sys/arch/mips/include [matt-nb5-mips64]: locore.h
src/sys/arch/mips/mips [matt-nb5-mips64]: mips_fixup.c spl_stubs.c
Log Message:
Rework fixups support a bit (add a convience macro, require fixups to be
sorted).
To generate a diff of this commit:
cvs rdiff -u -r1.78.36.1.2.18 -r1.78.36.1.2.19 \
src/sys/arch/mips/include/locore.h
cvs rdiff -u -r1.1.2.4 -r1.1.2.5 src/sys/arch/mips/mips/mips_fixup.c
cvs rdiff -u -r1.1.2.1 -r1.1.2.2 src/sys/arch/mips/mips/spl_stubs.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/include/locore.h
diff -u src/sys/arch/mips/include/locore.h:1.78.36.1.2.18 src/sys/arch/mips/include/locore.h:1.78.36.1.2.19
--- src/sys/arch/mips/include/locore.h:1.78.36.1.2.18 Sun Feb 28 23:45:07 2010
+++ src/sys/arch/mips/include/locore.h Mon Mar 1 19:26:00 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.h,v 1.78.36.1.2.18 2010/02/28 23:45:07 matt Exp $ */
+/* $NetBSD: locore.h,v 1.78.36.1.2.19 2010/03/01 19:26:00 matt Exp $ */
/*
* This file should not be included by MI code!!!
@@ -45,13 +45,26 @@
void softint_process(uint32_t);
void softint_fast_dispatch(struct lwp *, int);
+/*
+ * Convert an address to an offset used in a MIPS jump instruction. The offset
+ * contains the low 28 bits (allowing a jump to anywhere within the same 256MB
+ * segment of address space) of the address but since mips instructions are
+ * always on a 4 byte boundary the low 2 bits are always zero so the 28 bits
+ * get shifted right by 2 bits leaving us with a 26 bit result. To make the
+ * offset, we shift left to clear the upper four bits and then right by 6.
+ */
+#define fixup_addr2offset(x) uint32_t)(uintptr_t)(x)) 4) 6)
typedef bool (*mips_fixup_callback_t)(int32_t, uint32_t [2]);
+struct mips_jump_fixup_info {
+ uint32_t jfi_stub;
+ uint32_t jfi_real;
+};
void fixup_splcalls(void);/* splstubs.c */
bool mips_fixup_exceptions(mips_fixup_callback_t);
bool mips_fixup_zero_relative(int32_t, uint32_t [2]);
-void mips_fixup_stubs(uint32_t *, uint32_t *, const uint32_t *,
- const uint32_t *, size_t);
+void mips_fixup_stubs(uint32_t *, uint32_t *,
+ const struct mips_jump_fixup_info *, size_t);
void fixup_mips_cpu_switch_resume(void);
void mips_cpu_switch_resume(struct lwp *);
Index: src/sys/arch/mips/mips/mips_fixup.c
diff -u src/sys/arch/mips/mips/mips_fixup.c:1.1.2.4 src/sys/arch/mips/mips/mips_fixup.c:1.1.2.5
--- src/sys/arch/mips/mips/mips_fixup.c:1.1.2.4 Sun Feb 28 15:32:32 2010
+++ src/sys/arch/mips/mips/mips_fixup.c Mon Mar 1 19:26:01 2010
@@ -29,7 +29,7 @@
#include sys/cdefs.h
-__KERNEL_RCSID(0, $NetBSD: mips_fixup.c,v 1.1.2.4 2010/02/28 15:32:32 snj Exp $);
+__KERNEL_RCSID(0, $NetBSD: mips_fixup.c,v 1.1.2.5 2010/03/01 19:26:01 matt Exp $);
#include sys/param.h
@@ -175,44 +175,53 @@
#define OPCODE_J 002
#define OPCODE_JAL 003
-static void
-fixup_mips_jump(uint32_t *insnp, uint32_t stub, uint32_t real)
+static inline void
+fixup_mips_jump(uint32_t *insnp, const struct mips_jump_fixup_info *jfi)
{
uint32_t insn = *insnp;
KASSERT((insn (26+1)) == (OPCODE_J 1));
- KASSERT((insn 6) == (stub 4));
+ KASSERT((insn 6) == (jfi-jfi_stub 6));
- insn ^= (stub ^ real) 4 6;
+ insn ^= (jfi-jfi_stub ^ jfi-jfi_real);
- KASSERT((insn 6) == (real 4));
+ KASSERT((insn 6) == (jfi-jfi_real 6));
+#ifdef DEBUG
+#if 0
+ int32_t va = ((intptr_t) insnp 26) 26;
+ printf(%s: %08x: [%08x] %s %08x - [%08x] %s %08x\n,
+ __func__, (int32_t)(intptr_t)insnp,
+ insn, opcode == OPCODE_J ? j : jal,
+ va | (jfi-jfo_stub 2),
+ *insnp, opcode == OPCODE_J ? j : jal,
+ va | (jfi-jfi_real 2));
+#endif
+#endif
*insnp = insn;
}
void
mips_fixup_stubs(uint32_t *start, uint32_t *end,
- const uint32_t *stub_offsets, const uint32_t *real_offsets,
- size_t noffsets)
+ const struct mips_jump_fixup_info *fixups,
+ size_t nfixups)
{
- uint32_t min_offset = 0x03ff;
- uint32_t max_offset = 0x;
+ const uint32_t min_offset = fixups[0].jfi_stub;
+ const uint32_t max_offset = fixups[nfixups-1].jfi_stub;
#ifdef DEBUG
- size_t fixups = 0;
+ size_t fixups_done = 0;
uint32_t cycles = (CPUISMIPS3 ? mips3_cp0_count_read() : 0);
#endif
+#ifdef DIAGNOGSTIC
/*
- * Find the lowest and highest jumps we will be replacing. We don't
- * need to do it but it does make weeding out the non-matching jumps
- * faster.
+ * Verify the fixup list is sorted from low stub to high stub.
*/
- for (size_t i = 0; i noffsets; i++) {
- if (stub_offsets[i] min_offset)
- min_offset = stub_offsets[i];
- if (max_offset stub_offsets[i])
- max_offset = stub_offsets[i];
+ for (const struct mips_jump_fixup_info *jfi = fixups + 1;
+ jfi fixups + nfixups; jfi++) {
+ KASSERT(jfi[-1].jfi_stub jfi[0].jfi_stub);
}
+#endif
for
CVS commit: [matt-nb5-mips64] src/sys/arch/mips/mips
Module Name:src
Committed By: matt
Date: Mon Mar 1 19:26:57 UTC 2010
Modified Files:
src/sys/arch/mips/mips [matt-nb5-mips64]: mips_fpu.c
Log Message:
Put fp_lock and fp_cv in a common structure.
To generate a diff of this commit:
cvs rdiff -u -r1.1.2.1 -r1.1.2.2 src/sys/arch/mips/mips/mips_fpu.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/mips/mips_fpu.c
diff -u src/sys/arch/mips/mips/mips_fpu.c:1.1.2.1 src/sys/arch/mips/mips/mips_fpu.c:1.1.2.2
--- src/sys/arch/mips/mips/mips_fpu.c:1.1.2.1 Sun Feb 28 23:45:06 2010
+++ src/sys/arch/mips/mips/mips_fpu.c Mon Mar 1 19:26:57 2010
@@ -29,7 +29,7 @@
#include sys/cdefs.h
-__KERNEL_RCSID(0, $NetBSD: mips_fpu.c,v 1.1.2.1 2010/02/28 23:45:06 matt Exp $);
+__KERNEL_RCSID(0, $NetBSD: mips_fpu.c,v 1.1.2.2 2010/03/01 19:26:57 matt Exp $);
#include sys/param.h
#include sys/mutex.h
@@ -42,10 +42,14 @@
#include mips/regnum.h
#ifndef NOFPU
-kmutex_t fp_mutex __aligned(32);
+static struct {
+ kmutex_t fpx_mutex;
#ifdef MULTIPROCESSOR
-kcondvar_t fp_cv __aligned(32);
+ kcondvar_t fpx_cv;
#endif
+} fp_lockinfo __aligned(COHERENCY_UNIT);
+#define fp_mutex fp_lockinfo.fpx_mutex
+#define fp_cv fp_lockinfo.fpx_cv
#endif /* !NOFPU */
void
CVS commit: [matt-nb5-mips64] src/sys/arch/mips
Module Name:src Committed By: matt Date: Mon Mar 1 19:29:42 UTC 2010 Modified Files: src/sys/arch/mips/include [matt-nb5-mips64]: cpu.h locore.h src/sys/arch/mips/mips [matt-nb5-mips64]: cpu_subr.c genassym.cf locore_mips3.S mipsX_subr.S mips_machdep.c Log Message: Add secondary processor spinup support (cpu_trampoline is in locore_mips3.S). Nuke lse_boot_secondary_processors (not needed). Move cpu_info_store to cpu_subr.C To generate a diff of this commit: cvs rdiff -u -r1.90.16.24 -r1.90.16.25 src/sys/arch/mips/include/cpu.h cvs rdiff -u -r1.78.36.1.2.19 -r1.78.36.1.2.20 \ src/sys/arch/mips/include/locore.h cvs rdiff -u -r1.1.2.1 -r1.1.2.2 src/sys/arch/mips/mips/cpu_subr.c cvs rdiff -u -r1.44.12.20 -r1.44.12.21 src/sys/arch/mips/mips/genassym.cf cvs rdiff -u -r1.93.38.7 -r1.93.38.8 src/sys/arch/mips/mips/locore_mips3.S cvs rdiff -u -r1.26.36.1.2.29 -r1.26.36.1.2.30 \ src/sys/arch/mips/mips/mipsX_subr.S cvs rdiff -u -r1.205.4.1.2.1.2.39 -r1.205.4.1.2.1.2.40 \ src/sys/arch/mips/mips/mips_machdep.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [matt-nb5-mips64] src/sys/arch/mips/mips
Module Name:src Committed By: matt Date: Mon Mar 1 23:53:26 UTC 2010 Modified Files: src/sys/arch/mips/mips [matt-nb5-mips64]: pmap_tlb.c Log Message: Fix KASSERT botch. To generate a diff of this commit: cvs rdiff -u -r1.1.2.8 -r1.1.2.9 src/sys/arch/mips/mips/pmap_tlb.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [matt-nb5-mips64] src/sys/arch/mips/mips
Module Name:src Committed By: matt Date: Mon Mar 1 23:53:26 UTC 2010 Modified Files: src/sys/arch/mips/mips [matt-nb5-mips64]: pmap_tlb.c Log Message: Fix KASSERT botch. To generate a diff of this commit: cvs rdiff -u -r1.1.2.8 -r1.1.2.9 src/sys/arch/mips/mips/pmap_tlb.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/mips/mips/pmap_tlb.c diff -u src/sys/arch/mips/mips/pmap_tlb.c:1.1.2.8 src/sys/arch/mips/mips/pmap_tlb.c:1.1.2.9 --- src/sys/arch/mips/mips/pmap_tlb.c:1.1.2.8 Sun Feb 28 23:20:21 2010 +++ src/sys/arch/mips/mips/pmap_tlb.c Mon Mar 1 23:53:26 2010 @@ -1,4 +1,4 @@ -/* $NetBSD: pmap_tlb.c,v 1.1.2.8 2010/02/28 23:20:21 matt Exp $ */ +/* $NetBSD: pmap_tlb.c,v 1.1.2.9 2010/03/01 23:53:26 matt Exp $ */ /*- * Copyright (c) 2010 The NetBSD Foundation, Inc. @@ -31,7 +31,7 @@ #include sys/cdefs.h -__KERNEL_RCSID(0, $NetBSD: pmap_tlb.c,v 1.1.2.8 2010/02/28 23:20:21 matt Exp $); +__KERNEL_RCSID(0, $NetBSD: pmap_tlb.c,v 1.1.2.9 2010/03/01 23:53:26 matt Exp $); /* * Manages address spaces in a TLB. @@ -409,7 +409,7 @@ * next called for this pmap, it will allocate a new * ASID. */ - KASSERT((pm-pm_onproc ti-ti_cpu_mask) == 0); + KASSERT((curlwp-l_proc-p_vmspace-vm_map.pmap-pm_onproc ti-ti_cpu_mask) == 0); pmap_pai_reset(ti, pai, PAI_PMAP(pai, ti)); } break;
CVS commit: [matt-nb5-mips64] src/sys/arch/mips
Module Name:src
Committed By: matt
Date: Mon Mar 1 23:54:49 UTC 2010
Modified Files:
src/sys/arch/mips/include [matt-nb5-mips64]: locore.h
src/sys/arch/mips/mips [matt-nb5-mips64]: cpu_subr.c
Log Message:
Add a chip-dependent hook to locorew which cpu_hatch will call to do some
initialization that can only be done while running on the local CPU.
To generate a diff of this commit:
cvs rdiff -u -r1.78.36.1.2.20 -r1.78.36.1.2.21 \
src/sys/arch/mips/include/locore.h
cvs rdiff -u -r1.1.2.2 -r1.1.2.3 src/sys/arch/mips/mips/cpu_subr.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/include/locore.h
diff -u src/sys/arch/mips/include/locore.h:1.78.36.1.2.20 src/sys/arch/mips/include/locore.h:1.78.36.1.2.21
--- src/sys/arch/mips/include/locore.h:1.78.36.1.2.20 Mon Mar 1 19:29:41 2010
+++ src/sys/arch/mips/include/locore.h Mon Mar 1 23:54:49 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.h,v 1.78.36.1.2.20 2010/03/01 19:29:41 matt Exp $ */
+/* $NetBSD: locore.h,v 1.78.36.1.2.21 2010/03/01 23:54:49 matt Exp $ */
/*
* This file should not be included by MI code!!!
@@ -349,6 +349,7 @@
uintptr_t lsw_setfunc_trampoline;
int (*lsw_send_ipi)(struct cpu_info *, int);
void (*lsw_cpu_offline_md)(void);
+ void (*lsw_cpu_init)(struct cpu_info *);
};
struct mips_vmfreelist {
Index: src/sys/arch/mips/mips/cpu_subr.c
diff -u src/sys/arch/mips/mips/cpu_subr.c:1.1.2.2 src/sys/arch/mips/mips/cpu_subr.c:1.1.2.3
--- src/sys/arch/mips/mips/cpu_subr.c:1.1.2.2 Mon Mar 1 19:29:41 2010
+++ src/sys/arch/mips/mips/cpu_subr.c Mon Mar 1 23:54:49 2010
@@ -32,7 +32,7 @@
#include opt_multiprocessor.h
#include opt_sa.h
-__KERNEL_RCSID(0, $NetBSD: cpu_subr.c,v 1.1.2.2 2010/03/01 19:29:41 matt Exp $);
+__KERNEL_RCSID(0, $NetBSD: cpu_subr.c,v 1.1.2.3 2010/03/01 23:54:49 matt Exp $);
#include sys/param.h
#include sys/cpu.h
@@ -600,6 +600,12 @@
mips_icache_sync_all();
/*
+ * Let this CPU do its own initialization (for things that have to be
+ * done on the local CPU).
+ */
+ (*mips_locoresw.lsw_cpu_init)(ci);
+
+ /*
* Announce we are hatched
*/
atomic_or_ulong(cpus_hatched, cpu_mask);
CVS commit: [matt-nb5-mips64] src/sys/arch/mips
Module Name:src Committed By: matt Date: Mon Mar 1 23:54:49 UTC 2010 Modified Files: src/sys/arch/mips/include [matt-nb5-mips64]: locore.h src/sys/arch/mips/mips [matt-nb5-mips64]: cpu_subr.c Log Message: Add a chip-dependent hook to locorew which cpu_hatch will call to do some initialization that can only be done while running on the local CPU. To generate a diff of this commit: cvs rdiff -u -r1.78.36.1.2.20 -r1.78.36.1.2.21 \ src/sys/arch/mips/include/locore.h cvs rdiff -u -r1.1.2.2 -r1.1.2.3 src/sys/arch/mips/mips/cpu_subr.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [matt-nb5-mips64] src/sys/arch/sbmips
Module Name:src
Committed By: matt
Date: Mon Mar 1 23:55:49 UTC 2010
Modified Files:
src/sys/arch/sbmips/include [matt-nb5-mips64]: systemsw.h
src/sys/arch/sbmips/sbmips [matt-nb5-mips64]: cpu.c sb1250_icu.c
Log Message:
Add MP interrupts, IPIs, and secondary CPU spinup.
(compile tested only).
To generate a diff of this commit:
cvs rdiff -u -r1.7.28.3 -r1.7.28.4 src/sys/arch/sbmips/include/systemsw.h
cvs rdiff -u -r1.18.16.4 -r1.18.16.5 src/sys/arch/sbmips/sbmips/cpu.c
cvs rdiff -u -r1.9.36.5 -r1.9.36.6 src/sys/arch/sbmips/sbmips/sb1250_icu.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/sbmips/include/systemsw.h
diff -u src/sys/arch/sbmips/include/systemsw.h:1.7.28.3 src/sys/arch/sbmips/include/systemsw.h:1.7.28.4
--- src/sys/arch/sbmips/include/systemsw.h:1.7.28.3 Tue Feb 23 20:24:37 2010
+++ src/sys/arch/sbmips/include/systemsw.h Mon Mar 1 23:55:49 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: systemsw.h,v 1.7.28.3 2010/02/23 20:24:37 matt Exp $ */
+/* $NetBSD: systemsw.h,v 1.7.28.4 2010/03/01 23:55:49 matt Exp $ */
/*
* Copyright 2000, 2001
@@ -56,6 +56,7 @@
bool system_set_clockfns(void *, void (*)(void *));
void sb1250_icu_init(void);
+void sb1250_cpu_init(struct cpu_info *);
#define cpu_intr_establish(n,s,f,a) ((*systemsw.s_intr_establish)(n,s,f,a))
Index: src/sys/arch/sbmips/sbmips/cpu.c
diff -u src/sys/arch/sbmips/sbmips/cpu.c:1.18.16.4 src/sys/arch/sbmips/sbmips/cpu.c:1.18.16.5
--- src/sys/arch/sbmips/sbmips/cpu.c:1.18.16.4 Sun Feb 28 23:46:18 2010
+++ src/sys/arch/sbmips/sbmips/cpu.c Mon Mar 1 23:55:49 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.c,v 1.18.16.4 2010/02/28 23:46:18 matt Exp $ */
+/* $NetBSD: cpu.c,v 1.18.16.5 2010/03/01 23:55:49 matt Exp $ */
/*
* Copyright 2000, 2001
@@ -33,7 +33,7 @@
*/
#include sys/cdefs.h
-__KERNEL_RCSID(0, $NetBSD: cpu.c,v 1.18.16.4 2010/02/28 23:46:18 matt Exp $);
+__KERNEL_RCSID(0, $NetBSD: cpu.c,v 1.18.16.5 2010/03/01 23:55:49 matt Exp $);
#include opt_multiprocessor.h
@@ -52,6 +52,7 @@
#include mips/sibyte/include/sb1250_regs.h
#include mips/sibyte/include/sb1250_scd.h
#include mips/sibyte/dev/sbscdvar.h
+#include mips/cfe/cfe_api.h
#define READ_REG(rp) (mips3_ld((volatile uint64_t *)(rp)))
@@ -61,7 +62,7 @@
CFATTACH_DECL_NEW(cpu, 0,
cpu_match, cpu_attach, NULL, NULL);
-static int found = 0;
+static u_int found = 0;
static int
cpu_match(device_t parent, cfdata_t match, void *aux)
@@ -121,23 +122,44 @@
(ci-ci_cpu_freq % 100) / 1,
ci-ci_cycles_per_hz, ci-ci_divisor_delay);
- /*
- * If we're the primary CPU, no more work to do; we're already
- * running!
- */
- aprint_normal(%s: , xname);
- cpu_identify(self);
} else {
#if defined(MULTIPROCESSOR)
+ int status;
ci = cpu_info_alloc(NULL, found);
KASSERT(ci);
- // * spinup
+
+ sb1250_cpu_init(ci);
+
+ status = cfe_cpu_start(ci-ci_cpuid, cpu_trampoline,
+ (long) ci-ci_data.cpu_idlelwp-l_md.md_utf, 0,
+ (long) ci);
+ if (status != 0) {
+ aprint_error(: CFE call to start failed: %d\n,
+ status);
+ }
+ const u_long cpu_mask = 1L cpu_index(ci);
+ for (size_t i = 0; i 1; i++) {
+ if (cpus_hatched cpu_mask)
+ break;
+ DELAY(100);
+ }
+ if ((cpus_hatched cpu_mask) == 0) {
+ aprint_error(: failed to hatched!\n);
+ return;
+ }
#else
- aprint_normal(%s: processor off-line; multiprocessor support
- not present in kernel\n, xname);
+ aprint_normal_dev(self,
+ processor off-line;
+ multiprocessor support not present in kernel\n);
return;
#endif
}
+ /*
+ * Announce ourselves.
+ */
+ aprint_normal(%s: , xname);
+ cpu_identify(self);
+
cpu_attach_common(self, ci);
}
Index: src/sys/arch/sbmips/sbmips/sb1250_icu.c
diff -u src/sys/arch/sbmips/sbmips/sb1250_icu.c:1.9.36.5 src/sys/arch/sbmips/sbmips/sb1250_icu.c:1.9.36.6
--- src/sys/arch/sbmips/sbmips/sb1250_icu.c:1.9.36.5 Sun Feb 28 03:32:23 2010
+++ src/sys/arch/sbmips/sbmips/sb1250_icu.c Mon Mar 1 23:55:49 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: sb1250_icu.c,v 1.9.36.5 2010/02/28 03:32:23 matt Exp $ */
+/* $NetBSD: sb1250_icu.c,v 1.9.36.6 2010/03/01 23:55:49 matt Exp $ */
/*
* Copyright 2000, 2001
@@ -33,14 +33,14 @@
*/
#include sys/cdefs.h
-__KERNEL_RCSID(0, $NetBSD: sb1250_icu.c,v 1.9.36.5 2010/02/28 03:32:23 matt Exp $);
+__KERNEL_RCSID(0, $NetBSD: sb1250_icu.c,v 1.9.36.6 2010/03/01 23:55:49 matt Exp $);
#define __INTR_PRIVATE
#include sys/param.h
#include sys/systm.h
#include sys/device.h
-#include sys/malloc.h
+#include sys/kmem.h
/* XXX for uvmexp */
#include uvm/uvm_extern.h
@@ -48,7 +48,9 @@
#include machine/systemsw.h
#include mips/locore.h
-/* XXX for now, this copes with one cpu only, and assumes it's CPU 0 */
+#include mips/sibyte/include/sb1250_regs.h
+#include mips/sibyte/include/sb1250_int.h
+#include mips/sibyte/include/sb1250_scd.h
static const
CVS commit: [matt-nb5-mips64] src/sys/arch/sbmips
Module Name:src Committed By: matt Date: Mon Mar 1 23:55:49 UTC 2010 Modified Files: src/sys/arch/sbmips/include [matt-nb5-mips64]: systemsw.h src/sys/arch/sbmips/sbmips [matt-nb5-mips64]: cpu.c sb1250_icu.c Log Message: Add MP interrupts, IPIs, and secondary CPU spinup. (compile tested only). To generate a diff of this commit: cvs rdiff -u -r1.7.28.3 -r1.7.28.4 src/sys/arch/sbmips/include/systemsw.h cvs rdiff -u -r1.18.16.4 -r1.18.16.5 src/sys/arch/sbmips/sbmips/cpu.c cvs rdiff -u -r1.9.36.5 -r1.9.36.6 src/sys/arch/sbmips/sbmips/sb1250_icu.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [matt-nb5-mips64] src/sys/arch/mips/mips
Module Name:src Committed By: snj Date: Sun Feb 28 15:32:32 UTC 2010 Modified Files: src/sys/arch/mips/mips [matt-nb5-mips64]: mips_fixup.c Log Message: Fix some minor errors in comments. To generate a diff of this commit: cvs rdiff -u -r1.1.2.3 -r1.1.2.4 src/sys/arch/mips/mips/mips_fixup.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [matt-nb5-mips64] src/sys/arch/mips/mips
Module Name:src
Committed By: snj
Date: Sun Feb 28 15:32:32 UTC 2010
Modified Files:
src/sys/arch/mips/mips [matt-nb5-mips64]: mips_fixup.c
Log Message:
Fix some minor errors in comments.
To generate a diff of this commit:
cvs rdiff -u -r1.1.2.3 -r1.1.2.4 src/sys/arch/mips/mips/mips_fixup.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/mips/mips_fixup.c
diff -u src/sys/arch/mips/mips/mips_fixup.c:1.1.2.3 src/sys/arch/mips/mips/mips_fixup.c:1.1.2.4
--- src/sys/arch/mips/mips/mips_fixup.c:1.1.2.3 Sun Feb 28 03:21:07 2010
+++ src/sys/arch/mips/mips/mips_fixup.c Sun Feb 28 15:32:32 2010
@@ -29,7 +29,7 @@
#include sys/cdefs.h
-__KERNEL_RCSID(0, $NetBSD: mips_fixup.c,v 1.1.2.3 2010/02/28 03:21:07 matt Exp $);
+__KERNEL_RCSID(0, $NetBSD: mips_fixup.c,v 1.1.2.4 2010/02/28 15:32:32 snj Exp $);
#include sys/param.h
@@ -204,7 +204,7 @@
/*
* Find the lowest and highest jumps we will be replacing. We don't
- * need to do but it does make weeding out the non-matching jumps
+ * need to do it but it does make weeding out the non-matching jumps
* faster.
*/
for (size_t i = 0; i noffsets; i++) {
@@ -220,7 +220,7 @@
uint32_t opcode = insn 26;
/*
- * First we check to see if this is a jump and whether its
+ * First we check to see if this is a jump and whether it is
* within the range we are interested in.
*/
if ((opcode != OPCODE_J opcode != OPCODE_JAL)
@@ -237,7 +237,7 @@
/*
* Yes, we need to fix it up. Replace the old
* displacement with the real displacement. If we've
- * moved to a new cache line, sync the last cacheline
+ * moved to a new cache line, sync the last cache line
* we fixed.
*/
*insnp ^= offset ^ real_offsets[i];
CVS commit: [matt-nb5-mips64] src/sys/arch/evbmips/malta
Module Name:src Committed By: matt Date: Sun Feb 28 23:47:06 UTC 2010 Modified Files: src/sys/arch/evbmips/malta [matt-nb5-mips64]: machdep.c Log Message: Use cpu_startup_common. To generate a diff of this commit: cvs rdiff -u -r1.28.10.6 -r1.28.10.7 src/sys/arch/evbmips/malta/machdep.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [matt-nb5-mips64] src/sys/arch/evbmips
Module Name:src
Committed By: matt
Date: Sat Feb 27 08:00:02 UTC 2010
Modified Files:
src/sys/arch/evbmips/malta [matt-nb5-mips64]: machdep.c
src/sys/arch/evbmips/rmixl [matt-nb5-mips64]: machdep.c
Log Message:
For MULTIPROCESSOR kernels, enable exception fixups.
To generate a diff of this commit:
cvs rdiff -u -r1.28.10.4 -r1.28.10.5 src/sys/arch/evbmips/malta/machdep.c
cvs rdiff -u -r1.1.2.19 -r1.1.2.20 src/sys/arch/evbmips/rmixl/machdep.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/evbmips/malta/machdep.c
diff -u src/sys/arch/evbmips/malta/machdep.c:1.28.10.4 src/sys/arch/evbmips/malta/machdep.c:1.28.10.5
--- src/sys/arch/evbmips/malta/machdep.c:1.28.10.4 Mon Feb 1 04:17:51 2010
+++ src/sys/arch/evbmips/malta/machdep.c Sat Feb 27 08:00:02 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: machdep.c,v 1.28.10.4 2010/02/01 04:17:51 matt Exp $ */
+/* $NetBSD: machdep.c,v 1.28.10.5 2010/02/27 08:00:02 matt Exp $ */
/*
* Copyright 2001, 2002 Wasabi Systems, Inc.
@@ -112,7 +112,7 @@
*/
#include sys/cdefs.h
-__KERNEL_RCSID(0, $NetBSD: machdep.c,v 1.28.10.4 2010/02/01 04:17:51 matt Exp $);
+__KERNEL_RCSID(0, $NetBSD: machdep.c,v 1.28.10.5 2010/02/27 08:00:02 matt Exp $);
#include opt_ddb.h
#include opt_execfmt.h
@@ -144,6 +144,8 @@
#include machine/psl.h
#include machine/yamon.h
+#include mips/locore.h
+
#include evbmips/malta/autoconf.h
#include evbmips/malta/maltareg.h
#include evbmips/malta/maltavar.h
@@ -328,6 +330,13 @@
if (boothowto RB_KDB)
Debugger();
#endif
+
+#ifdef MULTIPROCESSOR
+ /*
+ * We can never running on more than one processor but we can dream.
+ */
+ mips_fixup_exceptions(mips_fixup_zero_relative);
+#endif
}
void
Index: src/sys/arch/evbmips/rmixl/machdep.c
diff -u src/sys/arch/evbmips/rmixl/machdep.c:1.1.2.19 src/sys/arch/evbmips/rmixl/machdep.c:1.1.2.20
--- src/sys/arch/evbmips/rmixl/machdep.c:1.1.2.19 Mon Feb 1 04:17:51 2010
+++ src/sys/arch/evbmips/rmixl/machdep.c Sat Feb 27 08:00:02 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: machdep.c,v 1.1.2.19 2010/02/01 04:17:51 matt Exp $ */
+/* $NetBSD: machdep.c,v 1.1.2.20 2010/02/27 08:00:02 matt Exp $ */
/*
* Copyright 2001, 2002 Wasabi Systems, Inc.
@@ -112,7 +112,7 @@
*/
#include sys/cdefs.h
-__KERNEL_RCSID(0, $NetBSD: machdep.c,v 1.1.2.19 2010/02/01 04:17:51 matt Exp $);
+__KERNEL_RCSID(0, $NetBSD: machdep.c,v 1.1.2.20 2010/02/27 08:00:02 matt Exp $);
#include opt_ddb.h
#include opt_com.h
@@ -248,6 +248,7 @@
#ifdef MULTIPROCESSOR
+static bool rmixl_fixup_cop0_oscratch(int32_t, uint32_t [2])
void rmixl_get_wakeup_info(struct rmixl_config *);
#ifdef MACHDEP_DEBUG
static void rmixl_wakeup_info_print(volatile rmixlfw_cpu_wakeup_info_t *);
@@ -443,7 +444,42 @@
if (boothowto RB_KDB)
Debugger();
#endif
+#ifdef MULTIPROCESSOR
+ /*
+ * Fix up the exception vector to use COP0 OSSCRATCH0
+ */
+ __asm __volatile(mtc0 %0,$%1
+ :: r(cpu_info_store), n(MIPS_COP_0_OSSCRATCH));
+ mips_fixup_exceptions(rmixl_fixup_cop0_oscratch);
+#endif
+}
+
+#ifdef MULTIPROCESSOR
+static bool
+rmixl_fixup_cop0_oscratch(int32_t load_addr, uint32_t new_insns[2])
+{
+ size_t offset = load_addr - (intptr_t)cpu_info_store;
+
+ KASSERT(MIPS_KSEG0_P(load_addr));
+ KASSERT(offset sizeof(struct cpu_info));
+
+ /*
+ * Fixup this direct load cpu_info_store to actual get the current
+ * CPU's cpu_info from COP0 OSSCRATCH0 and then fix the load to be
+ * relative from the start of struct cpu_info.
+ */
+
+ /* [0] = mfc0 rX, $22 (OSScratch) */
+ new_insns[0] = (020 26)
+ | (new_insns[0] 0x001f)
+ | (MIPS_COP_0_OSSCRATCH 11) | (0 0);
+
+ /* [1] = l[dw] rX, offset(rX) */
+ new_insns[1] = (new_insns[1] 0x) | offset;
+
+ return true;
}
+#endif /* MULTIPROCESSOR */
/*
* ram_seg_resv - cut reserved regions out of segs, fragmenting as needed
CVS commit: [matt-nb5-mips64] src/sys/arch/mips/mips
Module Name:src Committed By: snj Date: Sat Feb 27 18:25:25 UTC 2010 Modified Files: src/sys/arch/mips/mips [matt-nb5-mips64]: mips_fixup.c Log Message: Fix a couple typos in comments. To generate a diff of this commit: cvs rdiff -u -r1.1.2.1 -r1.1.2.2 src/sys/arch/mips/mips/mips_fixup.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [matt-nb5-mips64] src/sys/arch/mips/mips
Module Name:src Committed By: snj Date: Sat Feb 27 18:25:25 UTC 2010 Modified Files: src/sys/arch/mips/mips [matt-nb5-mips64]: mips_fixup.c Log Message: Fix a couple typos in comments. To generate a diff of this commit: cvs rdiff -u -r1.1.2.1 -r1.1.2.2 src/sys/arch/mips/mips/mips_fixup.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/mips/mips/mips_fixup.c diff -u src/sys/arch/mips/mips/mips_fixup.c:1.1.2.1 src/sys/arch/mips/mips/mips_fixup.c:1.1.2.2 --- src/sys/arch/mips/mips/mips_fixup.c:1.1.2.1 Sat Feb 27 07:58:52 2010 +++ src/sys/arch/mips/mips/mips_fixup.c Sat Feb 27 18:25:25 2010 @@ -29,7 +29,7 @@ #include sys/cdefs.h -__KERNEL_RCSID(0, $NetBSD: mips_fixup.c,v 1.1.2.1 2010/02/27 07:58:52 matt Exp $); +__KERNEL_RCSID(0, $NetBSD: mips_fixup.c,v 1.1.2.2 2010/02/27 18:25:25 snj Exp $); #include sys/param.h @@ -136,7 +136,7 @@ KASSERT(load_addr (intptr_t)(ci + 1)); /* - * Use the load instrution as a prototype and it make use $0 + * Use the load instruction as a prototype and it make use $0 * as base and the new negative offset. The second instruction * is a NOP. */ @@ -152,7 +152,7 @@ (new_insns[0] 21) 31); #endif /* - * Contruct the TLB_LO entry needed to map cpu_info_store. + * Construct the TLB_LO entry needed to map cpu_info_store. */ const uint32_t tlb_lo = MIPS3_PG_G|MIPS3_PG_V|MIPS3_PG_D | mips3_paddr_to_tlbpfn(MIPS_KSEG0_TO_PHYS(trunc_page(load_addr)));
CVS commit: [matt-nb5-mips64] src/sys/arch/mips/mips
Module Name:src Committed By: snj Date: Sat Feb 27 19:22:03 UTC 2010 Modified Files: src/sys/arch/mips/mips [matt-nb5-mips64]: lock_stubs.S Log Message: Fix comment gimplish. To generate a diff of this commit: cvs rdiff -u -r1.9.18.7 -r1.9.18.8 src/sys/arch/mips/mips/lock_stubs.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [matt-nb5-mips64] src/sys/arch/mips/mips
Module Name:src Committed By: snj Date: Sat Feb 27 19:22:47 UTC 2010 Modified Files: src/sys/arch/mips/mips [matt-nb5-mips64]: lock_stubs.S Log Message: Fix whitespace in previous. To generate a diff of this commit: cvs rdiff -u -r1.9.18.8 -r1.9.18.9 src/sys/arch/mips/mips/lock_stubs.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [matt-nb5-mips64] src/sys/arch/mips/mips
Module Name:src Committed By: snj Date: Sat Feb 27 19:22:47 UTC 2010 Modified Files: src/sys/arch/mips/mips [matt-nb5-mips64]: lock_stubs.S Log Message: Fix whitespace in previous. To generate a diff of this commit: cvs rdiff -u -r1.9.18.8 -r1.9.18.9 src/sys/arch/mips/mips/lock_stubs.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/mips/mips/lock_stubs.S diff -u src/sys/arch/mips/mips/lock_stubs.S:1.9.18.8 src/sys/arch/mips/mips/lock_stubs.S:1.9.18.9 --- src/sys/arch/mips/mips/lock_stubs.S:1.9.18.8 Sat Feb 27 19:22:03 2010 +++ src/sys/arch/mips/mips/lock_stubs.S Sat Feb 27 19:22:47 2010 @@ -1,4 +1,4 @@ -/* $NetBSD: lock_stubs.S,v 1.9.18.8 2010/02/27 19:22:03 snj Exp $ */ +/* $NetBSD: lock_stubs.S,v 1.9.18.9 2010/02/27 19:22:47 snj Exp $ */ /*- * Copyright (c) 2007 The NetBSD Foundation, Inc. @@ -241,7 +241,7 @@ /* * If the current IPL is less than the mutex's IPL, we need to raise - * our IPL to the mutex'es + * our IPL to the mutex'es */ sltu v1, ta1, ta0 # v1 = ta1 ta0 beqz v1, 1f @@ -457,7 +457,7 @@ /* * If the current IPL is less than the mutex's IPL, we need to raise - * our IPL to the mutex'es + * our IPL to the mutex'es */ sltu a3, ta1, a0 # a3 = ta1 a0 beqz a3, 1f
CVS commit: [matt-nb5-mips64] src/sys/arch/mips/mips
Module Name:src Committed By: snj Date: Sat Feb 27 19:49:26 UTC 2010 Modified Files: src/sys/arch/mips/mips [matt-nb5-mips64]: pmap.c Log Message: It's PARANOIADIAG, not PARANIOADIAG. Fix a couple small errors in comments. To generate a diff of this commit: cvs rdiff -u -r1.179.16.19 -r1.179.16.20 src/sys/arch/mips/mips/pmap.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [matt-nb5-mips64] src/sys/arch/mips/mips
Module Name:src Committed By: snj Date: Sat Feb 27 20:10:26 UTC 2010 Modified Files: src/sys/arch/mips/mips [matt-nb5-mips64]: pmap_tlb.c Log Message: Fix some gimplish in comments. To generate a diff of this commit: cvs rdiff -u -r1.1.2.5 -r1.1.2.6 src/sys/arch/mips/mips/pmap_tlb.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [matt-nb5-mips64] src/sys/arch/mips/mips
Module Name:src Committed By: snj Date: Sat Feb 27 20:10:26 UTC 2010 Modified Files: src/sys/arch/mips/mips [matt-nb5-mips64]: pmap_tlb.c Log Message: Fix some gimplish in comments. To generate a diff of this commit: cvs rdiff -u -r1.1.2.5 -r1.1.2.6 src/sys/arch/mips/mips/pmap_tlb.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/mips/mips/pmap_tlb.c diff -u src/sys/arch/mips/mips/pmap_tlb.c:1.1.2.5 src/sys/arch/mips/mips/pmap_tlb.c:1.1.2.6 --- src/sys/arch/mips/mips/pmap_tlb.c:1.1.2.5 Sat Feb 27 07:58:52 2010 +++ src/sys/arch/mips/mips/pmap_tlb.c Sat Feb 27 20:10:26 2010 @@ -1,4 +1,4 @@ -/* $NetBSD: pmap_tlb.c,v 1.1.2.5 2010/02/27 07:58:52 matt Exp $ */ +/* $NetBSD: pmap_tlb.c,v 1.1.2.6 2010/02/27 20:10:26 snj Exp $ */ /*- * Copyright (c) 2010 The NetBSD Foundation, Inc. @@ -31,7 +31,7 @@ #include sys/cdefs.h -__KERNEL_RCSID(0, $NetBSD: pmap_tlb.c,v 1.1.2.5 2010/02/27 07:58:52 matt Exp $); +__KERNEL_RCSID(0, $NetBSD: pmap_tlb.c,v 1.1.2.6 2010/02/27 20:10:26 snj Exp $); /* * Manages address spaces in a TLB. @@ -79,16 +79,16 @@ * * When a change to the local TLB may require a change in the TLB's of other * CPUs, we try to avoid sending an IPI if at all possible. For instance, if - * are updating a PTE and that PTE previously was invalid and therefore - * couldn't support an active mapping, there's no need for an IPI since can be - * no TLB entry to invalidate. The other case is when we change a PTE to be - * modified we just update the local TLB. If another TLB has a stale entry, - * a TLB MOD exception will be raised and that will cause the local TLB to be - * updated. + * we are updating a PTE and that PTE previously was invalid and therefore + * couldn't support an active mapping, there's no need for an IPI since there + * can be no TLB entry to invalidate. The other case is when we change a PTE + * to be modified we just update the local TLB. If another TLB has a stale + * entry, a TLB MOD exception will be raised and that will cause the local TLB + * to be updated. * * We never need to update a non-local TLB if the pmap doesn't have a valid * ASID for that TLB. If it does have a valid ASID but isn't current onproc - * we simply reset its ASID for that TLB and then time it goes onproc it + * we simply reset its ASID for that TLB and then when it goes onproc it * will allocate a new ASID and any existing TLB entries will be orphaned. * Only in the case that pmap has an onproc ASID do we actually have to send * an IPI. @@ -110,12 +110,12 @@ * 0) nothing, * 1) if that ASID is still onproc, we invalidate the TLB entries for * that single ASID. If not, just reset the pmap's ASID to invalidate - * and let it allocated the next time it goes onproc, + * and let it be allocated the next time it goes onproc, * 2) we reinitialize the ASID space (preserving any onproc ASIDs) and * invalidate all non-wired non-global TLB entries, * 3) we invalidate all of the non-wired global TLB entries, * 4) we reinitialize the ASID space (again preserving any onproc ASIDs) - * invalidate all non-wried TLB entries. + * invalidate all non-wired TLB entries. * * As you can see, shootdowns are not concerned with addresses, just address * spaces. Since the number of TLB entries is usually quite small, this avoids @@ -654,7 +654,7 @@ #ifdef MULTIPROCESSOR /* - * Mark that we now an active ASID for all CPUs sharing this TLB. + * Mark that we now have an active ASID for all CPUs sharing this TLB. * The bits in pm_active belonging to this TLB can only be changed * while this TLBs lock is held. */
CVS commit: [matt-nb5-mips64] src/sys/arch/mips/mips
Module Name:src Committed By: snj Date: Sat Feb 27 20:32:04 UTC 2010 Modified Files: src/sys/arch/mips/mips [matt-nb5-mips64]: mipsX_subr.S Log Message: Fix some typos in comments. To generate a diff of this commit: cvs rdiff -u -r1.26.36.1.2.27 -r1.26.36.1.2.28 \ src/sys/arch/mips/mips/mipsX_subr.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [matt-nb5-mips64] src/sys/arch/mips/mips
Module Name:src Committed By: snj Date: Sat Feb 27 20:32:04 UTC 2010 Modified Files: src/sys/arch/mips/mips [matt-nb5-mips64]: mipsX_subr.S Log Message: Fix some typos in comments. To generate a diff of this commit: cvs rdiff -u -r1.26.36.1.2.27 -r1.26.36.1.2.28 \ src/sys/arch/mips/mips/mipsX_subr.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/mips/mips/mipsX_subr.S diff -u src/sys/arch/mips/mips/mipsX_subr.S:1.26.36.1.2.27 src/sys/arch/mips/mips/mipsX_subr.S:1.26.36.1.2.28 --- src/sys/arch/mips/mips/mipsX_subr.S:1.26.36.1.2.27 Sat Feb 27 07:58:52 2010 +++ src/sys/arch/mips/mips/mipsX_subr.S Sat Feb 27 20:32:04 2010 @@ -1,4 +1,4 @@ -/* $NetBSD: mipsX_subr.S,v 1.26.36.1.2.27 2010/02/27 07:58:52 matt Exp $ */ +/* $NetBSD: mipsX_subr.S,v 1.26.36.1.2.28 2010/02/27 20:32:04 snj Exp $ */ /* * Copyright 2002 Wasabi Systems, Inc. @@ -671,7 +671,7 @@ /* * We need to find out if this was due to a T_BREAK and if so - * turn off interrupts in addition to clearing the execption level. + * turn off interrupts in addition to clearing the exception level. */ li v1, 1 T_BREAK # make a mask of T_BREAK sll t0, a1, MIPS_CR_EXC_CODE_SHIFT # shift exc code to low 5 bits @@ -1205,7 +1205,7 @@ * Clear interrupt enable */ mfc0 v0, MIPS_COP_0_STATUS # read it - xor v0, MIPS_SR_INT_IE # disable interrutps + xor v0, MIPS_SR_INT_IE # disable interrupts mtc0 v0, MIPS_COP_0_STATUS # write it COP0_SYNC nop @@ -1957,7 +1957,7 @@ * mipsN_VCED -- * * Handle virtual coherency exceptions. - * Called directly from the mips3 execption-table code. + * Called directly from the mips3 exception-table code. * only k0, k1 are available on entry * * Results: @@ -1965,7 +1965,7 @@ * * Side effects: * Remaps the conflicting address as uncached and returns - * from the execption. + * from the exception. * * NB: cannot be profiled, all registers are user registers on entry. * @@ -2631,7 +2631,7 @@ tlbwi # now write the invalid TLB COP0_SYNC - mtc0 a3, MIPS_COP_0_TLB_HI # retore the addr for new TLB + mtc0 a3, MIPS_COP_0_TLB_HI # restore the addr for new TLB COP0_SYNC nop nop
CVS commit: [matt-nb5-mips64] src/sys/arch/evbmips
Module Name:src Committed By: snj Date: Sat Feb 27 20:35:14 UTC 2010 Modified Files: src/sys/arch/evbmips/malta [matt-nb5-mips64]: machdep.c src/sys/arch/evbmips/rmixl [matt-nb5-mips64]: machdep.c Log Message: Fix gimplish. To generate a diff of this commit: cvs rdiff -u -r1.28.10.5 -r1.28.10.6 src/sys/arch/evbmips/malta/machdep.c cvs rdiff -u -r1.1.2.20 -r1.1.2.21 src/sys/arch/evbmips/rmixl/machdep.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/evbmips/malta/machdep.c diff -u src/sys/arch/evbmips/malta/machdep.c:1.28.10.5 src/sys/arch/evbmips/malta/machdep.c:1.28.10.6 --- src/sys/arch/evbmips/malta/machdep.c:1.28.10.5 Sat Feb 27 08:00:02 2010 +++ src/sys/arch/evbmips/malta/machdep.c Sat Feb 27 20:35:13 2010 @@ -1,4 +1,4 @@ -/* $NetBSD: machdep.c,v 1.28.10.5 2010/02/27 08:00:02 matt Exp $ */ +/* $NetBSD: machdep.c,v 1.28.10.6 2010/02/27 20:35:13 snj Exp $ */ /* * Copyright 2001, 2002 Wasabi Systems, Inc. @@ -112,7 +112,7 @@ */ #include sys/cdefs.h -__KERNEL_RCSID(0, $NetBSD: machdep.c,v 1.28.10.5 2010/02/27 08:00:02 matt Exp $); +__KERNEL_RCSID(0, $NetBSD: machdep.c,v 1.28.10.6 2010/02/27 20:35:13 snj Exp $); #include opt_ddb.h #include opt_execfmt.h @@ -333,7 +333,7 @@ #ifdef MULTIPROCESSOR /* - * We can never running on more than one processor but we can dream. + * We can never be running on more than one processor but we can dream. */ mips_fixup_exceptions(mips_fixup_zero_relative); #endif Index: src/sys/arch/evbmips/rmixl/machdep.c diff -u src/sys/arch/evbmips/rmixl/machdep.c:1.1.2.20 src/sys/arch/evbmips/rmixl/machdep.c:1.1.2.21 --- src/sys/arch/evbmips/rmixl/machdep.c:1.1.2.20 Sat Feb 27 08:00:02 2010 +++ src/sys/arch/evbmips/rmixl/machdep.c Sat Feb 27 20:35:14 2010 @@ -1,4 +1,4 @@ -/* $NetBSD: machdep.c,v 1.1.2.20 2010/02/27 08:00:02 matt Exp $ */ +/* $NetBSD: machdep.c,v 1.1.2.21 2010/02/27 20:35:14 snj Exp $ */ /* * Copyright 2001, 2002 Wasabi Systems, Inc. @@ -112,7 +112,7 @@ */ #include sys/cdefs.h -__KERNEL_RCSID(0, $NetBSD: machdep.c,v 1.1.2.20 2010/02/27 08:00:02 matt Exp $); +__KERNEL_RCSID(0, $NetBSD: machdep.c,v 1.1.2.21 2010/02/27 20:35:14 snj Exp $); #include opt_ddb.h #include opt_com.h @@ -464,7 +464,7 @@ KASSERT(offset sizeof(struct cpu_info)); /* - * Fixup this direct load cpu_info_store to actual get the current + * Fixup this direct load cpu_info_store to actually get the current * CPU's cpu_info from COP0 OSSCRATCH0 and then fix the load to be * relative from the start of struct cpu_info. */
CVS commit: [matt-nb5-mips64] src/sys/arch/mips/rmi
Module Name:src Committed By: matt Date: Sat Feb 27 21:25:24 UTC 2010 Modified Files: src/sys/arch/mips/rmi [matt-nb5-mips64]: rmixl_cpucore.c Log Message: s/pmap_tlb_info/pmap_tlb0_info/ To generate a diff of this commit: cvs rdiff -u -r1.1.2.4 -r1.1.2.5 src/sys/arch/mips/rmi/rmixl_cpucore.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [matt-nb5-mips64] src/sys/arch/mips/rmi
Module Name:src
Committed By: matt
Date: Sat Feb 27 21:25:24 UTC 2010
Modified Files:
src/sys/arch/mips/rmi [matt-nb5-mips64]: rmixl_cpucore.c
Log Message:
s/pmap_tlb_info/pmap_tlb0_info/
To generate a diff of this commit:
cvs rdiff -u -r1.1.2.4 -r1.1.2.5 src/sys/arch/mips/rmi/rmixl_cpucore.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/rmi/rmixl_cpucore.c
diff -u src/sys/arch/mips/rmi/rmixl_cpucore.c:1.1.2.4 src/sys/arch/mips/rmi/rmixl_cpucore.c:1.1.2.5
--- src/sys/arch/mips/rmi/rmixl_cpucore.c:1.1.2.4 Tue Feb 23 20:33:48 2010
+++ src/sys/arch/mips/rmi/rmixl_cpucore.c Sat Feb 27 21:25:24 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: rmixl_cpucore.c,v 1.1.2.4 2010/02/23 20:33:48 matt Exp $ */
+/* $NetBSD: rmixl_cpucore.c,v 1.1.2.5 2010/02/27 21:25:24 matt Exp $ */
/*
* Copyright 2002 Wasabi Systems, Inc.
@@ -38,7 +38,7 @@
#include locators.h
#include sys/cdefs.h
-__KERNEL_RCSID(0, $NetBSD: rmixl_cpucore.c,v 1.1.2.4 2010/02/23 20:33:48 matt Exp $);
+__KERNEL_RCSID(0, $NetBSD: rmixl_cpucore.c,v 1.1.2.5 2010/02/27 21:25:24 matt Exp $);
#include sys/param.h
#include sys/device.h
@@ -94,7 +94,7 @@
* default one for the system.
*/
if (sc-sc_core == 0) {
- sc-sc_tlbinfo = pmap_tlb_info;
+ sc-sc_tlbinfo = pmap_tlb0_info;
} else {
sc-sc_tlbinfo = sc-sc_tlbinfo0;
pmap_tlb_info_init(sc-sc_tlbinfo);
CVS commit: [matt-nb5-mips64] src/sys/arch/evbmips/rmixl
Module Name:src Committed By: matt Date: Sat Feb 27 21:26:28 UTC 2010 Modified Files: src/sys/arch/evbmips/rmixl [matt-nb5-mips64]: machdep.c Log Message: Fix tpyo (missing ;) To generate a diff of this commit: cvs rdiff -u -r1.1.2.21 -r1.1.2.22 src/sys/arch/evbmips/rmixl/machdep.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [matt-nb5-mips64] src/sys/arch/mips/mips
Module Name:src Committed By: matt Date: Sat Feb 27 21:29:01 UTC 2010 Modified Files: src/sys/arch/mips/mips [matt-nb5-mips64]: pmap_tlb.c Log Message: Fix for non DIAGNOSTIC kernels To generate a diff of this commit: cvs rdiff -u -r1.1.2.6 -r1.1.2.7 src/sys/arch/mips/mips/pmap_tlb.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [matt-nb5-mips64] src/sys/arch/mips/mips
Module Name:src
Committed By: matt
Date: Sat Feb 27 21:29:01 UTC 2010
Modified Files:
src/sys/arch/mips/mips [matt-nb5-mips64]: pmap_tlb.c
Log Message:
Fix for non DIAGNOSTIC kernels
To generate a diff of this commit:
cvs rdiff -u -r1.1.2.6 -r1.1.2.7 src/sys/arch/mips/mips/pmap_tlb.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/mips/pmap_tlb.c
diff -u src/sys/arch/mips/mips/pmap_tlb.c:1.1.2.6 src/sys/arch/mips/mips/pmap_tlb.c:1.1.2.7
--- src/sys/arch/mips/mips/pmap_tlb.c:1.1.2.6 Sat Feb 27 20:10:26 2010
+++ src/sys/arch/mips/mips/pmap_tlb.c Sat Feb 27 21:29:01 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: pmap_tlb.c,v 1.1.2.6 2010/02/27 20:10:26 snj Exp $ */
+/* $NetBSD: pmap_tlb.c,v 1.1.2.7 2010/02/27 21:29:01 matt Exp $ */
/*-
* Copyright (c) 2010 The NetBSD Foundation, Inc.
@@ -31,7 +31,7 @@
#include sys/cdefs.h
-__KERNEL_RCSID(0, $NetBSD: pmap_tlb.c,v 1.1.2.6 2010/02/27 20:10:26 snj Exp $);
+__KERNEL_RCSID(0, $NetBSD: pmap_tlb.c,v 1.1.2.7 2010/02/27 21:29:01 matt Exp $);
/*
* Manages address spaces in a TLB.
@@ -612,7 +612,9 @@
* a new one.
*/
if (__predict_false(TLBINFO_ASID_INUSE_P(ti, ti-ti_asid_hint))) {
+#ifdef DIAGNOSTIC
const size_t words = __arraycount(ti-ti_asid_bitmap);
+#endif
const size_t nbpw = 8 * sizeof(ti-ti_asid_bitmap[0]);
for (size_t i = 0; i ti-ti_asid_hint / nbpw; i++) {
KASSERT(~ti-ti_asid_bitmap[i] == 0);
CVS commit: [matt-nb5-mips64] src/sys/arch/mips
Module Name:src
Committed By: matt
Date: Sun Feb 28 03:21:07 UTC 2010
Modified Files:
src/sys/arch/mips/include [matt-nb5-mips64]: locore.h
src/sys/arch/mips/mips [matt-nb5-mips64]: mips_fixup.c
Log Message:
Add code which can change a direct jump to stub with an indirect call to
a direct jump to the actual routine.
To generate a diff of this commit:
cvs rdiff -u -r1.78.36.1.2.16 -r1.78.36.1.2.17 \
src/sys/arch/mips/include/locore.h
cvs rdiff -u -r1.1.2.2 -r1.1.2.3 src/sys/arch/mips/mips/mips_fixup.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/include/locore.h
diff -u src/sys/arch/mips/include/locore.h:1.78.36.1.2.16 src/sys/arch/mips/include/locore.h:1.78.36.1.2.17
--- src/sys/arch/mips/include/locore.h:1.78.36.1.2.16 Sat Feb 27 07:58:52 2010
+++ src/sys/arch/mips/include/locore.h Sun Feb 28 03:21:06 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.h,v 1.78.36.1.2.16 2010/02/27 07:58:52 matt Exp $ */
+/* $NetBSD: locore.h,v 1.78.36.1.2.17 2010/02/28 03:21:06 matt Exp $ */
/*
* This file should not be included by MI code!!!
@@ -47,8 +47,14 @@
typedef bool (*mips_fixup_callback_t)(int32_t, uint32_t [2]);
+void fixup_splcalls(void);/* splstubs.c */
bool mips_fixup_exceptions(mips_fixup_callback_t);
bool mips_fixup_zero_relative(int32_t, uint32_t [2]);
+void mips_fixup_stubs(uint32_t *, uint32_t *, const uint32_t *,
+ const uint32_t *, size_t);
+void fixup_mips_cpu_switch_resume(void);
+
+void mips_cpu_switch_resume(struct lwp *);
#ifdef MIPS1
void mips1_tlb_set_asid(uint32_t);
Index: src/sys/arch/mips/mips/mips_fixup.c
diff -u src/sys/arch/mips/mips/mips_fixup.c:1.1.2.2 src/sys/arch/mips/mips/mips_fixup.c:1.1.2.3
--- src/sys/arch/mips/mips/mips_fixup.c:1.1.2.2 Sat Feb 27 18:25:25 2010
+++ src/sys/arch/mips/mips/mips_fixup.c Sun Feb 28 03:21:07 2010
@@ -29,7 +29,7 @@
#include sys/cdefs.h
-__KERNEL_RCSID(0, $NetBSD: mips_fixup.c,v 1.1.2.2 2010/02/27 18:25:25 snj Exp $);
+__KERNEL_RCSID(0, $NetBSD: mips_fixup.c,v 1.1.2.3 2010/02/28 03:21:07 matt Exp $);
#include sys/param.h
@@ -71,20 +71,20 @@
if (INSN_LUI_P(insn)) {
const int32_t offset = insn 16;
lui_reg = (insn 16) 31;
-#ifdef DEBUG
- printf(%s: %#x: insn %08x: lui r%zu, %%hi(%#x),
+#ifdef DEBUG_VERBOSE
+ printf(%s: %#x: insn %08x: lui r%zu, %%hi(%#x),
__func__, (int32_t)(intptr_t)insnp,
insn, lui_reg, offset);
#endif
if (upper_addr == offset) {
lui_insnp = insnp;
-#ifdef DEBUG
+#ifdef DEBUG_VERBOSE
printf( (maybe));
#endif
} else {
lui_insnp = NULL;
}
-#ifdef DEBUG
+#ifdef DEBUG_VERBOSE
printf(\n);
#endif
} else if (lui_insnp != NULL INSN_LOAD_P(insn)) {
@@ -95,8 +95,8 @@
load_addr addr + size
base == lui_reg
rt == lui_reg) {
-#ifdef DEBUG
-printf(%s: %#x: insn %08x: %s r%zu, %%lo(%08x)(r%zu)\n,
+#ifdef DEBUG_VERBOSE
+printf(%s: %#x: insn %08x: %s r%zu, %%lo(%08x)(r%zu)\n,
__func__, (int32_t)(intptr_t)insnp,
insn, INSN_LW_P(insn) ? lw : ld,
rt, load_addr, base);
@@ -143,8 +143,8 @@
new_insns[0] =
(new_insns[1] (0xfc1f|PAGE_MASK)) | (0x ~PAGE_MASK);
new_insns[1] = 0;
-#ifdef DEBUG
- printf(%s: %08x: insn#1 %08x: %s r%u, %d(r%u)\n,
+#ifdef DEBUG_VERBOSE
+ printf(%s: %08x: insn#1 %08x: %s r%u, %d(r%u)\n,
__func__, (int32_t)load_addr, new_insns[0],
INSN_LW_P(new_insns[0]) ? lw : ld,
(new_insns[0] 16) 31,
@@ -171,3 +171,121 @@
return true;
}
+
+#define OPCODE_J 002
+#define OPCODE_JAL 003
+
+static void
+fixup_mips_jump(uint32_t *insnp, uint32_t stub, uint32_t real)
+{
+ uint32_t insn = *insnp;
+
+ KASSERT((insn (26+1)) == (OPCODE_J 1));
+ KASSERT((insn 6) == (stub 4));
+
+ insn ^= (stub ^ real) 4 6;
+
+ KASSERT((insn 6) == (real 4));
+
+ *insnp = insn;
+}
+
+void
+mips_fixup_stubs(uint32_t *start, uint32_t *end,
+ const uint32_t *stub_offsets, const uint32_t *real_offsets,
+ size_t noffsets)
+{
+ uint32_t min_offset = 0x03ff;
+ uint32_t max_offset = 0x;
+#ifdef DEBUG
+ size_t fixups = 0;
+ uint32_t cycles = (CPUISMIPS3 ? mips3_cp0_count_read() : 0);
+#endif
+
+ /*
+ * Find the lowest and highest jumps we will be replacing. We don't
+ * need to do but it does make weeding out the non-matching jumps
+ * faster.
+ */
+ for (size_t i = 0; i noffsets; i++) {
+ if (stub_offsets[i] min_offset)
+ min_offset = stub_offsets[i];
+ if (max_offset stub_offsets[i])
+ max_offset = stub_offsets[i];
+ }
+
+ for (uint32_t *insnp = start; insnp end; insnp++) {
+ uint32_t insn = *insnp;
+ uint32_t offset = insn 0x03ff;
+ uint32_t opcode = insn 26;
+
+ /*
+ * First we check to see if this is a jump and whether its
+ * within the range we are interested in.
+ */
+ if ((opcode != OPCODE_J opcode != OPCODE_JAL)
+ || offset min_offset || max_offset offset)
+
CVS commit: [matt-nb5-mips64] src/sys/arch/mips/mips
Module Name:src
Committed By: matt
Date: Sun Feb 28 03:23:06 UTC 2010
Added Files:
src/sys/arch/mips/mips [matt-nb5-mips64]: spl_stubs.c
Log Message:
We no longer inline the spl indirect calls through mips_splsw. Instead we
have stubs that do the indirection and then fixup the calls to the stubs to
be calls to the actual routines.
To generate a diff of this commit:
cvs rdiff -u -r0 -r1.1.2.1 src/sys/arch/mips/mips/spl_stubs.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Added files:
Index: src/sys/arch/mips/mips/spl_stubs.c
diff -u /dev/null src/sys/arch/mips/mips/spl_stubs.c:1.1.2.1
--- /dev/null Sun Feb 28 03:23:06 2010
+++ src/sys/arch/mips/mips/spl_stubs.c Sun Feb 28 03:23:06 2010
@@ -0,0 +1,238 @@
+/* $NetBSD: spl_stubs.c,v 1.1.2.1 2010/02/28 03:23:06 matt Exp $ */
+/*-
+ * Copyright (c) 2010 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Matt Thomas m...@3am-software.com.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include sys/cdefs.h
+
+__KERNEL_RCSID(0, $NetBSD: spl_stubs.c,v 1.1.2.1 2010/02/28 03:23:06 matt Exp $);
+
+#define __INTR_PRIVATE
+
+#include sys/param.h
+
+#include mips/cache.h
+#include mips/intr.h
+#include mips/locore.h
+
+int splhigh(void) __section(.stub);
+int splhigh_noprof(void) __section(.stub);
+int splsched(void) __section(.stub);
+int splvm(void) __section(.stub);
+int splsoftserial(void) __section(.stub);
+int splsoftnet(void) __section(.stub);
+int splsoftbio(void) __section(.stub);
+int splsoftclock(void) __section(.stub);
+int splraise(int) __section(.stub);
+void splx(int) __section(.stub);
+void splx_noprof(int) __section(.stub);
+void spl0(void) __section(.stub);
+int splintr(uint32_t *) __section(.stub);
+void _setsoftintr(uint32_t) __section(.stub);
+void _clrsoftintr(uint32_t) __section(.stub);
+
+#define J_SPLHIGH 0
+int
+splhigh(void)
+{
+ return (*mips_splsw.splsw_splhigh)();
+}
+
+#define J_SPLHIGH_NOPROF (J_SPLHIGH+1)
+int
+splhigh_noprof(void)
+{
+ return (*mips_splsw.splsw_splhigh_noprof)();
+}
+
+#define J_SPLSCHED (J_SPLHIGH_NOPROF+1)
+int
+splsched(void)
+{
+ return (*mips_splsw.splsw_splsched)();
+}
+
+#define J_SPLVM (J_SPLSCHED+1)
+int
+splvm(void)
+{
+ return (*mips_splsw.splsw_splvm)();
+}
+
+#define J_SPLSOFTSERIAL (J_SPLVM+1)
+int
+splsoftserial(void)
+{
+ return (*mips_splsw.splsw_splsoftserial)();
+}
+
+#define J_SPLSOFTNET (J_SPLSOFTSERIAL+1)
+int
+splsoftnet(void)
+{
+ return (*mips_splsw.splsw_splsoftnet)();
+}
+
+#define J_SPLSOFTBIO (J_SPLSOFTNET+1)
+int
+splsoftbio(void)
+{
+ return (*mips_splsw.splsw_splsoftbio)();
+}
+
+#define J_SPLSOFTCLOCK (J_SPLSOFTBIO+1)
+int
+splsoftclock(void)
+{
+ return (*mips_splsw.splsw_splsoftclock)();
+}
+
+#define J_SPL0 (J_SPLSOFTCLOCK+1)
+void
+spl0(void)
+{
+ (*mips_splsw.splsw_spl0)();
+}
+
+#define J_SPLX (J_SPL0+1)
+void
+splx(int s)
+{
+ (*mips_splsw.splsw_splx)(s);
+}
+
+#define J_SPLX_NOPROF (J_SPLX+1)
+void
+splx_noprof(int s)
+{
+ (*mips_splsw.splsw_splx_noprof)(s);
+}
+
+#define J_SPLRAISE (J_SPLX_NOPROF+1)
+int
+splraise(int s)
+{
+return (*mips_splsw.splsw_splraise)(s);
+}
+
+#define J_SPLINTR (J_SPLRAISE+1)
+int
+splintr(uint32_t *p)
+{
+ return (*mips_splsw.splsw_splintr)(p);
+}
+
+#define J_SETSOFTINTR (J_SPLINTR+1)
+void
+_setsoftintr(uint32_t m)
+{
+ (*mips_splsw.splsw__setsoftintr)(m);
+}
+
+#define J_CLRSOFTINTR (J_SETSOFTINTR+1)
+void
+_clrsoftintr(uint32_t m)
+{
+ (*mips_splsw.splsw__clrsoftintr)(m);
+}
+
+#define J_SPLMAX (J_CLRSOFTINTR+1)
+
+#if 0
+#define offsetofsplsw(x) (offsetof(struct splsw,
CVS commit: [matt-nb5-mips64] src/sys/arch/mips/mips
Module Name:src Committed By: matt Date: Sun Feb 28 03:23:06 UTC 2010 Added Files: src/sys/arch/mips/mips [matt-nb5-mips64]: spl_stubs.c Log Message: We no longer inline the spl indirect calls through mips_splsw. Instead we have stubs that do the indirection and then fixup the calls to the stubs to be calls to the actual routines. To generate a diff of this commit: cvs rdiff -u -r0 -r1.1.2.1 src/sys/arch/mips/mips/spl_stubs.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [matt-nb5-mips64] src/sys/arch/mips/conf
Module Name:src Committed By: matt Date: Sun Feb 28 03:24:56 UTC 2010 Modified Files: src/sys/arch/mips/conf [matt-nb5-mips64]: files.mips Log Message: Add spl_stubs.c To generate a diff of this commit: cvs rdiff -u -r1.58.24.9 -r1.58.24.10 src/sys/arch/mips/conf/files.mips Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [matt-nb5-mips64] src/sys/arch/mips/include
Module Name:src Committed By: matt Date: Sun Feb 28 03:26:25 UTC 2010 Modified Files: src/sys/arch/mips/include [matt-nb5-mips64]: intr.h Log Message: Now that we use stubs for the spl* calls, we no longer need to export struct splsw or struct ipl_sr_map to the world. So we protect those with __INTR_PRIVATE. To generate a diff of this commit: cvs rdiff -u -r1.3.96.5 -r1.3.96.6 src/sys/arch/mips/include/intr.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [matt-nb5-mips64] src/sys/arch/mips/include
Module Name:src
Committed By: matt
Date: Sun Feb 28 03:26:25 UTC 2010
Modified Files:
src/sys/arch/mips/include [matt-nb5-mips64]: intr.h
Log Message:
Now that we use stubs for the spl* calls, we no longer need to export
struct splsw or struct ipl_sr_map to the world. So we protect those with
__INTR_PRIVATE.
To generate a diff of this commit:
cvs rdiff -u -r1.3.96.5 -r1.3.96.6 src/sys/arch/mips/include/intr.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/include/intr.h
diff -u src/sys/arch/mips/include/intr.h:1.3.96.5 src/sys/arch/mips/include/intr.h:1.3.96.6
--- src/sys/arch/mips/include/intr.h:1.3.96.5 Tue Feb 23 20:24:36 2010
+++ src/sys/arch/mips/include/intr.h Sun Feb 28 03:26:25 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: intr.h,v 1.3.96.5 2010/02/23 20:24:36 matt Exp $ */
+/* $NetBSD: intr.h,v 1.3.96.6 2010/02/28 03:26:25 matt Exp $ */
/*-
* Copyright (c) 2009, 2010 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -61,6 +61,7 @@
#define IPI_ISYNC __BIT(4) /* sync icache for pages */
#define IPI_KPREEMPT __BIT(5) /* schedule a kernel preemption */
+#ifdef __INTR_PRIVATE
struct splsw {
int (*splsw_splhigh)(void);
int (*splsw_splsched)(void);
@@ -74,108 +75,52 @@
void (*splsw_splx)(int);
int (*splsw_splhigh_noprof)(void);
void (*splsw_splx_noprof)(int);
- void (*splsw_setsoftintr)(uint32_t);
- void (*splsw_clrsoftintr)(uint32_t);
+ void (*splsw__setsoftintr)(uint32_t);
+ void (*splsw__clrsoftintr)(uint32_t);
int (*splsw_splintr)(uint32_t *);
void (*splsw_splcheck)(void);
};
+struct ipl_sr_map {
+ uint32_t sr_bits[_IPL_N];
+};
+#endif /* __INTR_PRIVATE */
+
typedef int ipl_t;
typedef struct {
ipl_t _spl;
} ipl_cookie_t;
-struct ipl_sr_map {
- uint32_t sr_bits[_IPL_N];
-};
-
#ifdef _KERNEL
#ifdef MULTIPROCESSOR
#define __HAVE_PREEMPTION
#define SOFTINT_KPREEMPT (SOFTINT_COUNT+0)
#endif
+#ifdef __INTR_PRIVATE
extern struct splsw mips_splsw;
extern struct ipl_sr_map ipl_sr_map;
+#endif /* __INTR_PRIVATE */
-static inline int
-splhigh(void)
-{
- return (*mips_splsw.splsw_splhigh)();
-}
-
-static inline int
-splhigh_noprof(void)
-{
- return (*mips_splsw.splsw_splhigh_noprof)();
-}
-
-static inline int
-splsched(void)
-{
- return (*mips_splsw.splsw_splsched)();
-}
-
-static inline int
-splvm(void)
-{
- return (*mips_splsw.splsw_splvm)();
-}
-
-static inline int
-splsoftserial(void)
-{
- return (*mips_splsw.splsw_splsoftserial)();
-}
-
-static inline int
-splsoftnet(void)
-{
- return (*mips_splsw.splsw_splsoftnet)();
-}
-
-static inline int
-splsoftbio(void)
-{
- return (*mips_splsw.splsw_splsoftbio)();
-}
-
-static inline int
-splsoftclock(void)
-{
- return (*mips_splsw.splsw_splsoftclock)();
-}
-
-static inline void
-spl0(void)
-{
- (*mips_splsw.splsw_spl0)();
-}
-
-static inline void
-splx(int s)
-{
- (*mips_splsw.splsw_splx)(s);
-}
-
-static inline void
-splx_noprof(int s)
-{
- (*mips_splsw.splsw_splx_noprof)(s);
-}
-
-static inline void
-_setsoftintr(uint32_t m)
-{
- (*mips_splsw.splsw_setsoftintr)(m);
-}
-
-static inline void
-_clrsoftintr(uint32_t m)
-{
- (*mips_splsw.splsw_clrsoftintr)(m);
-}
+int splhigh(void);
+int splhigh_noprof(void);
+int splsched(void);
+int splvm(void);
+int splsoftserial(void);
+int splsoftnet(void);
+int splsoftbio(void);
+int splsoftclock(void);
+int splraise(int);
+void splx(int);
+void splx_noprof(int);
+void spl0(void);
+int splintr(uint32_t *);
+void _setsoftintr(uint32_t);
+void _clrsoftintr(uint32_t);
+/*
+ * These make no sense *NOT* to be inlined.
+ */
static inline ipl_cookie_t
makeiplcookie(ipl_t s)
{
@@ -183,22 +128,10 @@
}
static inline int
-splraise(int s)
-{
-return (*mips_splsw.splsw_splraise)(s);
-}
-
-static inline int
splraiseipl(ipl_cookie_t icookie)
{
return splraise(icookie._spl);
}
-static inline int
-splintr(uint32_t *p)
-{
- return (*mips_splsw.splsw_splintr)(p);
-}
-
#endif /* _KERNEL */
#endif /* _MIPS_INTR_H_ */
CVS commit: [matt-nb5-mips64] src/sys/arch/mips
Module Name:src Committed By: matt Date: Sun Feb 28 03:28:02 UTC 2010 Modified Files: src/sys/arch/mips/adm5120 [matt-nb5-mips64]: adm5120_intr.c src/sys/arch/mips/alchemy [matt-nb5-mips64]: au_icu.c src/sys/arch/mips/atheros [matt-nb5-mips64]: ar5312_intr.c ar5315_intr.c src/sys/arch/mips/mips [matt-nb5-mips64]: genassym.cf src/sys/arch/mips/rmi [matt-nb5-mips64]: rmixl_intr.c Log Message: Add #define __INTR_PRIVATE To generate a diff of this commit: cvs rdiff -u -r1.3.18.3 -r1.3.18.4 src/sys/arch/mips/adm5120/adm5120_intr.c cvs rdiff -u -r1.23.18.2 -r1.23.18.3 src/sys/arch/mips/alchemy/au_icu.c cvs rdiff -u -r1.6.28.3 -r1.6.28.4 src/sys/arch/mips/atheros/ar5312_intr.c cvs rdiff -u -r1.5.28.3 -r1.5.28.4 src/sys/arch/mips/atheros/ar5315_intr.c cvs rdiff -u -r1.44.12.18 -r1.44.12.19 src/sys/arch/mips/mips/genassym.cf cvs rdiff -u -r1.1.2.13 -r1.1.2.14 src/sys/arch/mips/rmi/rmixl_intr.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [matt-nb5-mips64] src/sys/arch/mips
Module Name:src Committed By: matt Date: Sun Feb 28 03:28:02 UTC 2010 Modified Files: src/sys/arch/mips/adm5120 [matt-nb5-mips64]: adm5120_intr.c src/sys/arch/mips/alchemy [matt-nb5-mips64]: au_icu.c src/sys/arch/mips/atheros [matt-nb5-mips64]: ar5312_intr.c ar5315_intr.c src/sys/arch/mips/mips [matt-nb5-mips64]: genassym.cf src/sys/arch/mips/rmi [matt-nb5-mips64]: rmixl_intr.c Log Message: Add #define __INTR_PRIVATE To generate a diff of this commit: cvs rdiff -u -r1.3.18.3 -r1.3.18.4 src/sys/arch/mips/adm5120/adm5120_intr.c cvs rdiff -u -r1.23.18.2 -r1.23.18.3 src/sys/arch/mips/alchemy/au_icu.c cvs rdiff -u -r1.6.28.3 -r1.6.28.4 src/sys/arch/mips/atheros/ar5312_intr.c cvs rdiff -u -r1.5.28.3 -r1.5.28.4 src/sys/arch/mips/atheros/ar5315_intr.c cvs rdiff -u -r1.44.12.18 -r1.44.12.19 src/sys/arch/mips/mips/genassym.cf cvs rdiff -u -r1.1.2.13 -r1.1.2.14 src/sys/arch/mips/rmi/rmixl_intr.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/mips/adm5120/adm5120_intr.c diff -u src/sys/arch/mips/adm5120/adm5120_intr.c:1.3.18.3 src/sys/arch/mips/adm5120/adm5120_intr.c:1.3.18.4 --- src/sys/arch/mips/adm5120/adm5120_intr.c:1.3.18.3 Tue Feb 23 20:25:57 2010 +++ src/sys/arch/mips/adm5120/adm5120_intr.c Sun Feb 28 03:28:01 2010 @@ -1,4 +1,4 @@ -/* $NetBSD: adm5120_intr.c,v 1.3.18.3 2010/02/23 20:25:57 matt Exp $ */ +/* $NetBSD: adm5120_intr.c,v 1.3.18.4 2010/02/28 03:28:01 matt Exp $ */ /*- * Copyright (c) 2007 Ruslan Ermilov and Vsevolod Lobko. @@ -67,9 +67,10 @@ */ #include sys/cdefs.h -__KERNEL_RCSID(0, $NetBSD: adm5120_intr.c,v 1.3.18.3 2010/02/23 20:25:57 matt Exp $); +__KERNEL_RCSID(0, $NetBSD: adm5120_intr.c,v 1.3.18.4 2010/02/28 03:28:01 matt Exp $); #include opt_ddb.h +#define __INTR_PRIVATE #include sys/param.h #include sys/queue.h Index: src/sys/arch/mips/alchemy/au_icu.c diff -u src/sys/arch/mips/alchemy/au_icu.c:1.23.18.2 src/sys/arch/mips/alchemy/au_icu.c:1.23.18.3 --- src/sys/arch/mips/alchemy/au_icu.c:1.23.18.2 Tue Feb 23 20:25:57 2010 +++ src/sys/arch/mips/alchemy/au_icu.c Sun Feb 28 03:28:01 2010 @@ -1,4 +1,4 @@ -/* $NetBSD: au_icu.c,v 1.23.18.2 2010/02/23 20:25:57 matt Exp $ */ +/* $NetBSD: au_icu.c,v 1.23.18.3 2010/02/28 03:28:01 matt Exp $ */ /*- * Copyright (c) 2006 Itronix Inc. @@ -68,9 +68,10 @@ */ #include sys/cdefs.h -__KERNEL_RCSID(0, $NetBSD: au_icu.c,v 1.23.18.2 2010/02/23 20:25:57 matt Exp $); +__KERNEL_RCSID(0, $NetBSD: au_icu.c,v 1.23.18.3 2010/02/28 03:28:01 matt Exp $); #include opt_ddb.h +#define __INTR_PRIVATE #include sys/param.h #include sys/queue.h Index: src/sys/arch/mips/atheros/ar5312_intr.c diff -u src/sys/arch/mips/atheros/ar5312_intr.c:1.6.28.3 src/sys/arch/mips/atheros/ar5312_intr.c:1.6.28.4 --- src/sys/arch/mips/atheros/ar5312_intr.c:1.6.28.3 Tue Feb 23 20:25:57 2010 +++ src/sys/arch/mips/atheros/ar5312_intr.c Sun Feb 28 03:28:01 2010 @@ -1,4 +1,4 @@ -/* $Id: ar5312_intr.c,v 1.6.28.3 2010/02/23 20:25:57 matt Exp $ */ +/* $Id: ar5312_intr.c,v 1.6.28.4 2010/02/28 03:28:01 matt Exp $ */ /* * Copyright (c) 2006 Urbana-Champaign Independent Media Center. * Copyright (c) 2006 Garrett D'Amore. @@ -41,7 +41,9 @@ */ #include sys/cdefs.h -__KERNEL_RCSID(0, $NetBSD: ar5312_intr.c,v 1.6.28.3 2010/02/23 20:25:57 matt Exp $); +__KERNEL_RCSID(0, $NetBSD: ar5312_intr.c,v 1.6.28.4 2010/02/28 03:28:01 matt Exp $); + +#define __INTR_PRIVATE #include sys/param.h #include sys/queue.h Index: src/sys/arch/mips/atheros/ar5315_intr.c diff -u src/sys/arch/mips/atheros/ar5315_intr.c:1.5.28.3 src/sys/arch/mips/atheros/ar5315_intr.c:1.5.28.4 --- src/sys/arch/mips/atheros/ar5315_intr.c:1.5.28.3 Tue Feb 23 20:25:57 2010 +++ src/sys/arch/mips/atheros/ar5315_intr.c Sun Feb 28 03:28:01 2010 @@ -1,4 +1,4 @@ -/* $Id: ar5315_intr.c,v 1.5.28.3 2010/02/23 20:25:57 matt Exp $ */ +/* $Id: ar5315_intr.c,v 1.5.28.4 2010/02/28 03:28:01 matt Exp $ */ /* * Copyright (c) 2006 Urbana-Champaign Independent Media Center. * Copyright (c) 2006 Garrett D'Amore. @@ -41,7 +41,9 @@ */ #include sys/cdefs.h -__KERNEL_RCSID(0, $NetBSD: ar5315_intr.c,v 1.5.28.3 2010/02/23 20:25:57 matt Exp $); +__KERNEL_RCSID(0, $NetBSD: ar5315_intr.c,v 1.5.28.4 2010/02/28 03:28:01 matt Exp $); + +#define __INTR_PRIVATE #include sys/param.h #include sys/queue.h Index: src/sys/arch/mips/mips/genassym.cf diff -u src/sys/arch/mips/mips/genassym.cf:1.44.12.18 src/sys/arch/mips/mips/genassym.cf:1.44.12.19 --- src/sys/arch/mips/mips/genassym.cf:1.44.12.18 Tue Feb 23 20:33:48 2010 +++ src/sys/arch/mips/mips/genassym.cf Sun Feb 28 03:28:01 2010 @@ -1,4 +1,4 @@ -# $NetBSD: genassym.cf,v 1.44.12.18 2010/02/23 20:33:48 matt Exp $ +# $NetBSD: genassym.cf,v 1.44.12.19 2010/02/28 03:28:01 matt Exp $ # # Copyright (c) 1992, 1993 # The Regents of the University of California. All rights reserved. @@ -71,6 +71,7 @@ # from
CVS commit: [matt-nb5-mips64] src/sys/arch/mips/mips
Module Name:src Committed By: matt Date: Sun Feb 28 03:28:54 UTC 2010 Modified Files: src/sys/arch/mips/mips [matt-nb5-mips64]: lock_stubs.S locore.S mipsX_subr.S Log Message: Change from indirect calls to direct calls to spl* routines. To generate a diff of this commit: cvs rdiff -u -r1.9.18.9 -r1.9.18.10 src/sys/arch/mips/mips/lock_stubs.S cvs rdiff -u -r1.167.38.16 -r1.167.38.17 src/sys/arch/mips/mips/locore.S cvs rdiff -u -r1.26.36.1.2.28 -r1.26.36.1.2.29 \ src/sys/arch/mips/mips/mipsX_subr.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [matt-nb5-mips64] src/sys/arch/mips/mips
Module Name:src Committed By: matt Date: Sun Feb 28 03:28:54 UTC 2010 Modified Files: src/sys/arch/mips/mips [matt-nb5-mips64]: lock_stubs.S locore.S mipsX_subr.S Log Message: Change from indirect calls to direct calls to spl* routines. To generate a diff of this commit: cvs rdiff -u -r1.9.18.9 -r1.9.18.10 src/sys/arch/mips/mips/lock_stubs.S cvs rdiff -u -r1.167.38.16 -r1.167.38.17 src/sys/arch/mips/mips/locore.S cvs rdiff -u -r1.26.36.1.2.28 -r1.26.36.1.2.29 \ src/sys/arch/mips/mips/mipsX_subr.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/mips/mips/lock_stubs.S diff -u src/sys/arch/mips/mips/lock_stubs.S:1.9.18.9 src/sys/arch/mips/mips/lock_stubs.S:1.9.18.10 --- src/sys/arch/mips/mips/lock_stubs.S:1.9.18.9 Sat Feb 27 19:22:47 2010 +++ src/sys/arch/mips/mips/lock_stubs.S Sun Feb 28 03:28:54 2010 @@ -1,4 +1,4 @@ -/* $NetBSD: lock_stubs.S,v 1.9.18.9 2010/02/27 19:22:47 snj Exp $ */ +/* $NetBSD: lock_stubs.S,v 1.9.18.10 2010/02/28 03:28:54 matt Exp $ */ /*- * Copyright (c) 2007 The NetBSD Foundation, Inc. @@ -254,8 +254,7 @@ * (only uses a0-a3 and v0-v1) */ move t3, ra # need to save ra - PTR_L t9, _C_LABEL(mips_splsw) + SPLSW_SPLRAISE - jalr t9 + jal _C_LABEL(splraise) move a0, ta0 move ra, t3 # move ra back #ifdef PARANOIA @@ -468,8 +467,7 @@ * call splraise (only uses a0-a3, v0-v1, and ra) */ move t3, ra - PTR_L t9, _C_LABEL(mips_splsw) + SPLSW_SPLRAISE - jalr t9 + jal _C_LABEL(splraise) nop move ra, t3 @@ -630,17 +628,18 @@ #endif /* PARANOIA */ beq a0, a1, 1f # if oldspl == cpl - move t9, ra # no reason to drop ipl + nop# no reason to drop ipl bltz t0, 1f # there are still holders - move t9, ra # so don't drop IPL + nop# so don't drop IPL /* * Mutex count is zero so we need to restore the old IPL */ - PTR_L t9, _C_LABEL(mips_splsw) + SPLSW_SPLX + j _C_LABEL(splx) + nop 1: - j t9 + j ra nop #if defined(DIAGNOSTIC) 2: Index: src/sys/arch/mips/mips/locore.S diff -u src/sys/arch/mips/mips/locore.S:1.167.38.16 src/sys/arch/mips/mips/locore.S:1.167.38.17 --- src/sys/arch/mips/mips/locore.S:1.167.38.16 Thu Feb 25 05:45:12 2010 +++ src/sys/arch/mips/mips/locore.S Sun Feb 28 03:28:54 2010 @@ -1,4 +1,4 @@ -/* $NetBSD: locore.S,v 1.167.38.16 2010/02/25 05:45:12 matt Exp $ */ +/* $NetBSD: locore.S,v 1.167.38.17 2010/02/28 03:28:54 matt Exp $ */ /* * Copyright (c) 1992, 1993 @@ -148,8 +148,7 @@ /* * Raise to IPLHIGH */ - PTR_L t9, _C_LABEL(mips_splsw) + SPLSW_SPLHIGH - jalr t9# splhigh() + jal _C_LABEL(splhigh_noprof) # go to splhigh nop /* * Now enable interrupts (but they are all masked). @@ -236,8 +235,9 @@ /* * Switch to new context. */ - PTR_L t9, _C_LABEL(mips_locoresw) + MIPSX_CPU_SWITCH_RESUME - jalr t9 + .globl _C_LABEL(__cpu_switchto_fixup) +_C_LABEL(__cpu_switchto_fixup): + jal _C_LABEL(mips_cpu_switch_resume) move a0, MIPS_CURLWP PTR_L t2, L_CPU(MIPS_CURLWP) @@ -247,7 +247,6 @@ /* Check for restartable atomic sequences (RAS) */ PTR_L a0, L_PROC(MIPS_CURLWP) # argument to ras_lookup PTR_L s5, L_ADDR(MIPS_CURLWP) - nop # patchable load deay slot PTR_L v1, P_RASLIST(a0) # get raslist beqz v1, 1f# skip call if empty nop @@ -374,7 +373,6 @@ PTR_L s1, L_CPU(MIPS_CURLWP) # get curcpu() nop # patchable load delay slot PTR_S MIPS_CURLWP, CPU_INFO_CURLWP(s1) #... - nop # patchable slot move s2, sp # remember sp move s3, t0 # remember curpcb @@ -387,19 +385,18 @@ move MIPS_CURLWP, s0# restore curlwp PTR_S MIPS_CURLWP, CPU_INFO_CURLWP(s1) # + REG_L ra, CALLFRAME_RA(sp) # load early since we use it + REG_PROLOGUE REG_L s0, U_PCB_CONTEXT+SF_REG_S0(s3) # restore the saved - nop # patchable delay slot REG_L s1, U_PCB_CONTEXT+SF_REG_S1(s3) #registers that we - nop # patchable delay slot REG_L s2, U_PCB_CONTEXT+SF_REG_S2(s3) #used REG_L s3, U_PCB_CONTEXT+SF_REG_S3(s3) REG_EPILOGUE /* - * Almost everything (all except sp) is restored so we ca retrn. + * Almost everything (all except sp) is restored so we can return. */ - REG_L ra, CALLFRAME_RA(sp) j ra PTR_ADDU sp, CALLFRAME_SIZ END(softint_fast_dispatch) Index: src/sys/arch/mips/mips/mipsX_subr.S diff -u src/sys/arch/mips/mips/mipsX_subr.S:1.26.36.1.2.28 src/sys/arch/mips/mips/mipsX_subr.S:1.26.36.1.2.29 --- src/sys/arch/mips/mips/mipsX_subr.S:1.26.36.1.2.28 Sat Feb 27 20:32:04 2010 +++ src/sys/arch/mips/mips/mipsX_subr.S Sun Feb 28 03:28:54 2010 @@ -1,4 +1,4 @@ -/* $NetBSD: mipsX_subr.S,v 1.26.36.1.2.28 2010/02/27 20:32:04 snj Exp $ */ +/* $NetBSD: mipsX_subr.S,v 1.26.36.1.2.29 2010/02/28 03:28:54 matt Exp $ */ /* * Copyright 2002 Wasabi Systems, Inc. @@ -1117,8 +1117,7 @@ /* * We first need to get to IPL_HIGH so that interrupts are masked. */ - PTR_L t9,
CVS commit: [matt-nb5-mips64] src/sys/arch/mips/mips
Module Name:src Committed By: matt Date: Sun Feb 28 03:30:35 UTC 2010 Modified Files: src/sys/arch/mips/mips [matt-nb5-mips64]: mips_machdep.c Log Message: #define __INTR_PRIVATE Add calls to fixup the splcalls and fixup the call to mips_cpu_switch_resume in cpu_switchto (which remove an indirect calls from a critical routine). To generate a diff of this commit: cvs rdiff -u -r1.205.4.1.2.1.2.37 -r1.205.4.1.2.1.2.38 \ src/sys/arch/mips/mips/mips_machdep.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/mips/mips/mips_machdep.c diff -u src/sys/arch/mips/mips/mips_machdep.c:1.205.4.1.2.1.2.37 src/sys/arch/mips/mips/mips_machdep.c:1.205.4.1.2.1.2.38 --- src/sys/arch/mips/mips/mips_machdep.c:1.205.4.1.2.1.2.37 Sat Feb 27 07:58:52 2010 +++ src/sys/arch/mips/mips/mips_machdep.c Sun Feb 28 03:30:34 2010 @@ -1,4 +1,4 @@ -/* $NetBSD: mips_machdep.c,v 1.205.4.1.2.1.2.37 2010/02/27 07:58:52 matt Exp $ */ +/* $NetBSD: mips_machdep.c,v 1.205.4.1.2.1.2.38 2010/02/28 03:30:34 matt Exp $ */ /* * Copyright 2002 Wasabi Systems, Inc. @@ -112,7 +112,9 @@ #include sys/cdefs.h /* RCS ID Copyright macro defns */ -__KERNEL_RCSID(0, $NetBSD: mips_machdep.c,v 1.205.4.1.2.1.2.37 2010/02/27 07:58:52 matt Exp $); +__KERNEL_RCSID(0, $NetBSD: mips_machdep.c,v 1.205.4.1.2.1.2.38 2010/02/28 03:30:34 matt Exp $); + +#define __INTR_PRIVATE #include opt_cputype.h #include opt_compat_netbsd32.h @@ -968,6 +970,13 @@ cpu_reboot(RB_HALT, NULL); } + /* + * Now that the splsw and locoresw have been filled in, fixup the + * jumps to their stubs to instead jump to the real routines. + */ + fixup_mips_cpu_switch_resume(); + fixup_splcalls(); + /* XXX simonb: ugg, another ugly #ifdef check... */ #if (defined(MIPS3) !defined(MIPS3_5900)) || defined(MIPS32) || defined(MIPS64) /*
CVS commit: [matt-nb5-mips64] src/sys/arch/mips/mips
Module Name:src Committed By: matt Date: Sun Feb 28 03:30:35 UTC 2010 Modified Files: src/sys/arch/mips/mips [matt-nb5-mips64]: mips_machdep.c Log Message: #define __INTR_PRIVATE Add calls to fixup the splcalls and fixup the call to mips_cpu_switch_resume in cpu_switchto (which remove an indirect calls from a critical routine). To generate a diff of this commit: cvs rdiff -u -r1.205.4.1.2.1.2.37 -r1.205.4.1.2.1.2.38 \ src/sys/arch/mips/mips/mips_machdep.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [matt-nb5-mips64] src/sys/arch
Module Name:src Committed By: matt Date: Sun Feb 28 03:32:23 UTC 2010 Modified Files: src/sys/arch/algor/algor [matt-nb5-mips64]: algor_p4032_intr.c algor_p5064_intr.c algor_p6032_intr.c interrupt.c src/sys/arch/evbmips/malta [matt-nb5-mips64]: malta_intr.c src/sys/arch/sbmips/sbmips [matt-nb5-mips64]: sb1250_icu.c Log Message: #define __INTR_PRIVATE To generate a diff of this commit: cvs rdiff -u -r1.20.16.1 -r1.20.16.2 \ src/sys/arch/algor/algor/algor_p4032_intr.c cvs rdiff -u -r1.23.16.1 -r1.23.16.2 \ src/sys/arch/algor/algor/algor_p5064_intr.c cvs rdiff -u -r1.16.16.1 -r1.16.16.2 \ src/sys/arch/algor/algor/algor_p6032_intr.c cvs rdiff -u -r1.13.18.3 -r1.13.18.4 src/sys/arch/algor/algor/interrupt.c cvs rdiff -u -r1.19.16.5 -r1.19.16.6 src/sys/arch/evbmips/malta/malta_intr.c cvs rdiff -u -r1.9.36.4 -r1.9.36.5 src/sys/arch/sbmips/sbmips/sb1250_icu.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/algor/algor/algor_p4032_intr.c diff -u src/sys/arch/algor/algor/algor_p4032_intr.c:1.20.16.1 src/sys/arch/algor/algor/algor_p4032_intr.c:1.20.16.2 --- src/sys/arch/algor/algor/algor_p4032_intr.c:1.20.16.1 Wed Feb 24 00:09:31 2010 +++ src/sys/arch/algor/algor/algor_p4032_intr.c Sun Feb 28 03:32:23 2010 @@ -1,4 +1,4 @@ -/* $NetBSD: algor_p4032_intr.c,v 1.20.16.1 2010/02/24 00:09:31 matt Exp $ */ +/* $NetBSD: algor_p4032_intr.c,v 1.20.16.2 2010/02/28 03:32:23 matt Exp $ */ /*- * Copyright (c) 2001 The NetBSD Foundation, Inc. @@ -38,9 +38,10 @@ */ #include sys/cdefs.h -__KERNEL_RCSID(0, $NetBSD: algor_p4032_intr.c,v 1.20.16.1 2010/02/24 00:09:31 matt Exp $); +__KERNEL_RCSID(0, $NetBSD: algor_p4032_intr.c,v 1.20.16.2 2010/02/28 03:32:23 matt Exp $); #include opt_ddb.h +#define __INTR_PRIVATE #include sys/param.h #include sys/queue.h Index: src/sys/arch/algor/algor/algor_p5064_intr.c diff -u src/sys/arch/algor/algor/algor_p5064_intr.c:1.23.16.1 src/sys/arch/algor/algor/algor_p5064_intr.c:1.23.16.2 --- src/sys/arch/algor/algor/algor_p5064_intr.c:1.23.16.1 Wed Feb 24 00:09:31 2010 +++ src/sys/arch/algor/algor/algor_p5064_intr.c Sun Feb 28 03:32:23 2010 @@ -1,4 +1,4 @@ -/* $NetBSD: algor_p5064_intr.c,v 1.23.16.1 2010/02/24 00:09:31 matt Exp $ */ +/* $NetBSD: algor_p5064_intr.c,v 1.23.16.2 2010/02/28 03:32:23 matt Exp $ */ /*- * Copyright (c) 2001 The NetBSD Foundation, Inc. @@ -38,9 +38,10 @@ */ #include sys/cdefs.h -__KERNEL_RCSID(0, $NetBSD: algor_p5064_intr.c,v 1.23.16.1 2010/02/24 00:09:31 matt Exp $); +__KERNEL_RCSID(0, $NetBSD: algor_p5064_intr.c,v 1.23.16.2 2010/02/28 03:32:23 matt Exp $); #include opt_ddb.h +#define __INTR_PRIVATE #include sys/param.h #include sys/queue.h Index: src/sys/arch/algor/algor/algor_p6032_intr.c diff -u src/sys/arch/algor/algor/algor_p6032_intr.c:1.16.16.1 src/sys/arch/algor/algor/algor_p6032_intr.c:1.16.16.2 --- src/sys/arch/algor/algor/algor_p6032_intr.c:1.16.16.1 Wed Feb 24 00:09:31 2010 +++ src/sys/arch/algor/algor/algor_p6032_intr.c Sun Feb 28 03:32:23 2010 @@ -1,4 +1,4 @@ -/* $NetBSD: algor_p6032_intr.c,v 1.16.16.1 2010/02/24 00:09:31 matt Exp $ */ +/* $NetBSD: algor_p6032_intr.c,v 1.16.16.2 2010/02/28 03:32:23 matt Exp $ */ /*- * Copyright (c) 2001 The NetBSD Foundation, Inc. @@ -37,9 +37,10 @@ */ #include sys/cdefs.h -__KERNEL_RCSID(0, $NetBSD: algor_p6032_intr.c,v 1.16.16.1 2010/02/24 00:09:31 matt Exp $); +__KERNEL_RCSID(0, $NetBSD: algor_p6032_intr.c,v 1.16.16.2 2010/02/28 03:32:23 matt Exp $); #include opt_ddb.h +#define __INTR_PRIVATE #include sys/param.h #include sys/queue.h Index: src/sys/arch/algor/algor/interrupt.c diff -u src/sys/arch/algor/algor/interrupt.c:1.13.18.3 src/sys/arch/algor/algor/interrupt.c:1.13.18.4 --- src/sys/arch/algor/algor/interrupt.c:1.13.18.3 Wed Feb 24 00:09:31 2010 +++ src/sys/arch/algor/algor/interrupt.c Sun Feb 28 03:32:23 2010 @@ -1,4 +1,4 @@ -/* $NetBSD: interrupt.c,v 1.13.18.3 2010/02/24 00:09:31 matt Exp $ */ +/* $NetBSD: interrupt.c,v 1.13.18.4 2010/02/28 03:32:23 matt Exp $ */ /*- * Copyright (c) 2001 The NetBSD Foundation, Inc. @@ -30,7 +30,9 @@ */ #include sys/cdefs.h -__KERNEL_RCSID(0, $NetBSD: interrupt.c,v 1.13.18.3 2010/02/24 00:09:31 matt Exp $); +__KERNEL_RCSID(0, $NetBSD: interrupt.c,v 1.13.18.4 2010/02/28 03:32:23 matt Exp $); + +#define __INTR_PRIVATE #include opt_algor_p4032.h #include opt_algor_p5064.h Index: src/sys/arch/evbmips/malta/malta_intr.c diff -u src/sys/arch/evbmips/malta/malta_intr.c:1.19.16.5 src/sys/arch/evbmips/malta/malta_intr.c:1.19.16.6 --- src/sys/arch/evbmips/malta/malta_intr.c:1.19.16.5 Tue Feb 23 20:24:37 2010 +++ src/sys/arch/evbmips/malta/malta_intr.c Sun Feb 28 03:32:23 2010 @@ -1,4 +1,4 @@ -/* $NetBSD: malta_intr.c,v 1.19.16.5 2010/02/23 20:24:37 matt Exp $ */ +/* $NetBSD: malta_intr.c,v 1.19.16.6 2010/02/28 03:32:23 matt Exp $ */ /* * Copyright 2001, 2002
CVS commit: [matt-nb5-mips64] src/sys/arch
Module Name:src Committed By: matt Date: Sun Feb 28 03:32:23 UTC 2010 Modified Files: src/sys/arch/algor/algor [matt-nb5-mips64]: algor_p4032_intr.c algor_p5064_intr.c algor_p6032_intr.c interrupt.c src/sys/arch/evbmips/malta [matt-nb5-mips64]: malta_intr.c src/sys/arch/sbmips/sbmips [matt-nb5-mips64]: sb1250_icu.c Log Message: #define __INTR_PRIVATE To generate a diff of this commit: cvs rdiff -u -r1.20.16.1 -r1.20.16.2 \ src/sys/arch/algor/algor/algor_p4032_intr.c cvs rdiff -u -r1.23.16.1 -r1.23.16.2 \ src/sys/arch/algor/algor/algor_p5064_intr.c cvs rdiff -u -r1.16.16.1 -r1.16.16.2 \ src/sys/arch/algor/algor/algor_p6032_intr.c cvs rdiff -u -r1.13.18.3 -r1.13.18.4 src/sys/arch/algor/algor/interrupt.c cvs rdiff -u -r1.19.16.5 -r1.19.16.6 src/sys/arch/evbmips/malta/malta_intr.c cvs rdiff -u -r1.9.36.4 -r1.9.36.5 src/sys/arch/sbmips/sbmips/sb1250_icu.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [matt-nb5-mips64] src/sys/arch/cobalt
Module Name:src Committed By: matt Date: Sun Feb 28 04:04:46 UTC 2010 Modified Files: src/sys/arch/cobalt/cobalt [matt-nb5-mips64]: interrupt.c machdep.c src/sys/arch/cobalt/conf [matt-nb5-mips64]: GENERIC std.cobalt src/sys/arch/cobalt/include [matt-nb5-mips64]: intr.h Added Files: src/sys/arch/cobalt/conf [matt-nb5-mips64]: GENERIC64 src/sys/arch/cobalt/include [matt-nb5-mips64]: netbsd32_machdep.h Log Message: Adapt to new common interrupts. Enable cobalt64 To generate a diff of this commit: cvs rdiff -u -r1.3.16.1 -r1.3.16.2 src/sys/arch/cobalt/cobalt/interrupt.c cvs rdiff -u -r1.98.10.2 -r1.98.10.3 src/sys/arch/cobalt/cobalt/machdep.c cvs rdiff -u -r1.119 -r1.119.6.1 src/sys/arch/cobalt/conf/GENERIC cvs rdiff -u -r0 -r1.1.4.2 src/sys/arch/cobalt/conf/GENERIC64 cvs rdiff -u -r1.13 -r1.13.80.1 src/sys/arch/cobalt/conf/std.cobalt cvs rdiff -u -r1.32.12.1 -r1.32.12.2 src/sys/arch/cobalt/include/intr.h cvs rdiff -u -r0 -r1.1.4.2 src/sys/arch/cobalt/include/netbsd32_machdep.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [matt-nb5-mips64] src/sys/arch/cobalt
Module Name:src
Committed By: matt
Date: Sun Feb 28 04:04:46 UTC 2010
Modified Files:
src/sys/arch/cobalt/cobalt [matt-nb5-mips64]: interrupt.c machdep.c
src/sys/arch/cobalt/conf [matt-nb5-mips64]: GENERIC std.cobalt
src/sys/arch/cobalt/include [matt-nb5-mips64]: intr.h
Added Files:
src/sys/arch/cobalt/conf [matt-nb5-mips64]: GENERIC64
src/sys/arch/cobalt/include [matt-nb5-mips64]: netbsd32_machdep.h
Log Message:
Adapt to new common interrupts.
Enable cobalt64
To generate a diff of this commit:
cvs rdiff -u -r1.3.16.1 -r1.3.16.2 src/sys/arch/cobalt/cobalt/interrupt.c
cvs rdiff -u -r1.98.10.2 -r1.98.10.3 src/sys/arch/cobalt/cobalt/machdep.c
cvs rdiff -u -r1.119 -r1.119.6.1 src/sys/arch/cobalt/conf/GENERIC
cvs rdiff -u -r0 -r1.1.4.2 src/sys/arch/cobalt/conf/GENERIC64
cvs rdiff -u -r1.13 -r1.13.80.1 src/sys/arch/cobalt/conf/std.cobalt
cvs rdiff -u -r1.32.12.1 -r1.32.12.2 src/sys/arch/cobalt/include/intr.h
cvs rdiff -u -r0 -r1.1.4.2 src/sys/arch/cobalt/include/netbsd32_machdep.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/cobalt/cobalt/interrupt.c
diff -u src/sys/arch/cobalt/cobalt/interrupt.c:1.3.16.1 src/sys/arch/cobalt/cobalt/interrupt.c:1.3.16.2
--- src/sys/arch/cobalt/cobalt/interrupt.c:1.3.16.1 Fri Feb 5 07:39:52 2010
+++ src/sys/arch/cobalt/cobalt/interrupt.c Sun Feb 28 04:04:46 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: interrupt.c,v 1.3.16.1 2010/02/05 07:39:52 matt Exp $ */
+/* $NetBSD: interrupt.c,v 1.3.16.2 2010/02/28 04:04:46 matt Exp $ */
/*-
* Copyright (c) 2006 Izumi Tsutsui. All rights reserved.
@@ -79,7 +79,9 @@
*/
#include sys/cdefs.h
-__KERNEL_RCSID(0, $NetBSD: interrupt.c,v 1.3.16.1 2010/02/05 07:39:52 matt Exp $);
+__KERNEL_RCSID(0, $NetBSD: interrupt.c,v 1.3.16.2 2010/02/28 04:04:46 matt Exp $);
+
+#define __INTR_PRIVATE
#include sys/param.h
#include sys/malloc.h
@@ -139,11 +141,27 @@
static int icu_intr(void *);
static void icu_set(void);
+static const struct ipl_sr_map cobalt_ipl_sr_map = {
+.sr_bits = {
+ [IPL_NONE] = 0,
+ [IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0,
+ [IPL_SOFTBIO] = MIPS_SOFT_INT_MASK_0,
+ [IPL_SOFTNET] = MIPS_SOFT_INT_MASK,
+ [IPL_SOFTSERIAL] = MIPS_SOFT_INT_MASK,
+ [IPL_VM] = MIPS_SOFT_INT_MASK | MIPS_INT_MASK_1
+| MIPS_INT_MASK_2 | MIPS_INT_MASK_3
+| MIPS_INT_MASK_4,
+ [IPL_SCHED] = MIPS_INT_MASK,
+ [IPL_HIGH] = MIPS_INT_MASK,
+},
+};
+
void
intr_init(void)
{
int i;
+ ipl_sr_map = cobalt_ipl_sr_map;
/*
* Initialize CPU interrupts.
*/
@@ -388,109 +406,65 @@
}
}
+static void inline
+intr_handle(struct cpu_intrhead *intr)
+{
+ struct cobalt_intrhand * const ih = intr-intr_ih;
+ if (__predict_true(ih-ih_func != NULL)
+ __predict_true((*ih-ih_func)(ih-ih_arg))) {
+ intr-intr_evcnt.ev_count++;
+ }
+}
+
void
-cpu_intr(uint32_t status, uint32_t cause, uint32_t pc, uint32_t ipending)
+cpu_intr(int ppl, vaddr_t pc, uint32_t status)
{
- struct clockframe cf;
- struct cobalt_intrhand *ih;
- struct cpu_info *ci;
- uint32_t handled;
+ uint32_t pending;
+ int ipl;
- handled = 0;
- ci = curcpu();
- ci-ci_idepth++;
uvmexp.intrs++;
- if (ipending MIPS_INT_MASK_5) {
- /* call the common MIPS3 clock interrupt handler */
- cf.pc = pc;
- cf.sr = status;
- mips3_clockintr(cf);
-
- handled |= MIPS_INT_MASK_5;
- }
- _splset((status handled) | MIPS_SR_INT_IE);
-
- if (__predict_false(ipending MIPS_INT_MASK_0)) {
- /* GT64x11 timer0 */
- volatile uint32_t *irq_src =
- (uint32_t *)MIPS_PHYS_TO_KSEG1(GT_BASE + GT_INTR_CAUSE);
-
- if (__predict_true((*irq_src T0EXP) != 0)) {
- /* GT64x11 timer is no longer used for hardclock(9) */
- *irq_src = 0;
+ while (ppl (ipl = splintr(pending))) {
+ splx(ipl);
+ if (pending MIPS_INT_MASK_5) {
+ struct clockframe cf;
+ /* call the common MIPS3 clock interrupt handler */
+ cf.pc = pc;
+ cf.sr = status;
+ cf.intr = (curcpu()-ci_idepth 1);
+ mips3_clockintr(cf);
}
- handled |= MIPS_INT_MASK_0;
- }
- if (ipending MIPS_INT_MASK_3) {
- /* 16650 serial */
- ih = cpu_intrtab[3].intr_ih;
- if (__predict_true(ih-ih_func != NULL)) {
- if (__predict_true((*ih-ih_func)(ih-ih_arg))) {
-cpu_intrtab[3].intr_evcnt.ev_count++;
+ if (__predict_false(pending MIPS_INT_MASK_0)) {
+ /* GT64x11 timer0 */
+ volatile uint32_t *irq_src =
+ (uint32_t *)MIPS_PHYS_TO_KSEG1(GT_BASE + GT_INTR_CAUSE);
+
+ if (__predict_true((*irq_src T0EXP) != 0)) {
+/* GT64x11 timer is no longer used for hardclock(9) */
+*irq_src = 0;
}
}
- handled |= MIPS_INT_MASK_3;
- }
- _splset((status handled) | MIPS_SR_INT_IE);
- if (ipending MIPS_INT_MASK_1) {
- /* tulip primary */
- ih = cpu_intrtab[1].intr_ih;
- if (__predict_true(ih-ih_func != NULL)) {
- if (__predict_true((*ih-ih_func)(ih-ih_arg))) {
-cpu_intrtab[1].intr_evcnt.ev_count++;
- }
+ if (pending MIPS_INT_MASK_3) {
CVS commit: [matt-nb5-mips64] src/sys/arch/arc/include
Module Name:src Committed By: matt Date: Sun Feb 28 04:08:52 UTC 2010 Added Files: src/sys/arch/arc/include [matt-nb5-mips64]: netbsd32_machdep.h Log Message: arc64 needs a machine/netbsd32_machdep.h To generate a diff of this commit: cvs rdiff -u -r0 -r1.1.2.1 src/sys/arch/arc/include/netbsd32_machdep.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Added files: Index: src/sys/arch/arc/include/netbsd32_machdep.h diff -u /dev/null src/sys/arch/arc/include/netbsd32_machdep.h:1.1.2.1 --- /dev/null Sun Feb 28 04:08:52 2010 +++ src/sys/arch/arc/include/netbsd32_machdep.h Sun Feb 28 04:08:51 2010 @@ -0,0 +1,3 @@ +/* $NetBSD: netbsd32_machdep.h,v 1.1.2.1 2010/02/28 04:08:51 matt Exp $ */ + +#include mips/netbsd32_machdep.h
CVS commit: [matt-nb5-mips64] src/sys/arch/arc/include
Module Name:src Committed By: matt Date: Sun Feb 28 04:08:52 UTC 2010 Added Files: src/sys/arch/arc/include [matt-nb5-mips64]: netbsd32_machdep.h Log Message: arc64 needs a machine/netbsd32_machdep.h To generate a diff of this commit: cvs rdiff -u -r0 -r1.1.2.1 src/sys/arch/arc/include/netbsd32_machdep.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [matt-nb5-mips64] src/sys/arch/mips/include
Module Name:src Committed By: matt Date: Sat Feb 27 07:52:25 UTC 2010 Modified Files: src/sys/arch/mips/include [matt-nb5-mips64]: cpuregs.h Log Message: Add the RMI COP0 OSSCRATCH register To generate a diff of this commit: cvs rdiff -u -r1.74.28.14 -r1.74.28.15 src/sys/arch/mips/include/cpuregs.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [matt-nb5-mips64] src/sys/arch/mips
Module Name:src Committed By: matt Date: Sat Feb 27 07:58:53 UTC 2010 Modified Files: src/sys/arch/mips/conf [matt-nb5-mips64]: files.mips src/sys/arch/mips/include [matt-nb5-mips64]: cpu.h locore.h pmap.h src/sys/arch/mips/mips [matt-nb5-mips64]: mipsX_subr.S mips_machdep.c pmap.c pmap_tlb.c Added Files: src/sys/arch/mips/mips [matt-nb5-mips64]: mips_fixup.c Log Message: Add mipsXX_tlb_enter which modifies/sets a specific TLB entry with a new mapping (useful for wired TLB entries). Add mips_fixup_exceptions which will walk through the exception vectors and allows the fixup of any cpu_info references to be changed to a more MP-friendly incarnation. Define a common fixup method to use a wired TLB entry at -PAGE_SIZE allowing direct loads using a negative based from the zero register. Change varible pmap_tlb_info t pmap_tlb0_info. To generate a diff of this commit: cvs rdiff -u -r1.58.24.8 -r1.58.24.9 src/sys/arch/mips/conf/files.mips cvs rdiff -u -r1.90.16.22 -r1.90.16.23 src/sys/arch/mips/include/cpu.h cvs rdiff -u -r1.78.36.1.2.15 -r1.78.36.1.2.16 \ src/sys/arch/mips/include/locore.h cvs rdiff -u -r1.54.26.10 -r1.54.26.11 src/sys/arch/mips/include/pmap.h cvs rdiff -u -r1.26.36.1.2.26 -r1.26.36.1.2.27 \ src/sys/arch/mips/mips/mipsX_subr.S cvs rdiff -u -r0 -r1.1.2.1 src/sys/arch/mips/mips/mips_fixup.c cvs rdiff -u -r1.205.4.1.2.1.2.36 -r1.205.4.1.2.1.2.37 \ src/sys/arch/mips/mips/mips_machdep.c cvs rdiff -u -r1.179.16.18 -r1.179.16.19 src/sys/arch/mips/mips/pmap.c cvs rdiff -u -r1.1.2.4 -r1.1.2.5 src/sys/arch/mips/mips/pmap_tlb.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [matt-nb5-mips64] src/sys/arch/mips/mips
Module Name:src Committed By: matt Date: Thu Feb 25 05:24:24 UTC 2010 Modified Files: src/sys/arch/mips/mips [matt-nb5-mips64]: pmap_segtab.c Log Message: Make sure we aren't looking up a direct-mapped address. To generate a diff of this commit: cvs rdiff -u -r1.1.2.5 -r1.1.2.6 src/sys/arch/mips/mips/pmap_segtab.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [matt-nb5-mips64] src/sys/arch/mips/include
Module Name:src Committed By: matt Date: Thu Feb 25 05:24:53 UTC 2010 Modified Files: src/sys/arch/mips/include [matt-nb5-mips64]: cpu.h Log Message: Remove ci_curpm since it isn't used. To generate a diff of this commit: cvs rdiff -u -r1.90.16.21 -r1.90.16.22 src/sys/arch/mips/include/cpu.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [matt-nb5-mips64] src/sys/arch/mips
Module Name:src Committed By: matt Date: Thu Feb 25 05:45:12 UTC 2010 Modified Files: src/sys/arch/mips/include [matt-nb5-mips64]: locore.h src/sys/arch/mips/mips [matt-nb5-mips64]: locore.S locore_mips3.S mipsX_subr.S mips_machdep.c Log Message: Add mipsXX_tlb_record_asids - records what ASIDs have valid TLB entries in the TLB. Move some mips3 specific routines from locore.S to locore_mips3.S To generate a diff of this commit: cvs rdiff -u -r1.78.36.1.2.14 -r1.78.36.1.2.15 \ src/sys/arch/mips/include/locore.h cvs rdiff -u -r1.167.38.15 -r1.167.38.16 src/sys/arch/mips/mips/locore.S cvs rdiff -u -r1.93.38.6 -r1.93.38.7 src/sys/arch/mips/mips/locore_mips3.S cvs rdiff -u -r1.26.36.1.2.25 -r1.26.36.1.2.26 \ src/sys/arch/mips/mips/mipsX_subr.S cvs rdiff -u -r1.205.4.1.2.1.2.35 -r1.205.4.1.2.1.2.36 \ src/sys/arch/mips/mips/mips_machdep.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [matt-nb5-mips64] src/sys/arch/mips
Module Name:src Committed By: matt Date: Thu Feb 25 05:53:23 UTC 2010 Modified Files: src/sys/arch/mips/include [matt-nb5-mips64]: pmap.h src/sys/arch/mips/mips [matt-nb5-mips64]: pmap.c pmap_tlb.c Log Message: Make the UP and MP ASID allocation algorithm common. Significantly improve the algorithm. Now when we exhaust the ASIDs, interrogate the TLB for active ASIDS and release all the other for future allocations. This leaves the TLB entries with ASIDs valid avoiding the need to re-incur TLB misses for them. To generate a diff of this commit: cvs rdiff -u -r1.54.26.9 -r1.54.26.10 src/sys/arch/mips/include/pmap.h cvs rdiff -u -r1.179.16.17 -r1.179.16.18 src/sys/arch/mips/mips/pmap.c cvs rdiff -u -r1.1.2.3 -r1.1.2.4 src/sys/arch/mips/mips/pmap_tlb.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
Re: CVS commit: [matt-nb5-mips64] src/sys/arch/mips
On Thu, Feb 25, 2010 at 05:53:23AM +, Matt Thomas wrote: Log Message: Make the UP and MP ASID allocation algorithm common. Significantly improve the algorithm. Now when we exhaust the ASIDs, interrogate the TLB for active ASIDS and release all the other for future allocations. This leaves the TLB entries with ASIDs valid avoiding the need to re-incur TLB misses for them. I presume it is willing to kill some TLB entries if the above doesn't find any (or enough) free ASIDs ? Or is the ASID number space guaranteed to be significantly higher that the number of TLBs ?? David -- David Laight: da...@l8s.co.uk
Re: CVS commit: [matt-nb5-mips64] src/sys/arch/mips
On Feb 24, 2010, at 10:31 PM, David Laight wrote: On Thu, Feb 25, 2010 at 05:53:23AM +, Matt Thomas wrote: Log Message: Make the UP and MP ASID allocation algorithm common. Significantly improve the algorithm. Now when we exhaust the ASIDs, interrogate the TLB for active ASIDS and release all the other for future allocations. This leaves the TLB entries with ASIDs valid avoiding the need to re-incur TLB misses for them. I presume it is willing to kill some TLB entries if the above doesn't find any (or enough) free ASIDs ? Or is the ASID number space guaranteed to be significantly higher that the number of TLBs ?? If it can't reclaim at least half of the ASID space, it invalidates all ASID based entries in the TLB. And for MIPS32/MIPS64 the ASID space is at least 4x the number of TLB entries.
CVS commit: [matt-nb5-mips64] src/sys/arch/mips/mips
Module Name:src Committed By: matt Date: Tue Feb 23 20:32:33 UTC 2010 Modified Files: src/sys/arch/mips/mips [matt-nb5-mips64]: spl.S Log Message: Instead of a read-only ipl_sr_bits, define a ipl_sr_map struct and fill that in the interrupt init routine. There's a default ipl_sr_map will operate correctly, but isn't performant. To generate a diff of this commit: cvs rdiff -u -r1.1.2.2 -r1.1.2.3 src/sys/arch/mips/mips/spl.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [matt-nb5-mips64] src/sys/arch/mips
Module Name:src Committed By: matt Date: Tue Feb 23 20:33:48 UTC 2010 Modified Files: src/sys/arch/mips/include [matt-nb5-mips64]: cpu.h locore.h pmap.h pte.h types.h vmparam.h src/sys/arch/mips/mips [matt-nb5-mips64]: genassym.cf locore.S locore_mips1.S mipsX_subr.S mips_fputrap.c mips_machdep.c pmap.c pmap_segtab.c pmap_tlb.c trap.c src/sys/arch/mips/rmi [matt-nb5-mips64]: rmixl_cpu.c rmixl_cpucore.c rmixl_cpucorevar.h rmixlvar.h src/sys/arch/mips/sibyte/pci [matt-nb5-mips64]: sbbrz.c Log Message: Make sure mips/locore.h is not included by MI code. Add send_ipi and cpu_offline_md hooks to locoresw. Add MP support to pmap (pvlist locking, tlb locking). Add TLB shootdown support (see comment at the top of mips/pmap_tlb.c). Add mipsXX_tlb_invalidate_globals routine To generate a diff of this commit: cvs rdiff -u -r1.90.16.20 -r1.90.16.21 src/sys/arch/mips/include/cpu.h cvs rdiff -u -r1.78.36.1.2.13 -r1.78.36.1.2.14 \ src/sys/arch/mips/include/locore.h cvs rdiff -u -r1.54.26.8 -r1.54.26.9 src/sys/arch/mips/include/pmap.h cvs rdiff -u -r1.19.18.2 -r1.19.18.3 src/sys/arch/mips/include/pte.h cvs rdiff -u -r1.43.36.13 -r1.43.36.14 src/sys/arch/mips/include/types.h cvs rdiff -u -r1.41.28.11 -r1.41.28.12 src/sys/arch/mips/include/vmparam.h cvs rdiff -u -r1.44.12.17 -r1.44.12.18 src/sys/arch/mips/mips/genassym.cf cvs rdiff -u -r1.167.38.14 -r1.167.38.15 src/sys/arch/mips/mips/locore.S cvs rdiff -u -r1.64.26.1.2.8 -r1.64.26.1.2.9 \ src/sys/arch/mips/mips/locore_mips1.S cvs rdiff -u -r1.26.36.1.2.24 -r1.26.36.1.2.25 \ src/sys/arch/mips/mips/mipsX_subr.S cvs rdiff -u -r1.5.66.4 -r1.5.66.5 src/sys/arch/mips/mips/mips_fputrap.c cvs rdiff -u -r1.205.4.1.2.1.2.34 -r1.205.4.1.2.1.2.35 \ src/sys/arch/mips/mips/mips_machdep.c cvs rdiff -u -r1.179.16.15 -r1.179.16.16 src/sys/arch/mips/mips/pmap.c cvs rdiff -u -r1.1.2.4 -r1.1.2.5 src/sys/arch/mips/mips/pmap_segtab.c cvs rdiff -u -r1.1.2.1 -r1.1.2.2 src/sys/arch/mips/mips/pmap_tlb.c cvs rdiff -u -r1.217.12.19 -r1.217.12.20 src/sys/arch/mips/mips/trap.c cvs rdiff -u -r1.1.2.4 -r1.1.2.5 src/sys/arch/mips/rmi/rmixl_cpu.c cvs rdiff -u -r1.1.2.3 -r1.1.2.4 src/sys/arch/mips/rmi/rmixl_cpucore.c cvs rdiff -u -r1.1.2.1 -r1.1.2.2 src/sys/arch/mips/rmi/rmixl_cpucorevar.h cvs rdiff -u -r1.1.2.13 -r1.1.2.14 src/sys/arch/mips/rmi/rmixlvar.h cvs rdiff -u -r1.1.2.4 -r1.1.2.5 src/sys/arch/mips/sibyte/pci/sbbrz.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [matt-nb5-mips64] src/sys/arch
Module Name:src Committed By: matt Date: Tue Feb 23 20:24:37 UTC 2010 Modified Files: src/sys/arch/evbmips/malta [matt-nb5-mips64]: malta_intr.c src/sys/arch/mips/include [matt-nb5-mips64]: intr.h src/sys/arch/mips/rmi [matt-nb5-mips64]: rmixl_intr.c src/sys/arch/sbmips/include [matt-nb5-mips64]: intr.h systemsw.h src/sys/arch/sbmips/sbmips [matt-nb5-mips64]: autoconf.c sb1250_icu.c systemsw.c Log Message: Instead of a read-only ipl_sr_bits, define a ipl_sr_map struct and fill that in the interrupt init routine. There's a default ipl_sr_map will operate correctly, but isn't performant. To generate a diff of this commit: cvs rdiff -u -r1.19.16.4 -r1.19.16.5 src/sys/arch/evbmips/malta/malta_intr.c cvs rdiff -u -r1.3.96.4 -r1.3.96.5 src/sys/arch/mips/include/intr.h cvs rdiff -u -r1.1.2.12 -r1.1.2.13 src/sys/arch/mips/rmi/rmixl_intr.c cvs rdiff -u -r1.9 -r1.9.36.1 src/sys/arch/sbmips/include/intr.h cvs rdiff -u -r1.7.28.2 -r1.7.28.3 src/sys/arch/sbmips/include/systemsw.h cvs rdiff -u -r1.6 -r1.6.96.1 src/sys/arch/sbmips/sbmips/autoconf.c cvs rdiff -u -r1.9.36.3 -r1.9.36.4 src/sys/arch/sbmips/sbmips/sb1250_icu.c cvs rdiff -u -r1.14.28.3 -r1.14.28.4 src/sys/arch/sbmips/sbmips/systemsw.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [matt-nb5-mips64] src/sys/arch/mips
Module Name:src Committed By: matt Date: Tue Feb 23 20:25:57 UTC 2010 Modified Files: src/sys/arch/mips/adm5120 [matt-nb5-mips64]: adm5120_intr.c src/sys/arch/mips/alchemy [matt-nb5-mips64]: au_icu.c src/sys/arch/mips/atheros [matt-nb5-mips64]: ar5312_intr.c ar5315_intr.c Log Message: Instead of a read-only ipl_sr_bits, define a ipl_sr_map struct and fill that in the interrupt init routine. There's a default ipl_sr_map will operate correctly, but isn't performant. To generate a diff of this commit: cvs rdiff -u -r1.3.18.2 -r1.3.18.3 src/sys/arch/mips/adm5120/adm5120_intr.c cvs rdiff -u -r1.23.18.1 -r1.23.18.2 src/sys/arch/mips/alchemy/au_icu.c cvs rdiff -u -r1.6.28.2 -r1.6.28.3 src/sys/arch/mips/atheros/ar5312_intr.c cvs rdiff -u -r1.5.28.2 -r1.5.28.3 src/sys/arch/mips/atheros/ar5315_intr.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [matt-nb5-mips64] src/sys/arch/mips/mips
Module Name:src Committed By: matt Date: Wed Feb 24 00:09:04 UTC 2010 Modified Files: src/sys/arch/mips/mips [matt-nb5-mips64]: pmap.c Log Message: Fix bug because of typo: if (foo); something is not the same as if (foo) something. Add some more KASSERTs (used to find the bug). To generate a diff of this commit: cvs rdiff -u -r1.179.16.16 -r1.179.16.17 src/sys/arch/mips/mips/pmap.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [matt-nb5-mips64] src/sys/arch/mips/mips
Module Name:src Committed By: matt Date: Wed Feb 24 00:30:21 UTC 2010 Modified Files: src/sys/arch/mips/mips [matt-nb5-mips64]: pmap_tlb.c Log Message: When adding a CPU to a TLB, mark the kernel pmap as active and onproc for that CPU. To generate a diff of this commit: cvs rdiff -u -r1.1.2.2 -r1.1.2.3 src/sys/arch/mips/mips/pmap_tlb.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [matt-nb5-mips64] src/sys/arch/mips/mips
Module Name:src Committed By: matt Date: Mon Feb 22 20:13:22 UTC 2010 Modified Files: src/sys/arch/mips/mips [matt-nb5-mips64]: locore_mips3.S Log Message: Add a weak alias of cpu_counter32 to mips3_cp0_count_read. This allows mips/cpu_counter.h to avoid including mips/locore.h. To generate a diff of this commit: cvs rdiff -u -r1.93.38.5 -r1.93.38.6 src/sys/arch/mips/mips/locore_mips3.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [matt-nb5-mips64] src/sys/arch/mips/include
Module Name:src
Committed By: matt
Date: Mon Feb 22 20:14:07 UTC 2010
Modified Files:
src/sys/arch/mips/include [matt-nb5-mips64]: cpu_counter.h
Log Message:
Don't include mips/locore.h. Rely on the weak alias in locore_mips3.S
To generate a diff of this commit:
cvs rdiff -u -r1.3.90.1 -r1.3.90.2 src/sys/arch/mips/include/cpu_counter.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/include/cpu_counter.h
diff -u src/sys/arch/mips/include/cpu_counter.h:1.3.90.1 src/sys/arch/mips/include/cpu_counter.h:1.3.90.2
--- src/sys/arch/mips/include/cpu_counter.h:1.3.90.1 Wed Jan 20 06:58:35 2010
+++ src/sys/arch/mips/include/cpu_counter.h Mon Feb 22 20:14:07 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu_counter.h,v 1.3.90.1 2010/01/20 06:58:35 matt Exp $ */
+/* $NetBSD: cpu_counter.h,v 1.3.90.2 2010/02/22 20:14:07 matt Exp $ */
/*
* Copyright (c) 2000 Soren S. Jorvang. All rights reserved.
@@ -33,7 +33,6 @@
*/
#include machine/cpu.h
-#include mips/locore.h
#ifdef _KERNEL
@@ -51,12 +50,7 @@
#define cpu_counter() cpu_counter32()
-static __inline uint32_t
-cpu_counter32(void)
-{
-
- return mips3_cp0_count_read();
-}
+uint32_t cpu_counter32(void); /* weak alias of mips3_cp0_count_read */
static __inline uint64_t
cpu_frequency(struct cpu_info *ci)
CVS commit: [matt-nb5-mips64] src/sys/arch/mips/mips
Module Name:src Committed By: matt Date: Mon Feb 22 20:17:09 UTC 2010 Modified Files: src/sys/arch/mips/mips [matt-nb5-mips64]: compat_16_machdep.c mips_softint.c process_machdep.c sig_machdep.c syscall.c Log Message: Explicitly include mips/locore.h since mips/cpu.h no longer includes it. Use curcpu()-ci_data.cpu_nsyscall instead of uvmexp.syscalls. To generate a diff of this commit: cvs rdiff -u -r1.12.14.4 -r1.12.14.5 \ src/sys/arch/mips/mips/compat_16_machdep.c cvs rdiff -u -r1.1.2.5 -r1.1.2.6 src/sys/arch/mips/mips/mips_softint.c cvs rdiff -u -r1.29.62.3 -r1.29.62.4 src/sys/arch/mips/mips/process_machdep.c cvs rdiff -u -r1.16.14.3 -r1.16.14.4 src/sys/arch/mips/mips/sig_machdep.c cvs rdiff -u -r1.37.12.11 -r1.37.12.12 src/sys/arch/mips/mips/syscall.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/mips/mips/compat_16_machdep.c diff -u src/sys/arch/mips/mips/compat_16_machdep.c:1.12.14.4 src/sys/arch/mips/mips/compat_16_machdep.c:1.12.14.5 --- src/sys/arch/mips/mips/compat_16_machdep.c:1.12.14.4 Mon Feb 1 04:16:19 2010 +++ src/sys/arch/mips/mips/compat_16_machdep.c Mon Feb 22 20:17:09 2010 @@ -1,4 +1,4 @@ -/* $NetBSD: compat_16_machdep.c,v 1.12.14.4 2010/02/01 04:16:19 matt Exp $ */ +/* $NetBSD: compat_16_machdep.c,v 1.12.14.5 2010/02/22 20:17:09 matt Exp $ */ /*- * Copyright (c) 1998, 2001 The NetBSD Foundation, Inc. @@ -45,7 +45,7 @@ #include sys/cdefs.h /* RCS ID Copyright macro defns */ -__KERNEL_RCSID(0, $NetBSD: compat_16_machdep.c,v 1.12.14.4 2010/02/01 04:16:19 matt Exp $); +__KERNEL_RCSID(0, $NetBSD: compat_16_machdep.c,v 1.12.14.5 2010/02/22 20:17:09 matt Exp $); #include opt_cputype.h #include opt_compat_netbsd.h @@ -68,6 +68,7 @@ #include mips/regnum.h #include mips/frame.h +#include mips/locore.h #if !defined(__mips_o32) #define fpreg fpreg_oabi Index: src/sys/arch/mips/mips/mips_softint.c diff -u src/sys/arch/mips/mips/mips_softint.c:1.1.2.5 src/sys/arch/mips/mips/mips_softint.c:1.1.2.6 --- src/sys/arch/mips/mips/mips_softint.c:1.1.2.5 Tue Feb 16 08:13:57 2010 +++ src/sys/arch/mips/mips/mips_softint.c Mon Feb 22 20:17:09 2010 @@ -29,7 +29,7 @@ #include sys/cdefs.h /* RCS ID Copyright macro defns */ -__KERNEL_RCSID(0, $NetBSD: mips_softint.c,v 1.1.2.5 2010/02/16 08:13:57 matt Exp $); +__KERNEL_RCSID(0, $NetBSD: mips_softint.c,v 1.1.2.6 2010/02/22 20:17:09 matt Exp $); #include sys/param.h #include sys/proc.h @@ -41,6 +41,7 @@ #include uvm/uvm_extern.h #include machine/intr.h +#include mips/locore.h #ifdef __HAVE_FAST_SOFTINTS Index: src/sys/arch/mips/mips/process_machdep.c diff -u src/sys/arch/mips/mips/process_machdep.c:1.29.62.3 src/sys/arch/mips/mips/process_machdep.c:1.29.62.4 --- src/sys/arch/mips/mips/process_machdep.c:1.29.62.3 Mon Feb 1 04:16:19 2010 +++ src/sys/arch/mips/mips/process_machdep.c Mon Feb 22 20:17:09 2010 @@ -1,4 +1,4 @@ -/* $NetBSD: process_machdep.c,v 1.29.62.3 2010/02/01 04:16:19 matt Exp $ */ +/* $NetBSD: process_machdep.c,v 1.29.62.4 2010/02/22 20:17:09 matt Exp $ */ /* * Copyright (c) 1993 The Regents of the University of California. @@ -76,7 +76,7 @@ */ #include sys/cdefs.h /* RCS ID Copyright macro defns */ -__KERNEL_RCSID(0, $NetBSD: process_machdep.c,v 1.29.62.3 2010/02/01 04:16:19 matt Exp $); +__KERNEL_RCSID(0, $NetBSD: process_machdep.c,v 1.29.62.4 2010/02/22 20:17:09 matt Exp $); /* * This file may seem a bit stylized, but that so that it's easier to port. @@ -105,8 +105,10 @@ #include sys/proc.h #include sys/user.h #include sys/ptrace.h + #include mips/reg.h #include mips/regnum.h /* symbolic register indices */ +#include mips/locore.h int process_read_regs(struct lwp *l, struct reg *regs) Index: src/sys/arch/mips/mips/sig_machdep.c diff -u src/sys/arch/mips/mips/sig_machdep.c:1.16.14.3 src/sys/arch/mips/mips/sig_machdep.c:1.16.14.4 --- src/sys/arch/mips/mips/sig_machdep.c:1.16.14.3 Mon Feb 1 04:16:20 2010 +++ src/sys/arch/mips/mips/sig_machdep.c Mon Feb 22 20:17:09 2010 @@ -1,4 +1,4 @@ -/* $NetBSD: sig_machdep.c,v 1.16.14.3 2010/02/01 04:16:20 matt Exp $ */ +/* $NetBSD: sig_machdep.c,v 1.16.14.4 2010/02/22 20:17:09 matt Exp $ */ /*- * Copyright (c) 2003 The NetBSD Foundation, Inc. @@ -31,7 +31,7 @@ #include sys/cdefs.h /* RCS ID Copyright macro defns */ -__KERNEL_RCSID(0, $NetBSD: sig_machdep.c,v 1.16.14.3 2010/02/01 04:16:20 matt Exp $); +__KERNEL_RCSID(0, $NetBSD: sig_machdep.c,v 1.16.14.4 2010/02/22 20:17:09 matt Exp $); #include opt_cputype.h #include opt_compat_netbsd.h @@ -50,6 +50,7 @@ #include mips/frame.h #include mips/regnum.h +#include mips/locore.h void * getframe(struct lwp *l, int sig, int *onstack) Index: src/sys/arch/mips/mips/syscall.c diff -u src/sys/arch/mips/mips/syscall.c:1.37.12.11 src/sys/arch/mips/mips/syscall.c:1.37.12.12 --- src/sys/arch/mips/mips/syscall.c:1.37.12.11
CVS commit: [matt-nb5-mips64] src/sys/arch/mips/mips
Module Name:src Committed By: matt Date: Tue Feb 16 08:03:15 UTC 2010 Modified Files: src/sys/arch/mips/mips [matt-nb5-mips64]: locore.S Log Message: Fix typo. To generate a diff of this commit: cvs rdiff -u -r1.167.38.13 -r1.167.38.14 src/sys/arch/mips/mips/locore.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [matt-nb5-mips64] src/sys/arch
Module Name:src Committed By: matt Date: Tue Feb 16 08:13:58 UTC 2010 Modified Files: src/sys/arch/evbmips/malta [matt-nb5-mips64]: malta_intr.c src/sys/arch/mips/adm5120 [matt-nb5-mips64]: adm5120_intr.c src/sys/arch/mips/atheros [matt-nb5-mips64]: ar5312_intr.c ar5315_intr.c src/sys/arch/mips/include [matt-nb5-mips64]: cpu.h intr.h src/sys/arch/mips/mips [matt-nb5-mips64]: genassym.cf mipsX_subr.S mips_machdep.c mips_softint.c src/sys/arch/mips/rmi [matt-nb5-mips64]: rmixl_intr.c Log Message: Add __HAVE_PREEMPTION support for NetBSD/mips. Kill IPL_PREEMPT since it isn't needed. To generate a diff of this commit: cvs rdiff -u -r1.19.16.3 -r1.19.16.4 src/sys/arch/evbmips/malta/malta_intr.c cvs rdiff -u -r1.3.18.1 -r1.3.18.2 src/sys/arch/mips/adm5120/adm5120_intr.c cvs rdiff -u -r1.6.28.1 -r1.6.28.2 src/sys/arch/mips/atheros/ar5312_intr.c cvs rdiff -u -r1.5.28.1 -r1.5.28.2 src/sys/arch/mips/atheros/ar5315_intr.c cvs rdiff -u -r1.90.16.19 -r1.90.16.20 src/sys/arch/mips/include/cpu.h cvs rdiff -u -r1.3.96.2 -r1.3.96.3 src/sys/arch/mips/include/intr.h cvs rdiff -u -r1.44.12.16 -r1.44.12.17 src/sys/arch/mips/mips/genassym.cf cvs rdiff -u -r1.26.36.1.2.23 -r1.26.36.1.2.24 \ src/sys/arch/mips/mips/mipsX_subr.S cvs rdiff -u -r1.205.4.1.2.1.2.33 -r1.205.4.1.2.1.2.34 \ src/sys/arch/mips/mips/mips_machdep.c cvs rdiff -u -r1.1.2.4 -r1.1.2.5 src/sys/arch/mips/mips/mips_softint.c cvs rdiff -u -r1.1.2.11 -r1.1.2.12 src/sys/arch/mips/rmi/rmixl_intr.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [matt-nb5-mips64] src/sys/arch/mips/conf
Module Name:src Committed By: matt Date: Sun Feb 14 21:50:38 UTC 2010 Modified Files: src/sys/arch/mips/conf [matt-nb5-mips64]: Makefile.mips Log Message: We use ntrad* and so make objcopy use them too. To generate a diff of this commit: cvs rdiff -u -r1.50.24.5 -r1.50.24.6 src/sys/arch/mips/conf/Makefile.mips Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [matt-nb5-mips64] src/sys/arch/mips/include
Module Name:src Committed By: matt Date: Mon Feb 15 03:11:58 UTC 2010 Modified Files: src/sys/arch/mips/include [matt-nb5-mips64]: lock.h Log Message: In SIMPLELOCK_LOCKED_P check against != UNLOCKED instead of == LOCKED. This is so the compiler can emit a bnez instead of loading 1 into a register and then doing beq. To generate a diff of this commit: cvs rdiff -u -r1.16 -r1.16.16.1 src/sys/arch/mips/include/lock.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [matt-nb5-mips64] src/sys/arch/mips/include
Module Name:src Committed By: matt Date: Mon Feb 15 03:12:17 UTC 2010 Modified Files: src/sys/arch/mips/include [matt-nb5-mips64]: asm.h Log Message: Fix a comment. To generate a diff of this commit: cvs rdiff -u -r1.40.38.11 -r1.40.38.12 src/sys/arch/mips/include/asm.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [matt-nb5-mips64] src/sys/arch/mips
Module Name:src
Committed By: matt
Date: Mon Feb 15 07:36:04 UTC 2010
Modified Files:
src/sys/arch/mips/include [matt-nb5-mips64]: cpu.h locore.h profile.h
src/sys/arch/mips/mips [matt-nb5-mips64]: genassym.cf lock_stubs.S
locore.S locore_mips1.S locore_mips3.S mips3_clockintr.c
mipsX_subr.S mips_machdep.c mips_softint.c spl.S trap.c
vm_machdep.c
Added Files:
src/sys/arch/mips/include [matt-nb5-mips64]: intr.h
Log Message:
Completely redo how interrupts and SPL are handled in NetBSD/mips.
[XXX locore_mips1.S still needs to adapted.]
Nested interrupts now work. Except for MIPS_SOFT_MASK and MIPS_SR_INT_IE,
how interrupts work is completely abstracted. spl is handled through the
mips_splsw table. Direct manipulation of the status register is no longer
done (except for MIPS_SR_INT_IE). A new mips/intr.h contains the common
IPL/IST/spl* definitions for all ports.
Interrupt delivery is completely different. Clock interrupts may interrupt
device interrupts. ci_idepth is now handled by the caller of cpu_intr as
are softints (both can be optimized/simplified in the case of interrupts of
usermode code). cpu_intr has new arguments and now get called at IPL_HIGH
with MIPS_SR_INT_IE set and its logic is:
void
cpu_intr(int ppl, vaddr_t pc, uint32_t status)
{
int ipl;
uint32_t pending;
while (ppl (ipl = splintr(pending))) {
splx(ipl); /* enable interrupts */
handle pending interrupts
(void)splhigh();/* disable interrupts */
}
}
mipsX_subr.S has been reworked. All user handlers (user_intr, systemcall,
user_gen_exception) now use common return to usermode code in lwp_trampoline.
ast() has changed to void ast(void) since the previous pc argument was never
used.
The playstation IPL_ICU_MASK support has been nuked.
MIPS_DYNAMIC_STATUS_MASK may soon be nuked soon.
A bunch of debugging code was left conditionalized by PARANOIA. If this
code detects a bug, it will enter an infinite loop. It is expected that
the kernel will be debugged in a simulator or with a hardware debugger so
that the state at that point can be analyzed.
To generate a diff of this commit:
cvs rdiff -u -r1.90.16.18 -r1.90.16.19 src/sys/arch/mips/include/cpu.h
cvs rdiff -u -r0 -r1.3.96.2 src/sys/arch/mips/include/intr.h
cvs rdiff -u -r1.78.36.1.2.12 -r1.78.36.1.2.13 \
src/sys/arch/mips/include/locore.h
cvs rdiff -u -r1.20 -r1.20.96.1 src/sys/arch/mips/include/profile.h
cvs rdiff -u -r1.44.12.15 -r1.44.12.16 src/sys/arch/mips/mips/genassym.cf
cvs rdiff -u -r1.9.18.6 -r1.9.18.7 src/sys/arch/mips/mips/lock_stubs.S
cvs rdiff -u -r1.167.38.12 -r1.167.38.13 src/sys/arch/mips/mips/locore.S
cvs rdiff -u -r1.64.26.1.2.7 -r1.64.26.1.2.8 \
src/sys/arch/mips/mips/locore_mips1.S
cvs rdiff -u -r1.93.38.4 -r1.93.38.5 src/sys/arch/mips/mips/locore_mips3.S
cvs rdiff -u -r1.8 -r1.8.12.1 src/sys/arch/mips/mips/mips3_clockintr.c
cvs rdiff -u -r1.26.36.1.2.22 -r1.26.36.1.2.23 \
src/sys/arch/mips/mips/mipsX_subr.S
cvs rdiff -u -r1.205.4.1.2.1.2.32 -r1.205.4.1.2.1.2.33 \
src/sys/arch/mips/mips/mips_machdep.c
cvs rdiff -u -r1.1.2.3 -r1.1.2.4 src/sys/arch/mips/mips/mips_softint.c
cvs rdiff -u -r1.1.2.1 -r1.1.2.2 src/sys/arch/mips/mips/spl.S
cvs rdiff -u -r1.217.12.18 -r1.217.12.19 src/sys/arch/mips/mips/trap.c
cvs rdiff -u -r1.121.6.1.2.11 -r1.121.6.1.2.12 \
src/sys/arch/mips/mips/vm_machdep.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
CVS commit: [matt-nb5-mips64] src/sys/arch
Module Name:src Committed By: matt Date: Mon Feb 15 07:37:37 UTC 2010 Modified Files: src/sys/arch/evbmips/alchemy [matt-nb5-mips64]: mach_intr.c src/sys/arch/evbmips/atheros [matt-nb5-mips64]: mach_intr.c src/sys/arch/evbmips/evbmips [matt-nb5-mips64]: interrupt.c src/sys/arch/evbmips/include [matt-nb5-mips64]: intr.h src/sys/arch/evbmips/malta [matt-nb5-mips64]: malta_intr.c src/sys/arch/mips/adm5120 [matt-nb5-mips64]: adm5120_intr.c src/sys/arch/mips/alchemy [matt-nb5-mips64]: au_icu.c src/sys/arch/mips/alchemy/include [matt-nb5-mips64]: auvar.h src/sys/arch/mips/atheros [matt-nb5-mips64]: ar5312_intr.c ar5315_intr.c src/sys/arch/mips/atheros/include [matt-nb5-mips64]: ar531xvar.h src/sys/arch/mips/rmi [matt-nb5-mips64]: rmixl_intr.c Log Message: Adapt to the new interrupt framework for NetBSD/mips. To generate a diff of this commit: cvs rdiff -u -r1.3 -r1.3.18.1 src/sys/arch/evbmips/alchemy/mach_intr.c cvs rdiff -u -r1.2 -r1.2.18.1 src/sys/arch/evbmips/atheros/mach_intr.c cvs rdiff -u -r1.11.18.2 -r1.11.18.3 src/sys/arch/evbmips/evbmips/interrupt.c cvs rdiff -u -r1.16.18.2 -r1.16.18.3 src/sys/arch/evbmips/include/intr.h cvs rdiff -u -r1.19.16.2 -r1.19.16.3 src/sys/arch/evbmips/malta/malta_intr.c cvs rdiff -u -r1.3 -r1.3.18.1 src/sys/arch/mips/adm5120/adm5120_intr.c cvs rdiff -u -r1.23 -r1.23.18.1 src/sys/arch/mips/alchemy/au_icu.c cvs rdiff -u -r1.9 -r1.9.64.1 src/sys/arch/mips/alchemy/include/auvar.h cvs rdiff -u -r1.6 -r1.6.28.1 src/sys/arch/mips/atheros/ar5312_intr.c cvs rdiff -u -r1.5 -r1.5.28.1 src/sys/arch/mips/atheros/ar5315_intr.c cvs rdiff -u -r1.5 -r1.5.74.1 src/sys/arch/mips/atheros/include/ar531xvar.h cvs rdiff -u -r1.1.2.10 -r1.1.2.11 src/sys/arch/mips/rmi/rmixl_intr.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [matt-nb5-mips64] src/sys/arch/mips/rmi
Module Name:src Committed By: cliff Date: Wed Feb 10 19:45:48 UTC 2010 Modified Files: src/sys/arch/mips/rmi [matt-nb5-mips64]: rmixl_subr.S Log Message: save gp and t8 before callback to firmware To generate a diff of this commit: cvs rdiff -u -r1.1.2.3 -r1.1.2.4 src/sys/arch/mips/rmi/rmixl_subr.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [matt-nb5-mips64] src/sys/arch/mips/mips
Module Name:src Committed By: matt Date: Sat Feb 6 14:41:40 UTC 2010 Modified Files: src/sys/arch/mips/mips [matt-nb5-mips64]: mips_softint.c Log Message: Add some more KASSERTs To generate a diff of this commit: cvs rdiff -u -r1.1.2.2 -r1.1.2.3 src/sys/arch/mips/mips/mips_softint.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [matt-nb5-mips64] src/sys/arch/mips/mips
Module Name:src Committed By: matt Date: Sat Feb 6 14:43:15 UTC 2010 Modified Files: src/sys/arch/mips/mips [matt-nb5-mips64]: locore.S Added Files: src/sys/arch/mips/mips [matt-nb5-mips64]: spl.S Log Message: Split spl functions into their own sources. Make sure fast softints clear l_ctxswtch in the softint thread, not their own. To generate a diff of this commit: cvs rdiff -u -r1.167.38.11 -r1.167.38.12 src/sys/arch/mips/mips/locore.S cvs rdiff -u -r0 -r1.1.2.1 src/sys/arch/mips/mips/spl.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [matt-nb5-mips64] src/sys/arch/mips/conf
Module Name:src Committed By: cliff Date: Sat Feb 6 18:18:01 UTC 2010 Modified Files: src/sys/arch/mips/conf [matt-nb5-mips64]: files.mips Log Message: add entry for mips/spl.S so kernel can compile To generate a diff of this commit: cvs rdiff -u -r1.58.24.7 -r1.58.24.8 src/sys/arch/mips/conf/files.mips Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
Re: CVS commit: [matt-nb5-mips64] src/sys/arch/mips
Matt Thomas wrote: Module Name: src Committed By: matt Date: Fri Feb 5 07:36:51 UTC 2010 [ ... ] Add __HAVE_FAST_SOFTINTS support. Add routine to remap an uarea via a direct-mapped address. This avoids TLB machinations when swtching to/from the softint thread. This can only be done for lwp which won't exit. Is this printf in cpu_uarea_remap() meant to be there? + printf(ctx=%#PRIxVADDR utf=%p\n, + (vaddr_t)l-l_addr-u_pcb.pcb_context.val[_L_SP], + l-l_md.md_utf Cheers, Simon.
CVS commit: [matt-nb5-mips64] src/sys/arch/mips/mips
Module Name:src Committed By: matt Date: Fri Feb 5 17:16:05 UTC 2010 Modified Files: src/sys/arch/mips/mips [matt-nb5-mips64]: vm_machdep.c Log Message: remove a debugging printf. cleanup the reinit of the lwp. To generate a diff of this commit: cvs rdiff -u -r1.121.6.1.2.10 -r1.121.6.1.2.11 \ src/sys/arch/mips/mips/vm_machdep.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [matt-nb5-mips64] src/sys/arch/mips/mips
Module Name:src Committed By: matt Date: Sat Feb 6 00:39:47 UTC 2010 Modified Files: src/sys/arch/mips/mips [matt-nb5-mips64]: genassym.cf locore.S mips_softint.c Log Message: Allow __HAVE_FAST_SOFTINTS to be optional To generate a diff of this commit: cvs rdiff -u -r1.44.12.14 -r1.44.12.15 src/sys/arch/mips/mips/genassym.cf cvs rdiff -u -r1.167.38.9 -r1.167.38.10 src/sys/arch/mips/mips/locore.S cvs rdiff -u -r1.1.2.1 -r1.1.2.2 src/sys/arch/mips/mips/mips_softint.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [matt-nb5-mips64] src/sys/arch/mips/mips
Module Name:src Committed By: matt Date: Sat Feb 6 02:56:23 UTC 2010 Modified Files: src/sys/arch/mips/mips [matt-nb5-mips64]: locore.S Log Message: Save curlwp in context (even though it should already be there). To generate a diff of this commit: cvs rdiff -u -r1.167.38.10 -r1.167.38.11 src/sys/arch/mips/mips/locore.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [matt-nb5-mips64] src/sys/arch
Module Name:src Committed By: matt Date: Sat Feb 6 02:57:44 UTC 2010 Modified Files: src/sys/arch/algor/include [matt-nb5-mips64]: intr.h src/sys/arch/arc/include [matt-nb5-mips64]: intr.h src/sys/arch/cobalt/include [matt-nb5-mips64]: intr.h src/sys/arch/evbmips/include [matt-nb5-mips64]: intr.h src/sys/arch/pmax/include [matt-nb5-mips64]: intr.h src/sys/arch/sgimips/include [matt-nb5-mips64]: intr.h Removed Files: src/sys/arch/mips/include [matt-nb5-mips64]: softintr.h Log Message: mips/softintr.h is no longer needed. To generate a diff of this commit: cvs rdiff -u -r1.13 -r1.13.18.1 src/sys/arch/algor/include/intr.h cvs rdiff -u -r1.22 -r1.22.18.1 src/sys/arch/arc/include/intr.h cvs rdiff -u -r1.32 -r1.32.12.1 src/sys/arch/cobalt/include/intr.h cvs rdiff -u -r1.16.18.1 -r1.16.18.2 src/sys/arch/evbmips/include/intr.h cvs rdiff -u -r1.4 -r0 src/sys/arch/mips/include/softintr.h cvs rdiff -u -r1.32 -r1.32.28.1 src/sys/arch/pmax/include/intr.h cvs rdiff -u -r1.25 -r1.25.36.1 src/sys/arch/sgimips/include/intr.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [matt-nb5-mips64] src/sys/arch
Module Name:src Committed By: matt Date: Sat Feb 6 02:59:04 UTC 2010 Modified Files: src/sys/arch/evbmips/malta [matt-nb5-mips64]: malta_intr.c src/sys/arch/mips/rmi [matt-nb5-mips64]: rmixl_intr.c Log Message: A little constification and remove some old softintr cruft. To generate a diff of this commit: cvs rdiff -u -r1.19.16.1 -r1.19.16.2 src/sys/arch/evbmips/malta/malta_intr.c cvs rdiff -u -r1.1.2.8 -r1.1.2.9 src/sys/arch/mips/rmi/rmixl_intr.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [matt-nb5-mips64] src/sys/arch/mips/rmi
Module Name:src Committed By: cliff Date: Sat Feb 6 03:10:14 UTC 2010 Modified Files: src/sys/arch/mips/rmi [matt-nb5-mips64]: rmixl_intr.c Log Message: - when establishing an intr, if malloc fails, be sure to splx on the way out - in interrupt dispatch, when ack-ing EIRR, preserve the softint bits To generate a diff of this commit: cvs rdiff -u -r1.1.2.9 -r1.1.2.10 src/sys/arch/mips/rmi/rmixl_intr.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [matt-nb5-mips64] src/sys/arch/mips/mips
Module Name:src Committed By: matt Date: Sat Feb 6 04:55:01 UTC 2010 Modified Files: src/sys/arch/mips/mips [matt-nb5-mips64]: mips_machdep.c Log Message: When choosing a msgbuf for a LP32 kernel, make sure it's mappable via KSEG0 To generate a diff of this commit: cvs rdiff -u -r1.205.4.1.2.1.2.31 -r1.205.4.1.2.1.2.32 \ src/sys/arch/mips/mips/mips_machdep.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [matt-nb5-mips64] src/sys/arch/mips/mips
Module Name:src Committed By: matt Date: Sat Feb 6 06:02:29 UTC 2010 Modified Files: src/sys/arch/mips/mips [matt-nb5-mips64]: pmap.c Log Message: Add some prelim poolpage debugging code. Don't use ptoa to expand pfns to paddrs since it's cast with a vaddr_t. To generate a diff of this commit: cvs rdiff -u -r1.179.16.14 -r1.179.16.15 src/sys/arch/mips/mips/pmap.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [matt-nb5-mips64] src/sys/arch/mips
Module Name:src Committed By: matt Date: Fri Feb 5 07:36:51 UTC 2010 Modified Files: src/sys/arch/mips/conf [matt-nb5-mips64]: files.mips src/sys/arch/mips/include [matt-nb5-mips64]: cpu.h cpuregs.h locore.h mips_param.h types.h src/sys/arch/mips/mips [matt-nb5-mips64]: genassym.cf locore.S vm_machdep.c Added Files: src/sys/arch/mips/mips [matt-nb5-mips64]: mips_softint.c Removed Files: src/sys/arch/mips/mips [matt-nb5-mips64]: softintr.c Log Message: Add __HAVE_FAST_SOFTINTS support. Add routine to remap an uarea via a direct-mapped address. This avoids TLB machinations when swtching to/from the softint thread. This can only be done for lwp which won't exit. To generate a diff of this commit: cvs rdiff -u -r1.58.24.6 -r1.58.24.7 src/sys/arch/mips/conf/files.mips cvs rdiff -u -r1.90.16.17 -r1.90.16.18 src/sys/arch/mips/include/cpu.h cvs rdiff -u -r1.74.28.13 -r1.74.28.14 src/sys/arch/mips/include/cpuregs.h cvs rdiff -u -r1.78.36.1.2.11 -r1.78.36.1.2.12 \ src/sys/arch/mips/include/locore.h cvs rdiff -u -r1.23.78.4 -r1.23.78.5 src/sys/arch/mips/include/mips_param.h cvs rdiff -u -r1.43.36.12 -r1.43.36.13 src/sys/arch/mips/include/types.h cvs rdiff -u -r1.44.12.13 -r1.44.12.14 src/sys/arch/mips/mips/genassym.cf cvs rdiff -u -r1.167.38.8 -r1.167.38.9 src/sys/arch/mips/mips/locore.S cvs rdiff -u -r0 -r1.1.2.1 src/sys/arch/mips/mips/mips_softint.c cvs rdiff -u -r1.7 -r0 src/sys/arch/mips/mips/softintr.c cvs rdiff -u -r1.121.6.1.2.9 -r1.121.6.1.2.10 \ src/sys/arch/mips/mips/vm_machdep.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [matt-nb5-mips64] src/sys/arch
Module Name:src Committed By: matt Date: Fri Feb 5 07:39:54 UTC 2010 Modified Files: src/sys/arch/algor/algor [matt-nb5-mips64]: interrupt.c src/sys/arch/algor/conf [matt-nb5-mips64]: files.algor src/sys/arch/arc/arc [matt-nb5-mips64]: interrupt.c src/sys/arch/arc/conf [matt-nb5-mips64]: files.arc src/sys/arch/cobalt/cobalt [matt-nb5-mips64]: interrupt.c src/sys/arch/cobalt/conf [matt-nb5-mips64]: files.cobalt src/sys/arch/evbmips/conf [matt-nb5-mips64]: WGT624V3 files.adm5120 files.alchemy files.atheros files.malta files.rmixl src/sys/arch/evbmips/evbmips [matt-nb5-mips64]: interrupt.c src/sys/arch/ews4800mips/conf [matt-nb5-mips64]: files.ews4800mips src/sys/arch/ews4800mips/ews4800mips [matt-nb5-mips64]: interrupt.c src/sys/arch/hpcmips/tx [matt-nb5-mips64]: tx39icu.c src/sys/arch/hpcmips/vr [matt-nb5-mips64]: vr.c src/sys/arch/mipsco/include [matt-nb5-mips64]: intr.h src/sys/arch/mipsco/mipsco [matt-nb5-mips64]: interrupt.c src/sys/arch/newsmips/conf [matt-nb5-mips64]: files.newsmips src/sys/arch/newsmips/newsmips [matt-nb5-mips64]: machdep.c src/sys/arch/pmax/conf [matt-nb5-mips64]: GENERIC files.pmax src/sys/arch/pmax/pmax [matt-nb5-mips64]: interrupt.c src/sys/arch/sbmips/conf [matt-nb5-mips64]: files.sbmips src/sys/arch/sbmips/sbmips [matt-nb5-mips64]: sb1250_icu.c src/sys/arch/sgimips/sgimips [matt-nb5-mips64]: cpu.c Log Message: Change to deal with new method of invoking softints. Remove mips/softintr.c from config files. Fix SYMTAB_SPACE for WGT62V43 To generate a diff of this commit: cvs rdiff -u -r1.13.18.1 -r1.13.18.2 src/sys/arch/algor/algor/interrupt.c cvs rdiff -u -r1.24 -r1.24.28.1 src/sys/arch/algor/conf/files.algor cvs rdiff -u -r1.4 -r1.4.22.1 src/sys/arch/arc/arc/interrupt.c cvs rdiff -u -r1.62 -r1.62.28.1 src/sys/arch/arc/conf/files.arc cvs rdiff -u -r1.3 -r1.3.16.1 src/sys/arch/cobalt/cobalt/interrupt.c cvs rdiff -u -r1.33 -r1.33.16.1 src/sys/arch/cobalt/conf/files.cobalt cvs rdiff -u -r1.3.8.1 -r1.3.8.2 src/sys/arch/evbmips/conf/WGT624V3 cvs rdiff -u -r1.5.28.1 -r1.5.28.2 src/sys/arch/evbmips/conf/files.adm5120 cvs rdiff -u -r1.9.28.1 -r1.9.28.2 src/sys/arch/evbmips/conf/files.alchemy cvs rdiff -u -r1.6.28.1 -r1.6.28.2 src/sys/arch/evbmips/conf/files.atheros cvs rdiff -u -r1.15.28.2 -r1.15.28.3 src/sys/arch/evbmips/conf/files.malta cvs rdiff -u -r1.1.2.4 -r1.1.2.5 src/sys/arch/evbmips/conf/files.rmixl cvs rdiff -u -r1.11.18.1 -r1.11.18.2 src/sys/arch/evbmips/evbmips/interrupt.c cvs rdiff -u -r1.3 -r1.3.28.1 src/sys/arch/ews4800mips/conf/files.ews4800mips cvs rdiff -u -r1.4 -r1.4.18.1 \ src/sys/arch/ews4800mips/ews4800mips/interrupt.c cvs rdiff -u -r1.25 -r1.25.18.1 src/sys/arch/hpcmips/tx/tx39icu.c cvs rdiff -u -r1.51 -r1.51.22.1 src/sys/arch/hpcmips/vr/vr.c cvs rdiff -u -r1.16 -r1.16.36.1 src/sys/arch/mipsco/include/intr.h cvs rdiff -u -r1.6 -r1.6.18.1 src/sys/arch/mipsco/mipsco/interrupt.c cvs rdiff -u -r1.26 -r1.26.28.1 src/sys/arch/newsmips/conf/files.newsmips cvs rdiff -u -r1.98.10.3 -r1.98.10.4 src/sys/arch/newsmips/newsmips/machdep.c cvs rdiff -u -r1.158 -r1.158.8.1 src/sys/arch/pmax/conf/GENERIC cvs rdiff -u -r1.111 -r1.111.28.1 src/sys/arch/pmax/conf/files.pmax cvs rdiff -u -r1.15.18.1 -r1.15.18.2 src/sys/arch/pmax/pmax/interrupt.c cvs rdiff -u -r1.14.28.1 -r1.14.28.2 src/sys/arch/sbmips/conf/files.sbmips cvs rdiff -u -r1.9.36.2 -r1.9.36.3 src/sys/arch/sbmips/sbmips/sb1250_icu.c cvs rdiff -u -r1.21.36.2 -r1.21.36.3 src/sys/arch/sgimips/sgimips/cpu.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
Re: CVS commit: [matt-nb5-mips64] src/sys/arch/mips
On Sun, Jan 31, 2010 at 01:33:59AM +, David Holland wrote: gcc does not seem to be very deterministic about this kind of thing. I've being trying to stop gcc using too many registers in another project - with 24 available registers you'd think it would manage not to spill locals to the stack! But no, the 'status function' (which just copies info into a big buffer with a few local actions) managed to generate temporaries all of its own! In this case marking the target buffer 'volatile' helped no end! David -- David Laight: da...@l8s.co.uk
Re: CVS commit: [matt-nb5-mips64] src/sys/arch/mips
David A. Holland said; Change MIPS_CURLWP from s7 to t8. ... Huh. That surprises me slightly. Good to know though. Remember to bump the kernel version when you merge the branch, or anyone using modules will get a nasty surprise :-) It's a major incompatiblity to change MIPS label_t definition (for pcb-pcb_context), which I hesitate to accept. Yes, a large caution (for NetBSD mips people) is required before branch merge. Toru Nishimura / ALKYL Technology
CVS commit: [matt-nb5-mips64] src/sys/arch
Module Name:src Committed By: matt Date: Mon Feb 1 04:17:51 UTC 2010 Modified Files: src/sys/arch/arc/arc [matt-nb5-mips64]: machdep.c src/sys/arch/cobalt/cobalt [matt-nb5-mips64]: machdep.c src/sys/arch/evbmips/adm5120 [matt-nb5-mips64]: machdep.c src/sys/arch/evbmips/alchemy [matt-nb5-mips64]: machdep.c src/sys/arch/evbmips/atheros [matt-nb5-mips64]: machdep.c src/sys/arch/evbmips/malta [matt-nb5-mips64]: machdep.c src/sys/arch/evbmips/rmixl [matt-nb5-mips64]: machdep.c src/sys/arch/ews4800mips/ews4800mips [matt-nb5-mips64]: machdep.c Log Message: fix fallout from frame/trapframe merger. To generate a diff of this commit: cvs rdiff -u -r1.112.10.2 -r1.112.10.3 src/sys/arch/arc/arc/machdep.c cvs rdiff -u -r1.98.10.1 -r1.98.10.2 src/sys/arch/cobalt/cobalt/machdep.c cvs rdiff -u -r1.6.10.3 -r1.6.10.4 src/sys/arch/evbmips/adm5120/machdep.c cvs rdiff -u -r1.37.10.3 -r1.37.10.4 src/sys/arch/evbmips/alchemy/machdep.c cvs rdiff -u -r1.13.10.4 -r1.13.10.5 src/sys/arch/evbmips/atheros/machdep.c cvs rdiff -u -r1.28.10.3 -r1.28.10.4 src/sys/arch/evbmips/malta/machdep.c cvs rdiff -u -r1.1.2.18 -r1.1.2.19 src/sys/arch/evbmips/rmixl/machdep.c cvs rdiff -u -r1.14.10.2 -r1.14.10.3 \ src/sys/arch/ews4800mips/ews4800mips/machdep.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [matt-nb5-mips64] src/sys/arch
Module Name:src Committed By: matt Date: Mon Feb 1 04:18:32 UTC 2010 Modified Files: src/sys/arch/hpcmips/hpcmips [matt-nb5-mips64]: machdep.c src/sys/arch/hpcmips/tx [matt-nb5-mips64]: tx39.c src/sys/arch/mipsco/mipsco [matt-nb5-mips64]: machdep.c mips_3x30.c src/sys/arch/newsmips/newsmips [matt-nb5-mips64]: machdep.c news3400.c src/sys/arch/sbmips/sbmips [matt-nb5-mips64]: machdep.c src/sys/arch/sgimips/sgimips [matt-nb5-mips64]: cpu.c machdep.c Log Message: fix fallout from frame/trapframe merger. To generate a diff of this commit: cvs rdiff -u -r1.96.10.3 -r1.96.10.4 src/sys/arch/hpcmips/hpcmips/machdep.c cvs rdiff -u -r1.39 -r1.39.18.1 src/sys/arch/hpcmips/tx/tx39.c cvs rdiff -u -r1.58.10.1 -r1.58.10.2 src/sys/arch/mipsco/mipsco/machdep.c cvs rdiff -u -r1.10 -r1.10.18.1 src/sys/arch/mipsco/mipsco/mips_3x30.c cvs rdiff -u -r1.98.10.2 -r1.98.10.3 src/sys/arch/newsmips/newsmips/machdep.c cvs rdiff -u -r1.19 -r1.19.36.1 src/sys/arch/newsmips/newsmips/news3400.c cvs rdiff -u -r1.38.10.5 -r1.38.10.6 src/sys/arch/sbmips/sbmips/machdep.c cvs rdiff -u -r1.21.36.1 -r1.21.36.2 src/sys/arch/sgimips/sgimips/cpu.c cvs rdiff -u -r1.121.8.3 -r1.121.8.4 src/sys/arch/sgimips/sgimips/machdep.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [matt-nb5-mips64] src/sys/arch/pmax/pmax
Module Name:src Committed By: matt Date: Mon Feb 1 06:09:21 UTC 2010 Modified Files: src/sys/arch/pmax/pmax [matt-nb5-mips64]: bus_dma.c dec_3100.c dec_3max.c dec_3min.c dec_maxine.c interrupt.c machdep.c Log Message: Update to reflect mips tree changes. To generate a diff of this commit: cvs rdiff -u -r1.49.16.1 -r1.49.16.2 src/sys/arch/pmax/pmax/bus_dma.c cvs rdiff -u -r1.44 -r1.44.36.1 src/sys/arch/pmax/pmax/dec_3100.c cvs rdiff -u -r1.45 -r1.45.36.1 src/sys/arch/pmax/pmax/dec_3max.c cvs rdiff -u -r1.60.22.1 -r1.60.22.2 src/sys/arch/pmax/pmax/dec_3min.c cvs rdiff -u -r1.52.28.1 -r1.52.28.2 src/sys/arch/pmax/pmax/dec_maxine.c cvs rdiff -u -r1.15 -r1.15.18.1 src/sys/arch/pmax/pmax/interrupt.c cvs rdiff -u -r1.223.8.1.2.4 -r1.223.8.1.2.5 src/sys/arch/pmax/pmax/machdep.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
