CVS commit: [netbsd-10] src/sys/arch/x86/pci
Module Name:src
Committed By: martin
Date: Wed Aug 23 17:05:39 UTC 2023
Modified Files:
src/sys/arch/x86/pci [netbsd-10]: pci_machdep.c
Log Message:
Pull up following revision(s) (requested by msaitoh in ticket #337):
sys/arch/x86/pci/pci_machdep.c: revision 1.94
Fix detection of availability of MSI/MSI-X on some systems.
Try to find all functions on bus 0, device 0 to find a PCI host bridge.
Some CPU's host bridge is at 0:0.4. Tested by Intel Snow Ridge.
To generate a diff of this commit:
cvs rdiff -u -r1.93 -r1.93.4.1 src/sys/arch/x86/pci/pci_machdep.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/pci/pci_machdep.c
diff -u src/sys/arch/x86/pci/pci_machdep.c:1.93 src/sys/arch/x86/pci/pci_machdep.c:1.93.4.1
--- src/sys/arch/x86/pci/pci_machdep.c:1.93 Tue Sep 6 01:44:24 2022
+++ src/sys/arch/x86/pci/pci_machdep.c Wed Aug 23 17:05:39 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: pci_machdep.c,v 1.93 2022/09/06 01:44:24 msaitoh Exp $ */
+/* $NetBSD: pci_machdep.c,v 1.93.4.1 2023/08/23 17:05:39 martin Exp $ */
/*-
* Copyright (c) 1997, 1998 The NetBSD Foundation, Inc.
@@ -73,7 +73,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.93 2022/09/06 01:44:24 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.93.4.1 2023/08/23 17:05:39 martin Exp $");
#include
#include
@@ -485,6 +485,8 @@ pci_attach_hook(device_t parent, device_
pci_chipset_tag_t pc = pba->pba_pc;
pcitag_t tag;
pcireg_t id, class;
+ int i;
+ bool havehb = false;
#endif
if (pba->pba_bus == 0)
@@ -502,19 +504,25 @@ pci_attach_hook(device_t parent, device_
#ifdef __HAVE_PCI_MSI_MSIX
/*
* In order to decide whether the system supports MSI we look
- * at the host bridge, which should be device 0 function 0 on
- * bus 0. It is better to not enable MSI on systems that
+ * at the host bridge, which should be device 0 on bus 0.
+ * It is better to not enable MSI on systems that
* support it than the other way around, so be conservative
* here. So we don't enable MSI if we don't find a host
* bridge there. We also deliberately don't enable MSI on
* chipsets from low-end manifacturers like VIA and SiS.
*/
- tag = pci_make_tag(pc, 0, 0, 0);
- id = pci_conf_read(pc, tag, PCI_ID_REG);
- class = pci_conf_read(pc, tag, PCI_CLASS_REG);
-
- if (PCI_CLASS(class) != PCI_CLASS_BRIDGE ||
- PCI_SUBCLASS(class) != PCI_SUBCLASS_BRIDGE_HOST)
+ for (i = 0; i <= 7; i++) {
+ tag = pci_make_tag(pc, 0, 0, i);
+ id = pci_conf_read(pc, tag, PCI_ID_REG);
+ class = pci_conf_read(pc, tag, PCI_CLASS_REG);
+
+ if (PCI_CLASS(class) == PCI_CLASS_BRIDGE &&
+ PCI_SUBCLASS(class) == PCI_SUBCLASS_BRIDGE_HOST) {
+ havehb = true;
+ break;
+ }
+ }
+ if (havehb == false)
return;
/* VMware and KVM use old chipset, but they can use MSI/MSI-X */
CVS commit: [netbsd-10] src/sys/arch/x86/pci
Module Name:src Committed By: martin Date: Wed Aug 23 17:05:39 UTC 2023 Modified Files: src/sys/arch/x86/pci [netbsd-10]: pci_machdep.c Log Message: Pull up following revision(s) (requested by msaitoh in ticket #337): sys/arch/x86/pci/pci_machdep.c: revision 1.94 Fix detection of availability of MSI/MSI-X on some systems. Try to find all functions on bus 0, device 0 to find a PCI host bridge. Some CPU's host bridge is at 0:0.4. Tested by Intel Snow Ridge. To generate a diff of this commit: cvs rdiff -u -r1.93 -r1.93.4.1 src/sys/arch/x86/pci/pci_machdep.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [netbsd-10] src/sys/arch/x86/pci
Module Name:src
Committed By: martin
Date: Tue Aug 22 16:07:34 UTC 2023
Modified Files:
src/sys/arch/x86/pci [netbsd-10]: amdsmn.c amdzentemp.c
Log Message:
Pull up following revision(s) (requested by msaitoh in ticket #335):
sys/arch/x86/pci/amdzentemp.c: revision 1.20
sys/arch/x86/pci/amdsmn.c: revision 1.17
sys/arch/x86/pci/amdzentemp.c: revision 1.19
Add Zen4 Ryzen "Phoenix" support.
Add Zen2 Mendocino APU support.
Add Zen4 Phoenix support.
To generate a diff of this commit:
cvs rdiff -u -r1.14.4.2 -r1.14.4.3 src/sys/arch/x86/pci/amdsmn.c
cvs rdiff -u -r1.16.2.1 -r1.16.2.2 src/sys/arch/x86/pci/amdzentemp.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/pci/amdsmn.c
diff -u src/sys/arch/x86/pci/amdsmn.c:1.14.4.2 src/sys/arch/x86/pci/amdsmn.c:1.14.4.3
--- src/sys/arch/x86/pci/amdsmn.c:1.14.4.2 Wed Jun 21 16:58:11 2023
+++ src/sys/arch/x86/pci/amdsmn.c Tue Aug 22 16:07:34 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: amdsmn.c,v 1.14.4.2 2023/06/21 16:58:11 martin Exp $ */
+/* $NetBSD: amdsmn.c,v 1.14.4.3 2023/08/22 16:07:34 martin Exp $ */
/*-
* Copyright (c) 2017, 2019 Conrad Meyer
@@ -29,7 +29,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: amdsmn.c,v 1.14.4.2 2023/06/21 16:58:11 martin Exp $ ");
+__KERNEL_RCSID(0, "$NetBSD: amdsmn.c,v 1.14.4.3 2023/08/22 16:07:34 martin Exp $ ");
/*
* Driver for the AMD Family 15h (model 60+) and 17h CPU
@@ -112,6 +112,11 @@ static const struct pciid {
.amdsmn_addr_reg = F17H_SMN_ADDR_REG,
.amdsmn_data_reg = F17H_SMN_DATA_REG,
},
+ {
+ .amdsmn_deviceid = PCI_PRODUCT_AMD_F19_7X_RC,
+ .amdsmn_addr_reg = F17H_SMN_ADDR_REG,
+ .amdsmn_data_reg = F17H_SMN_DATA_REG,
+ },
};
static int amdsmn_match(device_t, cfdata_t, void *);
Index: src/sys/arch/x86/pci/amdzentemp.c
diff -u src/sys/arch/x86/pci/amdzentemp.c:1.16.2.1 src/sys/arch/x86/pci/amdzentemp.c:1.16.2.2
--- src/sys/arch/x86/pci/amdzentemp.c:1.16.2.1 Wed Jun 21 16:58:11 2023
+++ src/sys/arch/x86/pci/amdzentemp.c Tue Aug 22 16:07:34 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: amdzentemp.c,v 1.16.2.1 2023/06/21 16:58:11 martin Exp $ */
+/* $NetBSD: amdzentemp.c,v 1.16.2.2 2023/08/22 16:07:34 martin Exp $ */
/* $OpenBSD: kate.c,v 1.2 2008/03/27 04:52:03 cnst Exp $ */
/*
@@ -53,7 +53,7 @@
#include
-__KERNEL_RCSID(0, "$NetBSD: amdzentemp.c,v 1.16.2.1 2023/06/21 16:58:11 martin Exp $ ");
+__KERNEL_RCSID(0, "$NetBSD: amdzentemp.c,v 1.16.2.2 2023/08/22 16:07:34 martin Exp $ ");
#include
#include
@@ -370,15 +370,19 @@ amdzentemp_probe_ccd_sensors17h(struct a
{
int maxreg;
- sc->sc_ccd_offset = 0x154;
-
switch (model) {
case 0x00 ... 0x2f: /* Zen1, Zen+ */
+ sc->sc_ccd_offset = 0x154;
maxreg = 4;
break;
case 0x30 ... 0x3f: /* Zen2 TR (Castle Peak)/EPYC (Rome) */
case 0x60 ... 0x7f: /* Zen2 Ryzen (Renoir APU, Matisse) */
case 0x90 ... 0x9f: /* Zen2 Ryzen (Van Gogh APU) */
+ sc->sc_ccd_offset = 0x154;
+ maxreg = 8;
+ break;
+ case 0xa0 ... 0xaf: /* Zen2 Ryzen (Mendocino APU) */
+ sc->sc_ccd_offset = 0x300;
maxreg = 8;
break;
default:
@@ -403,6 +407,7 @@ amdzentemp_probe_ccd_sensors19h(struct a
maxreg = 8;
break;
case 0x60 ... 0x6f: /* Zen4 Ryzen "Raphael" */
+ case 0x70 ... 0x7f: /* Zen4 Ryzen "Phoenix" */
sc->sc_ccd_offset = 0x308;
maxreg = 8;
break;
CVS commit: [netbsd-10] src/sys/arch/x86/pci
Module Name:src Committed By: martin Date: Tue Aug 22 16:07:34 UTC 2023 Modified Files: src/sys/arch/x86/pci [netbsd-10]: amdsmn.c amdzentemp.c Log Message: Pull up following revision(s) (requested by msaitoh in ticket #335): sys/arch/x86/pci/amdzentemp.c: revision 1.20 sys/arch/x86/pci/amdsmn.c: revision 1.17 sys/arch/x86/pci/amdzentemp.c: revision 1.19 Add Zen4 Ryzen "Phoenix" support. Add Zen2 Mendocino APU support. Add Zen4 Phoenix support. To generate a diff of this commit: cvs rdiff -u -r1.14.4.2 -r1.14.4.3 src/sys/arch/x86/pci/amdsmn.c cvs rdiff -u -r1.16.2.1 -r1.16.2.2 src/sys/arch/x86/pci/amdzentemp.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [netbsd-10] src/sys/arch/x86/pci
Module Name:src
Committed By: martin
Date: Wed Jun 21 16:58:11 UTC 2023
Modified Files:
src/sys/arch/x86/pci [netbsd-10]: amdsmn.c amdzentemp.c
Log Message:
Pull up following revision(s) (requested by msaitoh in ticket #198):
sys/arch/x86/pci/amdsmn.c: revision 1.16
sys/arch/x86/pci/amdzentemp.c: revision 1.17
sys/arch/x86/pci/amdzentemp.c: revision 1.18
Reduce diff against DragonFly. No functional change.
amdsmn(4),amdzentemp(4): Add Zen3+ Rembrandt(19h/4xh) & Zen4 Genoa(19h/1xh).
To generate a diff of this commit:
cvs rdiff -u -r1.14.4.1 -r1.14.4.2 src/sys/arch/x86/pci/amdsmn.c
cvs rdiff -u -r1.16 -r1.16.2.1 src/sys/arch/x86/pci/amdzentemp.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/pci/amdsmn.c
diff -u src/sys/arch/x86/pci/amdsmn.c:1.14.4.1 src/sys/arch/x86/pci/amdsmn.c:1.14.4.2
--- src/sys/arch/x86/pci/amdsmn.c:1.14.4.1 Mon Dec 19 11:37:14 2022
+++ src/sys/arch/x86/pci/amdsmn.c Wed Jun 21 16:58:11 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: amdsmn.c,v 1.14.4.1 2022/12/19 11:37:14 martin Exp $ */
+/* $NetBSD: amdsmn.c,v 1.14.4.2 2023/06/21 16:58:11 martin Exp $ */
/*-
* Copyright (c) 2017, 2019 Conrad Meyer
@@ -29,7 +29,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: amdsmn.c,v 1.14.4.1 2022/12/19 11:37:14 martin Exp $ ");
+__KERNEL_RCSID(0, "$NetBSD: amdsmn.c,v 1.14.4.2 2023/06/21 16:58:11 martin Exp $ ");
/*
* Driver for the AMD Family 15h (model 60+) and 17h CPU
@@ -93,7 +93,17 @@ static const struct pciid {
.amdsmn_data_reg = F17H_SMN_DATA_REG,
},
{
- .amdsmn_deviceid = PCI_PRODUCT_AMD_F17_7X_RC,
+ .amdsmn_deviceid = PCI_PRODUCT_AMD_F17_7X_RC, /* or F19_0X */
+ .amdsmn_addr_reg = F17H_SMN_ADDR_REG,
+ .amdsmn_data_reg = F17H_SMN_DATA_REG,
+ },
+ {
+ .amdsmn_deviceid = PCI_PRODUCT_AMD_F17_AX_RC, /* or F19_4X */
+ .amdsmn_addr_reg = F17H_SMN_ADDR_REG,
+ .amdsmn_data_reg = F17H_SMN_DATA_REG,
+ },
+ {
+ .amdsmn_deviceid = PCI_PRODUCT_AMD_F19_1X_RC,
.amdsmn_addr_reg = F17H_SMN_ADDR_REG,
.amdsmn_data_reg = F17H_SMN_DATA_REG,
},
Index: src/sys/arch/x86/pci/amdzentemp.c
diff -u src/sys/arch/x86/pci/amdzentemp.c:1.16 src/sys/arch/x86/pci/amdzentemp.c:1.16.2.1
--- src/sys/arch/x86/pci/amdzentemp.c:1.16 Thu Nov 24 21:03:38 2022
+++ src/sys/arch/x86/pci/amdzentemp.c Wed Jun 21 16:58:11 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: amdzentemp.c,v 1.16 2022/11/24 21:03:38 mrg Exp $ */
+/* $NetBSD: amdzentemp.c,v 1.16.2.1 2023/06/21 16:58:11 martin Exp $ */
/* $OpenBSD: kate.c,v 1.2 2008/03/27 04:52:03 cnst Exp $ */
/*
@@ -53,7 +53,7 @@
#include
-__KERNEL_RCSID(0, "$NetBSD: amdzentemp.c,v 1.16 2022/11/24 21:03:38 mrg Exp $ ");
+__KERNEL_RCSID(0, "$NetBSD: amdzentemp.c,v 1.16.2.1 2023/06/21 16:58:11 martin Exp $ ");
#include
#include
@@ -74,7 +74,6 @@ __KERNEL_RCSID(0, "$NetBSD: amdzentemp.c
#include "amdsmn.h"
#define AMD_CURTMP_RANGE_ADJUST 4900 /* in microKelvins (ie, 49C) */
-#define AMD_CURTMP_RANGE_CHECK __BIT(19)
#define F10_TEMP_CURTMP __BITS(31,21) /* XXX same as amdtemp.c */
#define F10_TEMP_CURTMP_MASK 0x7ff
#define F15M60_CURTMP_TJSEL __BITS(17,16)
@@ -96,14 +95,7 @@ __KERNEL_RCSID(0, "$NetBSD: amdzentemp.c
* to -49..206C.
*/
#define AMD_17H_CUR_TMP 0x59800
-
-/*
- * The following register set was discovered experimentally by Ondrej Čerman
- * and collaborators, but is not (yet) documented in a PPR/OSRR (other than
- * the M70H PPR SMN memory map showing [0x59800, +0x314] as allocated to
- * SMU::THM). It seems plausible and the Linux sensor folks have adopted it.
- */
-#define AMD_17H_CCD_TMP_BASE 0x59954
+#define AMD_17H_CUR_TMP_RANGE_SEL __BIT(19)
#define AMD_17H_CCD_TMP_VALID __BIT(11)
struct amdzentemp_softc {
@@ -114,7 +106,7 @@ struct amdzentemp_softc {
size_t sc_sensor_len;
size_t sc_numsensors;
int32_t sc_offset;
- uint32_t sc_ccd_tmp_base;
+ int32_t sc_ccd_offset;
};
enum {
@@ -129,6 +121,10 @@ enum {
CCD5,
CCD6,
CCD7,
+ CCD8,
+ CCD9,
+ CCD10,
+ CCD11,
CCD_MAX,
NUM_CCDS = CCD_MAX - CCD_BASE
};
@@ -339,14 +335,16 @@ amdzentemp_family17_refresh(struct sysmo
edata->state = ENVSYS_SINVALID;
return;
}
- minus49 = (temp & AMD_CURTMP_RANGE_CHECK) ? true : false;
+ minus49 = (temp & AMD_17H_CUR_TMP_RANGE_SEL) ?
+ true : false;
temp = __SHIFTOUT(temp, F10_TEMP_CURTMP);
break;
case CCD_BASE ... (CCD_MAX - 1):
/* Tccd */
i = edata->private - CCD_BASE;
error = amdsmn_read(sc->sc_smn,
- sc->sc_ccd_tmp_base + (i * sizeof(temp)), );
+ AMD_17H_CUR_TMP + sc->sc_ccd_offset + (i * sizeof(temp)),
+ );
if (error || !ISSET(temp, AMD_17H_CCD_TMP_VALID)) {
edata->state = ENVSYS_SINVALID;
return;
@@ -372,6 +370,8 @@ amdzentemp_probe_ccd_sensors17h(struct a
{
int maxreg;
+ sc->sc_ccd_offset = 0x154;
+
switch (model) {
case 0x00 ... 0x2f: /* Zen1, Zen+ */
maxreg = 4;
@@ -399,12 +399,21 @@
CVS commit: [netbsd-10] src/sys/arch/x86/pci
Module Name:src Committed By: martin Date: Wed Jun 21 16:58:11 UTC 2023 Modified Files: src/sys/arch/x86/pci [netbsd-10]: amdsmn.c amdzentemp.c Log Message: Pull up following revision(s) (requested by msaitoh in ticket #198): sys/arch/x86/pci/amdsmn.c: revision 1.16 sys/arch/x86/pci/amdzentemp.c: revision 1.17 sys/arch/x86/pci/amdzentemp.c: revision 1.18 Reduce diff against DragonFly. No functional change. amdsmn(4),amdzentemp(4): Add Zen3+ Rembrandt(19h/4xh) & Zen4 Genoa(19h/1xh). To generate a diff of this commit: cvs rdiff -u -r1.14.4.1 -r1.14.4.2 src/sys/arch/x86/pci/amdsmn.c cvs rdiff -u -r1.16 -r1.16.2.1 src/sys/arch/x86/pci/amdzentemp.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
