Re: CVS commit: src/sys/arch/aarch64/aarch64

2021-02-23 Thread Jared McNeill

On Mon, 22 Feb 2021, Ryo Shimizu wrote:


I think this condition is not necessary since cpu_idle() is just called from 
idle_loop(),
and ci_intr_depth is always zero at this time.


Ah yes, my mistake! Please feel free to revert this commit as part of 
your proposed change.


Re: CVS commit: src/sys/arch/aarch64/aarch64

2021-02-22 Thread Jason Thorpe


> On Feb 22, 2021, at 11:49 AM, Ryo Shimizu  wrote:
> 
> Ah, You are quite right!
> idle/# lwp is provided and assigned for each CPU, so curcpu() obtained from
> idle lwp was always the same.
> So, there's no need to move curcpu() to after DISABLE_INTERRUPT.

Please make sure to add a comment explaining why!

-- thorpej



Re: CVS commit: src/sys/arch/aarch64/aarch64

2021-02-22 Thread Ryo Shimizu


>> In addition, because of the possibility of kpreemption (but aarch64 has =
>no KPREEMPT yet),
>> the acquisition of curcpu() is moved to after DISABLE_INTERRUPT and got =
>the following.
>>
>[snip]
>
>
>>
>> Is this ok?
>>
>
>Looks good - I wonder if the fact that curcpu is an invariant for the
>idlelwp helps here too?

Ah, You are quite right!
idle/# lwp is provided and assigned for each CPU, so curcpu() obtained from
idle lwp was always the same.
So, there's no need to move curcpu() to after DISABLE_INTERRUPT.

Thanks
-- 
ryo shimizu


Re: CVS commit: src/sys/arch/aarch64/aarch64

2021-02-22 Thread Nick Hudson

On 22/02/2021 10:40, Ryo Shimizu wrote:



Module Name:src
Committed By:   jmcneill
Date:   Sun Feb 21 23:37:10 UTC 2021

Modified Files:
src/sys/arch/aarch64/aarch64: idle_machdep.S

Log Message:
When waking from cpu_idle(), only call dosoftints if ci_intr_depth == 0


To generate a diff of this commit:
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/aarch64/aarch64/idle_machdep.S


I think this condition is not necessary since cpu_idle() is just called from 
idle_loop(),
and ci_intr_depth is always zero at this time.

After thinking about it, I realized that there is no need to even increment 
intr_depth.

   curcpu()->ci_ntr_depth = 1;
   ARM_IRQ_HANDLER();
   curcpu()->ci_ntr_depth = 0;


In addition, because of the possibility of kpreemption (but aarch64 has no 
KPREEMPT yet),
the acquisition of curcpu() is moved to after DISABLE_INTERRUPT and got the 
following.


[snip]




Is this ok?



Looks good - I wonder if the fact that curcpu is an invariant for the
idlelwp helps here too?

Nick


Re: CVS commit: src/sys/arch/aarch64/aarch64

2021-02-22 Thread Ryo Shimizu


>Module Name:   src
>Committed By:  jmcneill
>Date:  Sun Feb 21 23:37:10 UTC 2021
>
>Modified Files:
>   src/sys/arch/aarch64/aarch64: idle_machdep.S
>
>Log Message:
>When waking from cpu_idle(), only call dosoftints if ci_intr_depth == 0
>
>
>To generate a diff of this commit:
>cvs rdiff -u -r1.7 -r1.8 src/sys/arch/aarch64/aarch64/idle_machdep.S

I think this condition is not necessary since cpu_idle() is just called from 
idle_loop(),
and ci_intr_depth is always zero at this time.

After thinking about it, I realized that there is no need to even increment 
intr_depth.

  curcpu()->ci_ntr_depth = 1;
  ARM_IRQ_HANDLER();
  curcpu()->ci_ntr_depth = 0;


In addition, because of the possibility of kpreemption (but aarch64 has no 
KPREEMPT yet),
the acquisition of curcpu() is moved to after DISABLE_INTERRUPT and got the 
following.

cvs -q diff -aU10 -a -p idle_machdep.S
Index: idle_machdep.S
===
RCS file: /src/cvs/cvsroot-netbsd/src/sys/arch/aarch64/aarch64/idle_machdep.S,v
retrieving revision 1.8
diff -a -U 10 -a -p -r1.8 idle_machdep.S
--- idle_machdep.S  21 Feb 2021 23:37:09 -  1.8
+++ idle_machdep.S  22 Feb 2021 10:16:25 -
@@ -67,40 +67,36 @@ ENTRY(cpu_idle)
stp x29, x30, [sp, #TF_X29] /* save x29,x30 */
 #ifdef DDB
add x29, sp, #TF_X29/* link frame for backtrace */
 #endif
 
/* fill the minimum required trapframe */
mov x2, #SPSR_M_EL1H/* what our spsr should be */
str x2, [sp, #TF_SPSR]
adr x0, 1f
str x0, [sp, #TF_PC]/* CLKF_PC refer to tf_pc */
-
-   mrs x1, tpidr_el1   /* get curlwp */
-   ldr x1, [x1, #L_CPU]/* get curcpu */
-   ldr w28, [x1, #CI_INTR_DEPTH]   /* w28 = ci->ci_intr_depth */
-   add w2, w28, #1 /* w2 = intr_depth + 1 */
-
mov x0, sp  /* get pointer to trapframe */
+   mrs x1, tpidr_el1   /* get curlwp */
 
DISABLE_INTERRUPT
-   wfi
+   ldr x1, [x1, #L_CPU]/* get curcpu */
+   mov w2, #1
+   str w2, [x1, #CI_INTR_DEPTH]/* ci->ci_intr_depth = 1 */
 
-   str w2, [x1, #CI_INTR_DEPTH]/* ci->ci_intr_depth++ */
+   wfi
bl  ARM_IRQ_HANDLER /* irqhandler(trapframe) */
 1:
mrs x1, tpidr_el1   /* get curlwp */
ldr x1, [x1, #L_CPU]/* get curcpu */
-   str w28, [x1, #CI_INTR_DEPTH]   /* ci->ci_intr_depth = old */
+   str wzr, [x1, #CI_INTR_DEPTH]   /* ci->ci_intr_depth = 0 */
 
 #if defined(__HAVE_FAST_SOFTINTS) && !defined(__HAVE_PIC_FAST_SOFTINTS)
-   cbnzw28, 1f /* Skip if intr_depth > 0 */
ldr w3, [x1, #CI_SOFTINTS]  /* Get pending softint mask */
/* CPL should be 0 */
ldr w2, [x1, #CI_CPL]   /* Get current priority level */
lsr w3, w3, w2  /* shift mask by cpl */
cbz w3, 1f
bl  _C_LABEL(dosoftints)/* dosoftints() */
 1:
 #endif /* __HAVE_FAST_SOFTINTS && !__HAVE_PIC_FAST_SOFTINTS */
 
ldr x28, [sp, #TF_X28]  /* restore x28 */


Is this ok?
-- 
ryo shimizu


re: CVS commit: src/sys/arch/aarch64/aarch64

2021-01-17 Thread matthew green
> Log Message:
> Fix build as crash(8); Protect db_md_meminfo_cmd() by defined(_KERNEL).

thanks.  surprised i never saw this as the change was in a
tree for a few weeks, but i guess i was mostly doing kernels
in that tree not full builds..


.mrg.


Re: CVS commit: src/sys/arch/aarch64/aarch64

2020-10-13 Thread Martin Husemann
On Tue, Oct 13, 2020 at 12:57:44PM +0200, Kamil Rytarowski wrote:
> > Log Message:
> > BE32 binaries are no longer supported for ARMv7 and later, and
> > therefore for aarch64eb.
> > 
> > Reject them with ENOEXEC, rather than causing illegal instruction
> > exceptions due to unexpected binary format.

> Not supported in general or on NetBSD? Big Endian 32bit is supported on
> Cavium ThunderX (at least on a selection of models if not all of them).

The new supported format is BE-8 (BE-32 is the legacy format used for big
endian arm upto v4). All newer arm either were LE only or supported BE-8 and
little endian.

Martin


Re: CVS commit: src/sys/arch/aarch64/aarch64

2020-10-13 Thread Rin Okuyama

On 2020/10/13 19:57, Kamil Rytarowski wrote:

On 13.10.2020 09:04, Rin Okuyama wrote:

Module Name:src
Committed By:   rin
Date:   Tue Oct 13 07:04:49 UTC 2020

Modified Files:
src/sys/arch/aarch64/aarch64: exec_machdep.c

Log Message:
BE32 binaries are no longer supported for ARMv7 and later, and
therefore for aarch64eb.

Reject them with ENOEXEC, rather than causing illegal instruction
exceptions due to unexpected binary format.




Not supported in general or on NetBSD? Big Endian 32bit is supported on
Cavium ThunderX (at least on a selection of models if not all of them).



BE32 does not mean "big endian 32bit binary". It is an old binary format for
big endian 32-bit executables, that is supported up to ARMv6. ARMv7 and later
only support a new binary format, BE8.

BE8 binaries work without problem with COMPAT_NETBSD32 on aarch64eb.

Thanks,
rin


Re: CVS commit: src/sys/arch/aarch64/aarch64

2020-10-13 Thread Kamil Rytarowski
On 13.10.2020 09:04, Rin Okuyama wrote:
> Module Name:  src
> Committed By: rin
> Date: Tue Oct 13 07:04:49 UTC 2020
> 
> Modified Files:
>   src/sys/arch/aarch64/aarch64: exec_machdep.c
> 
> Log Message:
> BE32 binaries are no longer supported for ARMv7 and later, and
> therefore for aarch64eb.
> 
> Reject them with ENOEXEC, rather than causing illegal instruction
> exceptions due to unexpected binary format.
> 
> 

Not supported in general or on NetBSD? Big Endian 32bit is supported on
Cavium ThunderX (at least on a selection of models if not all of them).



signature.asc
Description: OpenPGP digital signature


Re: CVS commit: src/sys/arch/aarch64/aarch64

2020-10-06 Thread Rin Okuyama

It works fine now. Thank you for quick fix!!

rin

On 2020/10/06 15:28, Nick Hudson wrote:


On 06/10/2020 01:54, Rin Okuyama wrote:

Hi,

On 2020/10/01 1:35, Nick Hudson wrote:

Module Name:    src
Committed By:    skrll
Date:    Wed Sep 30 16:35:49 UTC 2020

Modified Files:
src/sys/arch/aarch64/aarch64: cpuswitch.S vectors.S

Log Message:
Move el[01]_trap_exit into vectors.S where the callers exist


To generate a diff of this commit:
cvs rdiff -u -r1.27 -r1.28 src/sys/arch/aarch64/aarch64/cpuswitch.S
cvs rdiff -u -r1.18 -r1.19 src/sys/arch/aarch64/aarch64/vectors.S

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.


This commit seems to break COMPAT_NETBSD32. On RPI3, earmv7hf binaries
get SIGSEGV:


Hopefully fixed now with the commit below. Please let me know if you
have any other problems.

Sorry for the breakage.

Nick


Module Name:    src
Committed By:    skrll
Date:    Tue Oct  6 06:26:46 UTC 2020

Modified Files:
 src/sys/arch/aarch64/aarch64: cpuswitch.S vectors.S

Log Message:
move #include "opt_compat_netbsd32.h" to where it's required


To generate a diff of this commit:
cvs rdiff -u -r1.28 -r1.29 src/sys/arch/aarch64/aarch64/cpuswitch.S
cvs rdiff -u -r1.19 -r1.20 src/sys/arch/aarch64/aarch64/vectors.S




Re: CVS commit: src/sys/arch/aarch64/aarch64

2020-10-06 Thread Nick Hudson



On 06/10/2020 01:54, Rin Okuyama wrote:

Hi,

On 2020/10/01 1:35, Nick Hudson wrote:

Module Name:    src
Committed By:    skrll
Date:    Wed Sep 30 16:35:49 UTC 2020

Modified Files:
src/sys/arch/aarch64/aarch64: cpuswitch.S vectors.S

Log Message:
Move el[01]_trap_exit into vectors.S where the callers exist


To generate a diff of this commit:
cvs rdiff -u -r1.27 -r1.28 src/sys/arch/aarch64/aarch64/cpuswitch.S
cvs rdiff -u -r1.18 -r1.19 src/sys/arch/aarch64/aarch64/vectors.S

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.


This commit seems to break COMPAT_NETBSD32. On RPI3, earmv7hf binaries
get SIGSEGV:


Hopefully fixed now with the commit below. Please let me know if you
have any other problems.

Sorry for the breakage.

Nick


Module Name:src
Committed By:   skrll
Date:   Tue Oct  6 06:26:46 UTC 2020

Modified Files:
src/sys/arch/aarch64/aarch64: cpuswitch.S vectors.S

Log Message:
move #include "opt_compat_netbsd32.h" to where it's required


To generate a diff of this commit:
cvs rdiff -u -r1.28 -r1.29 src/sys/arch/aarch64/aarch64/cpuswitch.S
cvs rdiff -u -r1.19 -r1.20 src/sys/arch/aarch64/aarch64/vectors.S




Re: CVS commit: src/sys/arch/aarch64/aarch64

2020-10-05 Thread Rin Okuyama

Hi,

On 2020/10/01 1:35, Nick Hudson wrote:

Module Name:src
Committed By:   skrll
Date:   Wed Sep 30 16:35:49 UTC 2020

Modified Files:
src/sys/arch/aarch64/aarch64: cpuswitch.S vectors.S

Log Message:
Move el[01]_trap_exit into vectors.S where the callers exist


To generate a diff of this commit:
cvs rdiff -u -r1.27 -r1.28 src/sys/arch/aarch64/aarch64/cpuswitch.S
cvs rdiff -u -r1.18 -r1.19 src/sys/arch/aarch64/aarch64/vectors.S

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.


This commit seems to break COMPAT_NETBSD32. On RPI3, earmv7hf binaries
get SIGSEGV:

---
# uname -a
NetBSD  9.99.73 NetBSD 9.99.73 (GENERIC64) #33: Mon Oct  5 23:26:29 JST 2020  
rin@latipes:/sys/arch/evbarm/compile/GENERIC64 evbarm
# file /emul/netbsd32/bin/sh
/emul/netbsd32/bin/sh: ELF 32-bit LSB pie executable, ARM, EABI5 version 1 
(SYSV), dynamically linked, interpreter /libexec/ld.elf_so, for NetBSD 9.99.73, 
compiled for: earmv7hf, not stripped
# /emul/netbsd32/bin/sh
[1]   Segmentation fault (core dumped) /emul/netbsd32/bin/sh
# ktrace /emul/netbsd32/bin/sh
[1]   Segmentation fault (core dumped) ktrace /emul/netbsd32/bin/sh
# kdump | tail
   171171 sh   CALL  netbsd32_break(0xb74ffdc)
   171171 sh   RET   netbsd32_break 0
   171171 sh   CALL  netbsd32___clock_gettime50(3,0xfff997f8)
   171171 sh   RET   netbsd32___clock_gettime50 0
   171171 sh   CALL  netbsd32___clock_gettime50(3,0xfff997f8)
   171171 sh   RET   netbsd32___clock_gettime50 0
   171171 sh   CALL  netbsd32___clock_gettime50(3,0xfff99810)
   171171 sh   RET   netbsd32___clock_gettime50 0
   171171 sh   PSIG  SIGSEGV SIG_DFL: code=SEGV_MAPERR, addr=0x8, 
trap=-1845493754)
   171171 sh   NAMI  "sh.core"
---

Full kdump is provided here:

http://www.netbsd.org/~rin/aarch64_netbsd32_kdump_20201006.txt

By reverting this commit, arm32 binaries become working again.
Can you take a look please?

Thanks,
rin


Re: CVS commit: src/sys/arch/aarch64

2020-10-01 Thread Ryo Shimizu
>> Index: src/sys/arch/aarch64/include/cpu.h
>> diff -u src/sys/arch/aarch64/include/cpu.h:1.27 src/sys/arch/aarch64/inc=
>lude/cpu.h:1.28
>> --- src/sys/arch/aarch64/include/cpu.h:1.27  Mon Sep 14 10:06:35 2020
>> +++ src/sys/arch/aarch64/include/cpu.h   Thu Oct  1 06:40:16 2020
>> @@ -1,4 +1,4 @@
>> -/* $NetBSD: cpu.h,v 1.27 2020/09/14 10:06:35 ryo Exp $ */
>> +/* $NetBSD: cpu.h,v 1.28 2020/10/01 06:40:16 ryo Exp $ */
>>
>>   /*-
>>* Copyright (c) 2014, 2020 The NetBSD Foundation, Inc.
>> @@ -156,7 +156,7 @@ void cpu_hatch(struct cpu_info *);
>>   extern struct cpu_info *cpu_info[];
>>   extern struct cpu_info cpu_info_store[];
>>
>> -#define CPU_INFO_ITERATOR   cpuid_t
>> +#define CPU_INFO_ITERATOR   int
>>   #if defined(MULTIPROCESSOR) || defined(_MODULE)
>>   #define cpu_number()   (curcpu()->ci_index)
>>   #define CPU_IS_PRIMARY(ci) ((ci)->ci_index =3D=3D 0)
>>
>
>I think this is the wrong way to go ultimately
>
>unsigned int at least

In most arch, CPU_INFO_ITERATOR is an int.

  # grep CPU_INFO_ITERATOR /usr/src/sys/arch/*/include/cpu.h
  /usr/src/sys/arch/aarch64/include/cpu.h:#define CPU_INFO_ITERATOR int
  /usr/src/sys/arch/alpha/include/cpu.h:#define CPU_INFO_ITERATOR   
int __unused
  /usr/src/sys/arch/arm/include/cpu.h:#define CPU_INFO_ITERATOR int
  /usr/src/sys/arch/hppa/include/cpu.h:#define  CPU_INFO_ITERATOR   
int
  /usr/src/sys/arch/ia64/include/cpu.h:#define  CPU_INFO_ITERATOR   
int __unused
  /usr/src/sys/arch/mips/include/cpu.h:#define  CPU_INFO_ITERATOR   
int
  /usr/src/sys/arch/mips/include/cpu.h:#define  CPU_INFO_ITERATOR   
int __unused
  /usr/src/sys/arch/or1k/include/cpu.h:#define CPU_INFO_ITERATORcpuid_t
  /usr/src/sys/arch/powerpc/include/cpu.h:#define CPU_INFO_ITERATOR int
  /usr/src/sys/arch/powerpc/include/cpu.h:#define CPU_INFO_ITERATOR int
  /usr/src/sys/arch/riscv/include/cpu.h:#define CPU_INFO_ITERATOR   cpuid_t
  /usr/src/sys/arch/sparc64/include/cpu.h:#define CPU_INFO_ITERATOR 
int __unused
  /usr/src/sys/arch/vax/include/cpu.h:#define   CPU_INFO_ITERATOR   int 
__unused
  /usr/src/sys/arch/x86/include/cpu.h:#define   CPU_INFO_ITERATOR   
int __unused

and, it is compared to "int ncpu", so it is matched to the type of 'ncpu'. 
(otherwise, clang warns)

-- 
ryo shimizu


Re: CVS commit: src/sys/arch/aarch64

2020-10-01 Thread Nick Hudson

On 01/10/2020 07:40, Ryo Shimizu wrote:

Module Name:src
Committed By:   ryo
Date:   Thu Oct  1 06:40:16 UTC 2020

Modified Files:
src/sys/arch/aarch64/aarch64: procfs_machdep.c
src/sys/arch/aarch64/include: cpu.h

Log Message:
fix build error with LLVM

[...]


Index: src/sys/arch/aarch64/include/cpu.h
diff -u src/sys/arch/aarch64/include/cpu.h:1.27 
src/sys/arch/aarch64/include/cpu.h:1.28
--- src/sys/arch/aarch64/include/cpu.h:1.27 Mon Sep 14 10:06:35 2020
+++ src/sys/arch/aarch64/include/cpu.h  Thu Oct  1 06:40:16 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.h,v 1.27 2020/09/14 10:06:35 ryo Exp $ */
+/* $NetBSD: cpu.h,v 1.28 2020/10/01 06:40:16 ryo Exp $ */

  /*-
   * Copyright (c) 2014, 2020 The NetBSD Foundation, Inc.
@@ -156,7 +156,7 @@ voidcpu_hatch(struct cpu_info *);
  extern struct cpu_info *cpu_info[];
  extern struct cpu_info cpu_info_store[];

-#define CPU_INFO_ITERATOR  cpuid_t
+#define CPU_INFO_ITERATOR  int
  #if defined(MULTIPROCESSOR) || defined(_MODULE)
  #define cpu_number()  (curcpu()->ci_index)
  #define CPU_IS_PRIMARY(ci)((ci)->ci_index == 0)



I think this is the wrong way to go ultimately

unsigned int at least

Nick


Re: CVS commit: src/sys/arch/aarch64/aarch64

2020-09-24 Thread Ryo Shimizu


>On 24/09/2020 10:04, Ryo Shimizu wrote:
>> Module Name: src
>> Committed By:ryo
>> Date:Thu Sep 24 09:04:38 UTC 2020
>>
>> Modified Files:
>>  src/sys/arch/aarch64/aarch64: bus_space_asm_generic.S
>>
>> Log Message:
>> fix bugs in *_bs_rm_8_swap(). it was only reading 4 bytes, not 8 bytes.
>
>I think there's another one that needs fixing...
>
>Nick

>Index: sys/arch/aarch64/aarch64/bus_space_asm_generic.S
>===
>RCS file: /cvsroot/src/sys/arch/aarch64/aarch64/bus_space_asm_generic.S,v
>retrieving revision 1.3
>diff -u -p -r1.3 bus_space_asm_generic.S
>--- sys/arch/aarch64/aarch64/bus_space_asm_generic.S   24 Sep 2020 09:04:38 
>-  1.3
>+++ sys/arch/aarch64/aarch64/bus_space_asm_generic.S   24 Sep 2020 10:11:18 
>-
>@@ -225,7 +225,7 @@ ENTRY_NP(\funcname\()_bs_rm_4_swap)
>   ldr w8, [x0, #BS_STRIDE]
>   lsl x8, x2, x8  /* offset <<= tag->bs_stride */
> 1:
>-  ldrhw9, [x1, x8]
>+  ldr w9, [x1, x8]
>   subsx4, x4, #1  /* count-- */
>   rev w9, w9
>   str w9, [x3], #4

Ahhh, right. I fixed this too.
Thanks again.

-- 
ryo shimizu


Re: CVS commit: src/sys/arch/aarch64/aarch64

2020-09-24 Thread Nick Hudson

On 24/09/2020 10:04, Ryo Shimizu wrote:

Module Name:src
Committed By:   ryo
Date:   Thu Sep 24 09:04:38 UTC 2020

Modified Files:
src/sys/arch/aarch64/aarch64: bus_space_asm_generic.S

Log Message:
fix bugs in *_bs_rm_8_swap(). it was only reading 4 bytes, not 8 bytes.


I think there's another one that needs fixing...

Nick

Index: sys/arch/aarch64/aarch64/bus_space_asm_generic.S
===
RCS file: /cvsroot/src/sys/arch/aarch64/aarch64/bus_space_asm_generic.S,v
retrieving revision 1.3
diff -u -p -r1.3 bus_space_asm_generic.S
--- sys/arch/aarch64/aarch64/bus_space_asm_generic.S	24 Sep 2020 09:04:38 -	1.3
+++ sys/arch/aarch64/aarch64/bus_space_asm_generic.S	24 Sep 2020 10:11:18 -
@@ -225,7 +225,7 @@ ENTRY_NP(\funcname\()_bs_rm_4_swap)
 	ldr	w8, [x0, #BS_STRIDE]
 	lsl	x8, x2, x8	/* offset <<= tag->bs_stride */
 1:
-	ldrh	w9, [x1, x8]
+	ldr	w9, [x1, x8]
 	subs	x4, x4, #1	/* count-- */
 	rev	w9, w9
 	str	w9, [x3], #4



Re: CVS commit: src/sys/arch/aarch64/aarch64

2020-07-02 Thread Jared McNeill
I think this will have issues on some big.LITTLE configurations 
like Rockchip RK3399.


In the RK3399 case cpu[0-3] is VIPT I$ and cpu[4-5] is PIPT I$. Boot 
order of secondaries is not guaranteed so it is possible to get different 
values of aarch64_cache_vindexsize from one boot to the next.


Jared


On Thu, 2 Jul 2020, Rin Okuyama wrote:


Module Name:src
Committed By:   rin
Date:   Thu Jul  2 12:59:31 UTC 2020

Modified Files:
src/sys/arch/aarch64/aarch64: pmap.c

Log Message:
Set uvmexp.ncolors appropriately, which is required for some CPU
models with VIPT icache.

Otherwise, alias in virtual address results in inconsistent results,
at least for applications that rewrite text of other process, e.g.,
GDB for arm32.

Also, this hopefully fixes other unexpected failures due to alias.

Confirmed that there's no observable regression in performance;
difference in ``time make -j8'' for GENERIC64 kernel on BCM2837
with and without setting uvmexp.ncolors is within 0.1%.

Thanks to ryo@ for discussion.


To generate a diff of this commit:
cvs rdiff -u -r1.80 -r1.81 src/sys/arch/aarch64/aarch64/pmap.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.




Re: CVS commit: src/sys/arch/aarch64

2020-05-23 Thread Ryo Shimizu


>> Has any consideration be given to perhaps creating a new MACHINE_ARCH for 
>> this, or somehow otherwise decorating the ELF files to indicate their 
>> exec-ability?
>
>I am under the impression that PAC was designed to be forewards
>compatible, so older CPUs can execute code with this annotation. I don't
>whether it works in practice though.

Yes. That's right.
Even binaries compiled with "gcc -msign-return-address=all" work fine on
ARMv8.0-v8.2 CPUs. This is because the "paciasp" and "autiasp" instructions are
treated as "nop" on ARMv8.0-v8.2 CPUs.

Therefore, I don't think it's necessary to add detailed attributes to the ELF
header.

So, even if we default the PAC option right now, we won't have any problems.
But we might as well enable PAC by default after real ARMv8.3 hardware becomes
available easily.
(now tested on "qemu-system-aarch64 -cpu max")

-- 
ryo shimizu


Re: CVS commit: src/sys/arch/aarch64

2020-05-23 Thread maya
On Sat, May 23, 2020 at 02:13:46PM -0700, Jason Thorpe wrote:
> 
> > On May 23, 2020, at 11:08 AM, Ryo Shimizu  wrote:
> > 
> > Module Name:src
> > Committed By:   ryo
> > Date:   Sat May 23 18:08:59 UTC 2020
> > 
> > Modified Files:
> > src/sys/arch/aarch64/aarch64: cpufunc.c cpuswitch.S exec_machdep.c
> > genassym.cf netbsd32_machdep.c vectors.S vm_machdep.c
> > src/sys/arch/aarch64/include: armreg.h machdep.h proc.h
> > 
> > Log Message:
> > Not only the kernel thread, but also the userland PAC keys
> > (APIA,APIB,APDA,APDB,APGA) are now randomly initialized at exec, and 
> > switched
> > when context switch.
> > userland programs are able to perform pointer authentication on ARMv8.3+PAC 
> > cpu.
> 
> Has any consideration be given to perhaps creating a new MACHINE_ARCH for 
> this, or somehow otherwise decorating the ELF files to indicate their 
> exec-ability?

I am under the impression that PAC was designed to be forewards
compatible, so older CPUs can execute code with this annotation. I don't
whether it works in practice though.


Re: CVS commit: src/sys/arch/aarch64

2020-05-23 Thread Jason Thorpe


> On May 23, 2020, at 11:08 AM, Ryo Shimizu  wrote:
> 
> Module Name:  src
> Committed By: ryo
> Date: Sat May 23 18:08:59 UTC 2020
> 
> Modified Files:
>   src/sys/arch/aarch64/aarch64: cpufunc.c cpuswitch.S exec_machdep.c
>   genassym.cf netbsd32_machdep.c vectors.S vm_machdep.c
>   src/sys/arch/aarch64/include: armreg.h machdep.h proc.h
> 
> Log Message:
> Not only the kernel thread, but also the userland PAC keys
> (APIA,APIB,APDA,APDB,APGA) are now randomly initialized at exec, and switched
> when context switch.
> userland programs are able to perform pointer authentication on ARMv8.3+PAC 
> cpu.

Has any consideration be given to perhaps creating a new MACHINE_ARCH for this, 
or somehow otherwise decorating the ELF files to indicate their exec-ability?

> 
> reviewd by maxv@, thanks.
> 
> 
> To generate a diff of this commit:
> cvs rdiff -u -r1.18 -r1.19 src/sys/arch/aarch64/aarch64/cpufunc.c
> cvs rdiff -u -r1.20 -r1.21 src/sys/arch/aarch64/aarch64/cpuswitch.S
> cvs rdiff -u -r1.6 -r1.7 src/sys/arch/aarch64/aarch64/exec_machdep.c
> cvs rdiff -u -r1.24 -r1.25 src/sys/arch/aarch64/aarch64/genassym.cf
> cvs rdiff -u -r1.12 -r1.13 src/sys/arch/aarch64/aarch64/netbsd32_machdep.c
> cvs rdiff -u -r1.16 -r1.17 src/sys/arch/aarch64/aarch64/vectors.S
> cvs rdiff -u -r1.7 -r1.8 src/sys/arch/aarch64/aarch64/vm_machdep.c
> cvs rdiff -u -r1.44 -r1.45 src/sys/arch/aarch64/include/armreg.h
> cvs rdiff -u -r1.10 -r1.11 src/sys/arch/aarch64/include/machdep.h
> cvs rdiff -u -r1.6 -r1.7 src/sys/arch/aarch64/include/proc.h
> 
> Please note that diffs are not public domain; they are subject to the
> copyright notices on the relevant files.
> 

-- thorpej



Re: CVS commit: src/sys/arch/aarch64

2020-01-30 Thread Maxime Villard
Le 28/01/2020 à 19:39, Nick Hudson a écrit :
> On 28/01/2020 17:47, Maxime Villard wrote:
>> @@ -460,8 +460,7 @@ cpu_setup_id(struct cpu_info *ci)
>>
>>   id->ac_aa64mmfr0 = reg_id_aa64mmfr0_el1_read();
>>   id->ac_aa64mmfr1 = reg_id_aa64mmfr1_el1_read();
>> -    /* Only in ARMv8.2. */
>> -    id->ac_aa64mmfr2 = 0 /* reg_id_aa64mmfr2_el1_read() */;
>> +    id->ac_aa64mmfr2 = reg_id_aa64mmfr2_el1_read();
>>
>>   id->ac_mvfr0 = reg_mvfr0_el1_read();
>>   id->ac_mvfr1 = reg_mvfr1_el1_read();
> 
> I didn't ok this bit...

Verily you did; I sent you this patch as-is two weeks ago.

> This needs to be conditional on the CPU we're running on.

ID_AA64MMFR2_EL1 is res0 on < ARMv8.2, reading it is therefore not a
problem.


Re: CVS commit: src/sys/arch/aarch64

2020-01-30 Thread Nick Hudson




On 30/01/2020 10:04, Maxime Villard wrote:

Le 28/01/2020 à 19:39, Nick Hudson a écrit :

On 28/01/2020 17:47, Maxime Villard wrote:

@@ -460,8 +460,7 @@ cpu_setup_id(struct cpu_info *ci)

   id->ac_aa64mmfr0 = reg_id_aa64mmfr0_el1_read();
   id->ac_aa64mmfr1 = reg_id_aa64mmfr1_el1_read();
-    /* Only in ARMv8.2. */
-    id->ac_aa64mmfr2 = 0 /* reg_id_aa64mmfr2_el1_read() */;
+    id->ac_aa64mmfr2 = reg_id_aa64mmfr2_el1_read();

   id->ac_mvfr0 = reg_mvfr0_el1_read();
   id->ac_mvfr1 = reg_mvfr1_el1_read();


I didn't ok this bit...


Verily you did; I sent you this patch as-is two weeks ago.


OK, well, I don't remember it :) I'm must be getting old.




This needs to be conditional on the CPU we're running on.


ID_AA64MMFR2_EL1 is res0 on < ARMv8.2, reading it is therefore not a
problem.


OK.

Thanks,

Nick


Re: CVS commit: src/sys/arch/aarch64

2020-01-28 Thread Nick Hudson

On 28/01/2020 17:47, Maxime Villard wrote:

@@ -460,8 +460,7 @@ cpu_setup_id(struct cpu_info *ci)

id->ac_aa64mmfr0 = reg_id_aa64mmfr0_el1_read();
id->ac_aa64mmfr1 = reg_id_aa64mmfr1_el1_read();
-   /* Only in ARMv8.2. */
-   id->ac_aa64mmfr2 = 0 /* reg_id_aa64mmfr2_el1_read() */;
+   id->ac_aa64mmfr2 = reg_id_aa64mmfr2_el1_read();

id->ac_mvfr0 = reg_mvfr0_el1_read();
id->ac_mvfr1 = reg_mvfr1_el1_read();


I didn't ok this bit...

This needs to be conditional on the CPU we're running on.

Thanks,
Nick


CVS commit: src/sys/arch/aarch64/aarch64

2019-11-24 Thread Rin Okuyama
Module Name:src
Committed By:   rin
Date:   Sun Nov 24 11:45:00 UTC 2019

Modified Files:
src/sys/arch/aarch64/aarch64: exec_machdep.c

Log Message:
part of PR port-arm/54702

Make sure that md_march32 and ep_machine_arch have same size.

XXX
pullup to netbsd-9


To generate a diff of this commit:
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/aarch64/aarch64/exec_machdep.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/aarch64/aarch64

2019-11-24 Thread Rin Okuyama
Module Name:src
Committed By:   rin
Date:   Sun Nov 24 11:45:00 UTC 2019

Modified Files:
src/sys/arch/aarch64/aarch64: exec_machdep.c

Log Message:
part of PR port-arm/54702

Make sure that md_march32 and ep_machine_arch have same size.

XXX
pullup to netbsd-9


To generate a diff of this commit:
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/aarch64/aarch64/exec_machdep.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/aarch64/aarch64/exec_machdep.c
diff -u src/sys/arch/aarch64/aarch64/exec_machdep.c:1.5 src/sys/arch/aarch64/aarch64/exec_machdep.c:1.6
--- src/sys/arch/aarch64/aarch64/exec_machdep.c:1.5	Sun Nov 24 04:08:36 2019
+++ src/sys/arch/aarch64/aarch64/exec_machdep.c	Sun Nov 24 11:45:00 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: exec_machdep.c,v 1.5 2019/11/24 04:08:36 rin Exp $ */
+/* $NetBSD: exec_machdep.c,v 1.6 2019/11/24 11:45:00 rin Exp $ */
 
 /*-
  * Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -31,7 +31,7 @@
 
 #include 
 
-__KERNEL_RCSID(1, "$NetBSD: exec_machdep.c,v 1.5 2019/11/24 04:08:36 rin Exp $");
+__KERNEL_RCSID(1, "$NetBSD: exec_machdep.c,v 1.6 2019/11/24 11:45:00 rin Exp $");
 
 #include "opt_compat_netbsd.h"
 #include "opt_compat_netbsd32.h"
@@ -86,6 +86,8 @@ aarch64_netbsd_elf32_probe(struct lwp *l
 	/*
 	 * Copy (if any) the machine_arch of the executable to the proc.
 	 */
+	CTASSERT(sizeof(l->l_proc->p_md.md_march32) ==
+	sizeof(epp->ep_machine_arch));
 	if (epp->ep_machine_arch[0] != 0)
 		strlcpy(l->l_proc->p_md.md_march32, epp->ep_machine_arch,
 		sizeof(l->l_proc->p_md.md_march32));



CVS commit: src/sys/arch/aarch64/include

2019-11-24 Thread Rin Okuyama
Module Name:src
Committed By:   rin
Date:   Sun Nov 24 11:28:40 UTC 2019

Modified Files:
src/sys/arch/aarch64/include: proc.h

Log Message:
part of PR port-arm/54702

Having md_march32 unconditionally in struct mdproc, in order to
make libkvm happy.

XXX
pullup to netbsd-9


To generate a diff of this commit:
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/aarch64/include/proc.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/aarch64/include/proc.h
diff -u src/sys/arch/aarch64/include/proc.h:1.4 src/sys/arch/aarch64/include/proc.h:1.5
--- src/sys/arch/aarch64/include/proc.h:1.4	Sun Nov 24 04:08:36 2019
+++ src/sys/arch/aarch64/include/proc.h	Sun Nov 24 11:28:40 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: proc.h,v 1.4 2019/11/24 04:08:36 rin Exp $ */
+/* $NetBSD: proc.h,v 1.5 2019/11/24 11:28:40 rin Exp $ */
 
 /*-
  * Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -47,9 +47,7 @@ struct mdlwp {
 
 struct mdproc {
 	void (*md_syscall)(struct trapframe *);
-#ifdef COMPAT_NETBSD32
 	char md_march32[12];	/* machine arch of executable */
-#endif
 };
 
 #ifdef COMPAT_NETBSD32



CVS commit: src/sys/arch/aarch64/include

2019-11-24 Thread Rin Okuyama
Module Name:src
Committed By:   rin
Date:   Sun Nov 24 11:28:40 UTC 2019

Modified Files:
src/sys/arch/aarch64/include: proc.h

Log Message:
part of PR port-arm/54702

Having md_march32 unconditionally in struct mdproc, in order to
make libkvm happy.

XXX
pullup to netbsd-9


To generate a diff of this commit:
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/aarch64/include/proc.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/aarch64

2019-11-23 Thread Rin Okuyama
Module Name:src
Committed By:   rin
Date:   Sun Nov 24 04:08:36 UTC 2019

Modified Files:
src/sys/arch/aarch64/aarch64: exec_machdep.c netbsd32_machdep.c trap.c
src/sys/arch/aarch64/include: netbsd32_machdep.h param.h proc.h

Log Message:
PR port-arm/54702

Add support for earmv6hf binaries on COMPAT_NETBSD32 for aarch64:

- Emulate ARMv6 instructions with cache operations register (c7), that
  are deprecated since ARMv7, and disabled on ARMv8 with LP64 kernel.

- ep_machine_arch (default: earmv7hf) is copied from executables, as we
  do for mips64. "uname -p" reports earmv6hf if compiled for earmv6hf;
  configure scripts etc can determine the appropriate architecture.

Many thanks to ryo@ for helping me to add support of Thumb-mode,
as well as providing exhaustive test cases:

  https://github.com/ryo/mcr_test/

We've confirmed:

- Emulation works in Thumb-mode.
- T32 16-bit length illegal instruction results in SIGILL, even if
  it is located nearby a boundary b/w mapped and unmapped pages.
- T32 32-bit instruction results in SIGSEGV if it is located across
  a boundary b/w mapped and unmapped pages.

XXX
pullup to netbsd-9


To generate a diff of this commit:
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/aarch64/aarch64/exec_machdep.c
cvs rdiff -u -r1.8 -r1.9 src/sys/arch/aarch64/aarch64/netbsd32_machdep.c
cvs rdiff -u -r1.20 -r1.21 src/sys/arch/aarch64/aarch64/trap.c
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/aarch64/include/netbsd32_machdep.h
cvs rdiff -u -r1.12 -r1.13 src/sys/arch/aarch64/include/param.h
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/aarch64/include/proc.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/aarch64/aarch64/exec_machdep.c
diff -u src/sys/arch/aarch64/aarch64/exec_machdep.c:1.4 src/sys/arch/aarch64/aarch64/exec_machdep.c:1.5
--- src/sys/arch/aarch64/aarch64/exec_machdep.c:1.4	Wed Nov 28 08:12:15 2018
+++ src/sys/arch/aarch64/aarch64/exec_machdep.c	Sun Nov 24 04:08:36 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: exec_machdep.c,v 1.4 2018/11/28 08:12:15 ryo Exp $ */
+/* $NetBSD: exec_machdep.c,v 1.5 2019/11/24 04:08:36 rin Exp $ */
 
 /*-
  * Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -31,7 +31,7 @@
 
 #include 
 
-__KERNEL_RCSID(1, "$NetBSD: exec_machdep.c,v 1.4 2018/11/28 08:12:15 ryo Exp $");
+__KERNEL_RCSID(1, "$NetBSD: exec_machdep.c,v 1.5 2019/11/24 04:08:36 rin Exp $");
 
 #include "opt_compat_netbsd.h"
 #include "opt_compat_netbsd32.h"
@@ -83,6 +83,13 @@ aarch64_netbsd_elf32_probe(struct lwp *l
 	ID_AA64PFR0_EL1_EL0_64_32)
 		return ENOEXEC;
 
+	/*
+	 * Copy (if any) the machine_arch of the executable to the proc.
+	 */
+	if (epp->ep_machine_arch[0] != 0)
+		strlcpy(l->l_proc->p_md.md_march32, epp->ep_machine_arch,
+		sizeof(l->l_proc->p_md.md_march32));
+
 	return 0;
 }
 #endif

Index: src/sys/arch/aarch64/aarch64/netbsd32_machdep.c
diff -u src/sys/arch/aarch64/aarch64/netbsd32_machdep.c:1.8 src/sys/arch/aarch64/aarch64/netbsd32_machdep.c:1.9
--- src/sys/arch/aarch64/aarch64/netbsd32_machdep.c:1.8	Wed Nov 20 19:37:51 2019
+++ src/sys/arch/aarch64/aarch64/netbsd32_machdep.c	Sun Nov 24 04:08:36 2019
@@ -1,4 +1,4 @@
-/*	$NetBSD: netbsd32_machdep.c,v 1.8 2019/11/20 19:37:51 pgoyette Exp $	*/
+/*	$NetBSD: netbsd32_machdep.c,v 1.9 2019/11/24 04:08:36 rin Exp $	*/
 
 /*
  * Copyright (c) 2018 Ryo Shimizu 
@@ -27,7 +27,7 @@
  */
 
 #include 
-__KERNEL_RCSID(0, "$NetBSD: netbsd32_machdep.c,v 1.8 2019/11/20 19:37:51 pgoyette Exp $");
+__KERNEL_RCSID(0, "$NetBSD: netbsd32_machdep.c,v 1.9 2019/11/24 04:08:36 rin Exp $");
 
 #if defined(_KERNEL_OPT)
 #include "opt_compat_netbsd.h"
@@ -55,11 +55,7 @@ __KERNEL_RCSID(0, "$NetBSD: netbsd32_mac
 #include 
 
 const char machine32[] = MACHINE;
-#ifdef __AARCH64EB__
-const char machine_arch32[] = "earmv7hfeb";
-#else
-const char machine_arch32[] = "earmv7hf";
-#endif
+const char machine_arch32[] = MACHINE32_ARCH;
 
 void
 netbsd32_setregs(struct lwp *l, struct exec_package *pack, vaddr_t stack)

Index: src/sys/arch/aarch64/aarch64/trap.c
diff -u src/sys/arch/aarch64/aarch64/trap.c:1.20 src/sys/arch/aarch64/aarch64/trap.c:1.21
--- src/sys/arch/aarch64/aarch64/trap.c:1.20	Thu Nov 21 19:23:58 2019
+++ src/sys/arch/aarch64/aarch64/trap.c	Sun Nov 24 04:08:36 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: trap.c,v 1.20 2019/11/21 19:23:58 ad Exp $ */
+/* $NetBSD: trap.c,v 1.21 2019/11/24 04:08:36 rin Exp $ */
 
 /*-
  * Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -31,7 +31,7 @@
 
 #include 
 
-__KERNEL_RCSID(1, "$NetBSD: trap.c,v 1.20 2019/11/21 19:23:58 ad Exp $");
+__KERNEL_RCSID(1, "$NetBSD: trap.c,v 1.21 2019/11/24 04:08:36 rin Exp $");
 
 #include "opt_arm_intr_impl.h"
 #include "opt_compat_netbsd32.h"
@@ -321,6 +321,103 @@ interrupt(struct trapframe *tf)
 	cpu_dosoftints();
 }
 
+#ifdef COMPAT_NETBSD32
+
+/*
+ * 32-bit length Thumb instruction. See ARMv7 DDI0406A A6.3.
+ */
+#define THUMB_32BIT(hi) (((hi) & 0xe000) == 0xe000 && 

CVS commit: src/sys/arch/aarch64

2019-11-23 Thread Rin Okuyama
Module Name:src
Committed By:   rin
Date:   Sun Nov 24 04:08:36 UTC 2019

Modified Files:
src/sys/arch/aarch64/aarch64: exec_machdep.c netbsd32_machdep.c trap.c
src/sys/arch/aarch64/include: netbsd32_machdep.h param.h proc.h

Log Message:
PR port-arm/54702

Add support for earmv6hf binaries on COMPAT_NETBSD32 for aarch64:

- Emulate ARMv6 instructions with cache operations register (c7), that
  are deprecated since ARMv7, and disabled on ARMv8 with LP64 kernel.

- ep_machine_arch (default: earmv7hf) is copied from executables, as we
  do for mips64. "uname -p" reports earmv6hf if compiled for earmv6hf;
  configure scripts etc can determine the appropriate architecture.

Many thanks to ryo@ for helping me to add support of Thumb-mode,
as well as providing exhaustive test cases:

  https://github.com/ryo/mcr_test/

We've confirmed:

- Emulation works in Thumb-mode.
- T32 16-bit length illegal instruction results in SIGILL, even if
  it is located nearby a boundary b/w mapped and unmapped pages.
- T32 32-bit instruction results in SIGSEGV if it is located across
  a boundary b/w mapped and unmapped pages.

XXX
pullup to netbsd-9


To generate a diff of this commit:
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/aarch64/aarch64/exec_machdep.c
cvs rdiff -u -r1.8 -r1.9 src/sys/arch/aarch64/aarch64/netbsd32_machdep.c
cvs rdiff -u -r1.20 -r1.21 src/sys/arch/aarch64/aarch64/trap.c
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/aarch64/include/netbsd32_machdep.h
cvs rdiff -u -r1.12 -r1.13 src/sys/arch/aarch64/include/param.h
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/aarch64/include/proc.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/aarch64

2019-11-21 Thread Michael van Elst
Module Name:src
Committed By:   mlelstv
Date:   Fri Nov 22 05:21:19 UTC 2019

Modified Files:
src/sys/arch/aarch64/aarch64: cpu.c cpufunc.c locore.S
src/sys/arch/aarch64/include: cpufunc.h

Log Message:
Make cache operations available early.


To generate a diff of this commit:
cvs rdiff -u -r1.25 -r1.26 src/sys/arch/aarch64/aarch64/cpu.c
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/aarch64/aarch64/cpufunc.c
cvs rdiff -u -r1.44 -r1.45 src/sys/arch/aarch64/aarch64/locore.S
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/aarch64/include/cpufunc.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/aarch64

2019-11-21 Thread Michael van Elst
Module Name:src
Committed By:   mlelstv
Date:   Fri Nov 22 05:21:19 UTC 2019

Modified Files:
src/sys/arch/aarch64/aarch64: cpu.c cpufunc.c locore.S
src/sys/arch/aarch64/include: cpufunc.h

Log Message:
Make cache operations available early.


To generate a diff of this commit:
cvs rdiff -u -r1.25 -r1.26 src/sys/arch/aarch64/aarch64/cpu.c
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/aarch64/aarch64/cpufunc.c
cvs rdiff -u -r1.44 -r1.45 src/sys/arch/aarch64/aarch64/locore.S
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/aarch64/include/cpufunc.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/aarch64/aarch64/cpu.c
diff -u src/sys/arch/aarch64/aarch64/cpu.c:1.25 src/sys/arch/aarch64/aarch64/cpu.c:1.26
--- src/sys/arch/aarch64/aarch64/cpu.c:1.25	Sun Oct 20 14:03:51 2019
+++ src/sys/arch/aarch64/aarch64/cpu.c	Fri Nov 22 05:21:19 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.c,v 1.25 2019/10/20 14:03:51 jmcneill Exp $ */
+/* $NetBSD: cpu.c,v 1.26 2019/11/22 05:21:19 mlelstv Exp $ */
 
 /*
  * Copyright (c) 2017 Ryo Shimizu 
@@ -27,7 +27,7 @@
  */
 
 #include 
-__KERNEL_RCSID(1, "$NetBSD: cpu.c,v 1.25 2019/10/20 14:03:51 jmcneill Exp $");
+__KERNEL_RCSID(1, "$NetBSD: cpu.c,v 1.26 2019/11/22 05:21:19 mlelstv Exp $");
 
 #include "locators.h"
 #include "opt_arm_debug.h"
@@ -102,7 +102,6 @@ cpu_attach(device_t dv, cpuid_t id)
 {
 	struct cpu_info *ci;
 	const int unit = device_unit(dv);
-	uint64_t mpidr;
 
 	if (unit == 0) {
 		ci = curcpu();
@@ -142,19 +141,11 @@ cpu_attach(device_t dv, cpuid_t id)
 #endif /* MULTIPROCESSOR */
 	}
 
-	mpidr = ci->ci_id.ac_mpidr;
-	if (mpidr & MPIDR_MT) {
-		ci->ci_smt_id = __SHIFTOUT(mpidr, MPIDR_AFF0);
-		ci->ci_core_id = __SHIFTOUT(mpidr, MPIDR_AFF1);
-		ci->ci_package_id = __SHIFTOUT(mpidr, MPIDR_AFF2);
-	} else {
-		ci->ci_core_id = __SHIFTOUT(mpidr, MPIDR_AFF0);
-		ci->ci_package_id = __SHIFTOUT(mpidr, MPIDR_AFF1);
-	}
-
 	ci->ci_dev = dv;
 	dv->dv_private = ci;
 
+	aarch64_gettopology(ci, ci->ci_id.ac_mpidr);
+
 	cpu_identify(ci->ci_dev, ci);
 #ifdef MULTIPROCESSOR
 	if (unit != 0) {
@@ -167,7 +158,10 @@ cpu_attach(device_t dv, cpuid_t id)
 	fpu_attach(ci);
 
 	cpu_identify1(dv, ci);
-	aarch64_getcacheinfo();
+#if 0
+	/* already done in locore */
+	aarch64_getcacheinfo(unit); 
+#endif
 	aarch64_printcacheinfo(dv);
 	cpu_identify2(dv, ci);
 
@@ -539,7 +533,7 @@ cpu_hatch(struct cpu_info *ci)
 	fpu_attach(ci);
 
 	cpu_identify1(ci->ci_dev, ci);
-	aarch64_getcacheinfo();
+	aarch64_getcacheinfo(device_unit(ci->ci_dev));
 	aarch64_printcacheinfo(ci->ci_dev);
 	cpu_identify2(ci->ci_dev, ci);
 

Index: src/sys/arch/aarch64/aarch64/cpufunc.c
diff -u src/sys/arch/aarch64/aarch64/cpufunc.c:1.7 src/sys/arch/aarch64/aarch64/cpufunc.c:1.8
--- src/sys/arch/aarch64/aarch64/cpufunc.c:1.7	Tue Oct  1 18:00:07 2019
+++ src/sys/arch/aarch64/aarch64/cpufunc.c	Fri Nov 22 05:21:19 2019
@@ -1,4 +1,4 @@
-/*	$NetBSD: cpufunc.c,v 1.7 2019/10/01 18:00:07 chs Exp $	*/
+/*	$NetBSD: cpufunc.c,v 1.8 2019/11/22 05:21:19 mlelstv Exp $	*/
 
 /*
  * Copyright (c) 2017 Ryo Shimizu 
@@ -29,7 +29,7 @@
 #include "opt_multiprocessor.h"
 
 #include 
-__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.7 2019/10/01 18:00:07 chs Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.8 2019/11/22 05:21:19 mlelstv Exp $");
 
 #include 
 #include 
@@ -49,6 +49,7 @@ u_int aarch64_cache_prefer_mask;
 /* cache info per cluster. the same cluster has the same cache configuration? */
 #define MAXCPUPACKAGES	MAXCPUS		/* maximum of ci->ci_package_id */
 static struct aarch64_cache_info *aarch64_cacheinfo[MAXCPUPACKAGES];
+static struct aarch64_cache_info aarch64_cacheinfo0;
 
 
 static void
@@ -88,27 +89,46 @@ extract_cacheunit(int level, bool insn, 
 }
 
 void
-aarch64_getcacheinfo(void)
+aarch64_gettopology(struct cpu_info * const ci, uint64_t mpidr)
 {
+
+	if (mpidr & MPIDR_MT) {
+		ci->ci_smt_id = __SHIFTOUT(mpidr, MPIDR_AFF0);
+		ci->ci_core_id = __SHIFTOUT(mpidr, MPIDR_AFF1);
+		ci->ci_package_id = __SHIFTOUT(mpidr, MPIDR_AFF2);
+	} else {
+		ci->ci_core_id = __SHIFTOUT(mpidr, MPIDR_AFF0);
+		ci->ci_package_id = __SHIFTOUT(mpidr, MPIDR_AFF1);
+	}
+}
+
+void
+aarch64_getcacheinfo(int unit)
+{
+	struct cpu_info * const ci = curcpu();
 	uint32_t clidr, ctr;
 	int level, cachetype;
-	struct aarch64_cache_info *cinfo;
+	struct aarch64_cache_info *cinfo = NULL;
 
 	if (cputype == 0)
 		cputype = aarch64_cpuid();
 
 	/* already extract about this cluster? */
-	KASSERT(curcpu()->ci_package_id < MAXCPUPACKAGES);
-	cinfo = aarch64_cacheinfo[curcpu()->ci_package_id];
+	KASSERT(ci->ci_package_id < MAXCPUPACKAGES);
+	cinfo = aarch64_cacheinfo[ci->ci_package_id];
 	if (cinfo != NULL) {
-		curcpu()->ci_cacheinfo = cinfo;
+		ci->ci_cacheinfo = cinfo;
 		return;
 	}
 
-	cinfo = aarch64_cacheinfo[curcpu()->ci_package_id] =
-	kmem_zalloc(sizeof(struct aarch64_cache_info) * MAX_CACHE_LEVEL,
-	KM_SLEEP);
-	curcpu()->ci_cacheinfo = cinfo;
+	/* 

CVS commit: src/sys/arch/aarch64

2019-10-29 Thread Maya Rashish
Module Name:src
Committed By:   maya
Date:   Tue Oct 29 20:01:22 UTC 2019

Modified Files:
src/sys/arch/aarch64/aarch64: pmap.c
src/sys/arch/aarch64/include: pmap.h

Log Message:
Define PMAP_NEED_PROCWR, providing strategically placed i-cache
synchronization where just-changed memory is about to be executed.

Fixes SIGILLs seen when running Mono 6 on QEMU Cortex-A57.

ok ryo


To generate a diff of this commit:
cvs rdiff -u -r1.47 -r1.48 src/sys/arch/aarch64/aarch64/pmap.c
cvs rdiff -u -r1.25 -r1.26 src/sys/arch/aarch64/include/pmap.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/aarch64

2019-10-29 Thread Maya Rashish
Module Name:src
Committed By:   maya
Date:   Tue Oct 29 20:01:22 UTC 2019

Modified Files:
src/sys/arch/aarch64/aarch64: pmap.c
src/sys/arch/aarch64/include: pmap.h

Log Message:
Define PMAP_NEED_PROCWR, providing strategically placed i-cache
synchronization where just-changed memory is about to be executed.

Fixes SIGILLs seen when running Mono 6 on QEMU Cortex-A57.

ok ryo


To generate a diff of this commit:
cvs rdiff -u -r1.47 -r1.48 src/sys/arch/aarch64/aarch64/pmap.c
cvs rdiff -u -r1.25 -r1.26 src/sys/arch/aarch64/include/pmap.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/aarch64/aarch64/pmap.c
diff -u src/sys/arch/aarch64/aarch64/pmap.c:1.47 src/sys/arch/aarch64/aarch64/pmap.c:1.48
--- src/sys/arch/aarch64/aarch64/pmap.c:1.47	Sun Sep 22 13:57:55 2019
+++ src/sys/arch/aarch64/aarch64/pmap.c	Tue Oct 29 20:01:22 2019
@@ -1,4 +1,4 @@
-/*	$NetBSD: pmap.c,v 1.47 2019/09/22 13:57:55 jmcneill Exp $	*/
+/*	$NetBSD: pmap.c,v 1.48 2019/10/29 20:01:22 maya Exp $	*/
 
 /*
  * Copyright (c) 2017 Ryo Shimizu 
@@ -27,7 +27,7 @@
  */
 
 #include 
-__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.47 2019/09/22 13:57:55 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.48 2019/10/29 20:01:22 maya Exp $");
 
 #include "opt_arm_debug.h"
 #include "opt_ddb.h"
@@ -877,6 +877,22 @@ pmap_icache_sync_range(pmap_t pm, vaddr_
 	pm_unlock(pm);
 }
 
+/*
+ * Routine:	pmap_procwr
+ *
+ * Function:
+ *	Synchronize caches corresponding to [addr, addr+len) in p.
+ *
+ */
+void
+pmap_procwr(struct proc *p, vaddr_t va, int len)
+{
+
+	/* We only need to do anything if it is the current process. */
+	if (p == curproc)
+		cpu_icache_sync_range(va, len);
+}
+
 static pt_entry_t
 _pmap_pte_adjust_prot(pt_entry_t pte, vm_prot_t prot, vm_prot_t protmask,
 bool user)

Index: src/sys/arch/aarch64/include/pmap.h
diff -u src/sys/arch/aarch64/include/pmap.h:1.25 src/sys/arch/aarch64/include/pmap.h:1.26
--- src/sys/arch/aarch64/include/pmap.h:1.25	Mon Aug 12 10:28:04 2019
+++ src/sys/arch/aarch64/include/pmap.h	Tue Oct 29 20:01:22 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: pmap.h,v 1.25 2019/08/12 10:28:04 skrll Exp $ */
+/* $NetBSD: pmap.h,v 1.26 2019/10/29 20:01:22 maya Exp $ */
 
 /*-
  * Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -46,6 +46,7 @@
 
 #include 
 
+#define PMAP_NEED_PROCWR
 #define PMAP_GROWKERNEL
 #define PMAP_STEAL_MEMORY
 
@@ -272,6 +273,7 @@ aarch64_mmap_flags(paddr_t mdpgno)
 #define pmap_wired_count(pmap)		((pmap)->pm_stats.wired_count)
 #define pmap_resident_count(pmap)	((pmap)->pm_stats.resident_count)
 
+void	pmap_procwr(struct proc *, vaddr_t, int);
 bool	pmap_extract_coherency(pmap_t, vaddr_t, paddr_t *, bool *);
 void	pmap_icache_sync_range(pmap_t, vaddr_t, vaddr_t);
 



CVS commit: src/sys/arch/aarch64/aarch64

2019-10-28 Thread Joerg Sonnenberger
Module Name:src
Committed By:   joerg
Date:   Mon Oct 28 18:15:26 UTC 2019

Modified Files:
src/sys/arch/aarch64/aarch64: db_disasm.c

Log Message:
Format string annotation for strdisasm_printf


To generate a diff of this commit:
cvs rdiff -u -r1.6 -r1.7 src/sys/arch/aarch64/aarch64/db_disasm.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/aarch64/aarch64/db_disasm.c
diff -u src/sys/arch/aarch64/aarch64/db_disasm.c:1.6 src/sys/arch/aarch64/aarch64/db_disasm.c:1.7
--- src/sys/arch/aarch64/aarch64/db_disasm.c:1.6	Sun Jan 27 02:08:36 2019
+++ src/sys/arch/aarch64/aarch64/db_disasm.c	Mon Oct 28 18:15:25 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: db_disasm.c,v 1.6 2019/01/27 02:08:36 pgoyette Exp $ */
+/* $NetBSD: db_disasm.c,v 1.7 2019/10/28 18:15:25 joerg Exp $ */
 
 /*
  * Copyright (c) 2017 Ryo Shimizu 
@@ -27,7 +27,7 @@
  */
 
 #include 
-__KERNEL_RCSID(0, "$NetBSD: db_disasm.c,v 1.6 2019/01/27 02:08:36 pgoyette Exp $");
+__KERNEL_RCSID(0, "$NetBSD: db_disasm.c,v 1.7 2019/10/28 18:15:25 joerg Exp $");
 
 #include 
 #include 
@@ -75,7 +75,7 @@ strdisasm_readword(uintptr_t address)
 	return *(uint32_t *)address;
 }
 
-static void
+static void __printflike(1, 2)
 strdisasm_printf(const char *fmt, ...)
 {
 	va_list ap;



CVS commit: src/sys/arch/aarch64/aarch64

2019-10-28 Thread Joerg Sonnenberger
Module Name:src
Committed By:   joerg
Date:   Mon Oct 28 18:15:26 UTC 2019

Modified Files:
src/sys/arch/aarch64/aarch64: db_disasm.c

Log Message:
Format string annotation for strdisasm_printf


To generate a diff of this commit:
cvs rdiff -u -r1.6 -r1.7 src/sys/arch/aarch64/aarch64/db_disasm.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/aarch64/aarch64

2019-10-20 Thread Jared D. McNeill
Module Name:src
Committed By:   jmcneill
Date:   Sun Oct 20 14:03:51 UTC 2019

Modified Files:
src/sys/arch/aarch64/aarch64: cpu.c locore.S

Log Message:
Use separate cacheline aligned arrays for mbox and hatched as before.


To generate a diff of this commit:
cvs rdiff -u -r1.24 -r1.25 src/sys/arch/aarch64/aarch64/cpu.c
cvs rdiff -u -r1.43 -r1.44 src/sys/arch/aarch64/aarch64/locore.S

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/aarch64/aarch64/cpu.c
diff -u src/sys/arch/aarch64/aarch64/cpu.c:1.24 src/sys/arch/aarch64/aarch64/cpu.c:1.25
--- src/sys/arch/aarch64/aarch64/cpu.c:1.24	Sun Oct 20 11:17:41 2019
+++ src/sys/arch/aarch64/aarch64/cpu.c	Sun Oct 20 14:03:51 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.c,v 1.24 2019/10/20 11:17:41 jmcneill Exp $ */
+/* $NetBSD: cpu.c,v 1.25 2019/10/20 14:03:51 jmcneill Exp $ */
 
 /*
  * Copyright (c) 2017 Ryo Shimizu 
@@ -27,7 +27,7 @@
  */
 
 #include 
-__KERNEL_RCSID(1, "$NetBSD: cpu.c,v 1.24 2019/10/20 11:17:41 jmcneill Exp $");
+__KERNEL_RCSID(1, "$NetBSD: cpu.c,v 1.25 2019/10/20 14:03:51 jmcneill Exp $");
 
 #include "locators.h"
 #include "opt_arm_debug.h"
@@ -69,9 +69,8 @@ static void cpu_setup_sysctl(device_t, s
 #ifdef MULTIPROCESSOR
 uint64_t cpu_mpidr[MAXCPUS];
 
-volatile u_int aarch64_cpu_mbox[MAXCPUS] __cacheline_aligned = { 0 };
-#define CPU_MBOX_HATCHED	__BIT(0)
-#define	CPU_MBOX_START		__BIT(1)
+volatile u_int aarch64_cpu_mbox[howmany(MAXCPUS, sizeof(u_int))] __cacheline_aligned = { 0 };
+volatile u_int aarch64_cpu_hatched[howmany(MAXCPUS, sizeof(u_int))] __cacheline_aligned = { 0 };
 u_int arm_cpu_max = 1;
 
 static kmutex_t cpu_hatch_lock;
@@ -500,7 +499,7 @@ cpu_setup_sysctl(device_t dv, struct cpu
 void
 cpu_boot_secondary_processors(void)
 {
-	u_int cpuno;
+	u_int n, bit;
 
 	if ((boothowto & RB_MD1) != 0)
 		return;
@@ -510,22 +509,20 @@ cpu_boot_secondary_processors(void)
 	VPRINTF("%s: starting secondary processors\n", __func__);
 
 	/* send mbox to have secondary processors do cpu_hatch() */
-	for (cpuno = 1; cpuno < ncpu; cpuno++) {
-		if (cpu_hatched_p(cpuno) == false)
-			continue;
-		atomic_or_uint(_cpu_mbox[cpuno], CPU_MBOX_START);
-	}
+	for (n = 0; n < __arraycount(aarch64_cpu_mbox); n++)
+		atomic_or_uint(_cpu_mbox[n], aarch64_cpu_hatched[n]);
 	__asm __volatile ("sev; sev; sev");
 
 	/* wait all cpus have done cpu_hatch() */
-	for (cpuno = 1; cpuno < ncpu; cpuno++) {
-		if (cpu_hatched_p(cpuno) == 0)
-			continue;
-		while (membar_consumer(), aarch64_cpu_mbox[cpuno] & CPU_MBOX_START) {
+	for (n = 0; n < __arraycount(aarch64_cpu_mbox); n++) {
+		while (membar_consumer(), aarch64_cpu_mbox[n] & aarch64_cpu_hatched[n]) {
 			__asm __volatile ("wfe");
 		}
-		/* Add processor to kcpuset */
-		kcpuset_set(kcpuset_attached, cpuno);
+		/* Add processors to kcpuset */
+		for (bit = 0; bit < 32; bit++) {
+			if (aarch64_cpu_hatched[n] & __BIT(bit))
+kcpuset_set(kcpuset_attached, n * 32 + bit);
+		}
 	}
 
 	VPRINTF("%s: secondary processors hatched\n", __func__);
@@ -563,15 +560,18 @@ cpu_hatch(struct cpu_info *ci)
 	 * ci_index are each cpu0=0, cpu1=1, cpu2=undef, cpu3=2.
 	 * therefore we have to use device_unit instead of ci_index for mbox.
 	 */
-	const u_int cpuno = device_unit(ci->ci_dev);
-	atomic_and_uint(_cpu_mbox[cpuno], ~(u_int)CPU_MBOX_START);
+	const u_int off = device_unit(ci->ci_dev) / 32;
+	const u_int bit = device_unit(ci->ci_dev) % 32;
+	atomic_and_uint(_cpu_mbox[off], ~__BIT(bit));
 	__asm __volatile ("sev; sev; sev");
 }
 
 bool
 cpu_hatched_p(u_int cpuindex)
 {
-	aarch64_dcache_inv_range((vaddr_t)_cpu_mbox[cpuindex], 4);
-	return (aarch64_cpu_mbox[cpuindex] & CPU_MBOX_HATCHED) != 0;
+	const u_int off = cpuindex / 32;
+	const u_int bit = cpuindex % 32;
+	membar_consumer();
+	return (aarch64_cpu_hatched[off] & __BIT(bit)) != 0;
 }
 #endif /* MULTIPROCESSOR */

Index: src/sys/arch/aarch64/aarch64/locore.S
diff -u src/sys/arch/aarch64/aarch64/locore.S:1.43 src/sys/arch/aarch64/aarch64/locore.S:1.44
--- src/sys/arch/aarch64/aarch64/locore.S:1.43	Sun Oct 20 12:25:43 2019
+++ src/sys/arch/aarch64/aarch64/locore.S	Sun Oct 20 14:03:51 2019
@@ -1,4 +1,4 @@
-/*	$NetBSD: locore.S,v 1.43 2019/10/20 12:25:43 skrll Exp $	*/
+/*	$NetBSD: locore.S,v 1.44 2019/10/20 14:03:51 jmcneill Exp $	*/
 
 /*
  * Copyright (c) 2017 Ryo Shimizu 
@@ -38,7 +38,7 @@
 #include 
 #include "assym.h"
 
-RCSID("$NetBSD: locore.S,v 1.43 2019/10/20 12:25:43 skrll Exp $")
+RCSID("$NetBSD: locore.S,v 1.44 2019/10/20 14:03:51 jmcneill Exp $")
 
 
 /*#define DEBUG_LOCORE			/* debug print */
@@ -361,19 +361,16 @@ ENTRY_NP(cpu_mpstart)
 	mov	x1, xzr
 1:
 	add	x1, x1, #1
-	cmp	x1, MAXCPUS		/* cpuindex >= MAXCPUS ? */
+	cmp	x1, #MAXCPUS		/* cpuindex >= MAXCPUS ? */
 	bge	toomanycpus
 	ldr	x2, [x0, x1, lsl #3]	/* cpu_mpidr[cpuindex] */
 	cmp	x2, x3			/* == mpidr_el1 & MPIDR_AFF ? */
 	bne	1b
 
 	mov	x27, x1			/* x27 = cpuindex */
-	ADDR	x0, 

CVS commit: src/sys/arch/aarch64/aarch64

2019-10-20 Thread Jared D. McNeill
Module Name:src
Committed By:   jmcneill
Date:   Sun Oct 20 14:03:51 UTC 2019

Modified Files:
src/sys/arch/aarch64/aarch64: cpu.c locore.S

Log Message:
Use separate cacheline aligned arrays for mbox and hatched as before.


To generate a diff of this commit:
cvs rdiff -u -r1.24 -r1.25 src/sys/arch/aarch64/aarch64/cpu.c
cvs rdiff -u -r1.43 -r1.44 src/sys/arch/aarch64/aarch64/locore.S

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/aarch64/aarch64

2019-10-20 Thread Nick Hudson
Module Name:src
Committed By:   skrll
Date:   Sun Oct 20 12:25:43 UTC 2019

Modified Files:
src/sys/arch/aarch64/aarch64: locore.S

Log Message:
Avoid overlap between BP and last AP stack. AP stacks are now in order of
increasing address order.

Spotted by and idea from mlelstv.


To generate a diff of this commit:
cvs rdiff -u -r1.42 -r1.43 src/sys/arch/aarch64/aarch64/locore.S

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/aarch64/aarch64

2019-10-20 Thread Nick Hudson
Module Name:src
Committed By:   skrll
Date:   Sun Oct 20 12:25:43 UTC 2019

Modified Files:
src/sys/arch/aarch64/aarch64: locore.S

Log Message:
Avoid overlap between BP and last AP stack. AP stacks are now in order of
increasing address order.

Spotted by and idea from mlelstv.


To generate a diff of this commit:
cvs rdiff -u -r1.42 -r1.43 src/sys/arch/aarch64/aarch64/locore.S

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/aarch64/aarch64/locore.S
diff -u src/sys/arch/aarch64/aarch64/locore.S:1.42 src/sys/arch/aarch64/aarch64/locore.S:1.43
--- src/sys/arch/aarch64/aarch64/locore.S:1.42	Sat Oct 19 18:04:26 2019
+++ src/sys/arch/aarch64/aarch64/locore.S	Sun Oct 20 12:25:43 2019
@@ -1,4 +1,4 @@
-/*	$NetBSD: locore.S,v 1.42 2019/10/19 18:04:26 jmcneill Exp $	*/
+/*	$NetBSD: locore.S,v 1.43 2019/10/20 12:25:43 skrll Exp $	*/
 
 /*
  * Copyright (c) 2017 Ryo Shimizu 
@@ -38,7 +38,7 @@
 #include 
 #include "assym.h"
 
-RCSID("$NetBSD: locore.S,v 1.42 2019/10/19 18:04:26 jmcneill Exp $")
+RCSID("$NetBSD: locore.S,v 1.43 2019/10/20 12:25:43 skrll Exp $")
 
 
 /*#define DEBUG_LOCORE			/* debug print */
@@ -379,9 +379,8 @@ ENTRY_NP(cpu_mpstart)
 	/* set stack pointer for boot */
 	mov	x1, #BOOT_AP_STACKSIZE
 	mul	x1, x1, x27
-	ADDR	x0, bootstk_cpus
-	sub	sp, x0, x1  /* sp = bootstk_cpus-(BOOT_AP_STACKSIZE*cpuindex) */
-
+	ADDR	x0, bootstk
+	add	sp, x0, x1  /* sp = bootstk + (BOOT_AP_STACKSIZE * cpuindex) */
 
 	bl	1f
 1:	CPU_DPRINTREG("PC   = ", lr)
@@ -1038,7 +1037,6 @@ bootstk:
 
 #ifdef MULTIPROCESSOR
 	.space	BOOT_AP_STACKSIZE * (MAXCPUS - 1)
-bootstk_cpus:
 #endif
 
 	.section ".init_pagetable", "aw", %nobits



CVS commit: src/sys/arch/aarch64/aarch64

2019-10-20 Thread Jared D. McNeill
Module Name:src
Committed By:   jmcneill
Date:   Sun Oct 20 11:17:42 UTC 2019

Modified Files:
src/sys/arch/aarch64/aarch64: cpu.c

Log Message:
Invalidate dcache before polling AP hatched status


To generate a diff of this commit:
cvs rdiff -u -r1.23 -r1.24 src/sys/arch/aarch64/aarch64/cpu.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/aarch64/aarch64/cpu.c
diff -u src/sys/arch/aarch64/aarch64/cpu.c:1.23 src/sys/arch/aarch64/aarch64/cpu.c:1.24
--- src/sys/arch/aarch64/aarch64/cpu.c:1.23	Sat Oct 19 18:04:26 2019
+++ src/sys/arch/aarch64/aarch64/cpu.c	Sun Oct 20 11:17:41 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.c,v 1.23 2019/10/19 18:04:26 jmcneill Exp $ */
+/* $NetBSD: cpu.c,v 1.24 2019/10/20 11:17:41 jmcneill Exp $ */
 
 /*
  * Copyright (c) 2017 Ryo Shimizu 
@@ -27,7 +27,7 @@
  */
 
 #include 
-__KERNEL_RCSID(1, "$NetBSD: cpu.c,v 1.23 2019/10/19 18:04:26 jmcneill Exp $");
+__KERNEL_RCSID(1, "$NetBSD: cpu.c,v 1.24 2019/10/20 11:17:41 jmcneill Exp $");
 
 #include "locators.h"
 #include "opt_arm_debug.h"
@@ -571,7 +571,7 @@ cpu_hatch(struct cpu_info *ci)
 bool
 cpu_hatched_p(u_int cpuindex)
 {
-	membar_consumer();
+	aarch64_dcache_inv_range((vaddr_t)_cpu_mbox[cpuindex], 4);
 	return (aarch64_cpu_mbox[cpuindex] & CPU_MBOX_HATCHED) != 0;
 }
 #endif /* MULTIPROCESSOR */



CVS commit: src/sys/arch/aarch64/aarch64

2019-10-20 Thread Jared D. McNeill
Module Name:src
Committed By:   jmcneill
Date:   Sun Oct 20 11:17:42 UTC 2019

Modified Files:
src/sys/arch/aarch64/aarch64: cpu.c

Log Message:
Invalidate dcache before polling AP hatched status


To generate a diff of this commit:
cvs rdiff -u -r1.23 -r1.24 src/sys/arch/aarch64/aarch64/cpu.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/aarch64/aarch64

2019-10-14 Thread Jared D. McNeill
Module Name:src
Committed By:   jmcneill
Date:   Mon Oct 14 22:53:05 UTC 2019

Modified Files:
src/sys/arch/aarch64/aarch64: cpu.c

Log Message:
Remove the A72 errata #859971 detection, it causes an illegal instruction on 
AWS A1 (virtualized)


To generate a diff of this commit:
cvs rdiff -u -r1.21 -r1.22 src/sys/arch/aarch64/aarch64/cpu.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/aarch64/aarch64/cpu.c
diff -u src/sys/arch/aarch64/aarch64/cpu.c:1.21 src/sys/arch/aarch64/aarch64/cpu.c:1.22
--- src/sys/arch/aarch64/aarch64/cpu.c:1.21	Sun Sep 15 15:16:30 2019
+++ src/sys/arch/aarch64/aarch64/cpu.c	Mon Oct 14 22:53:05 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.c,v 1.21 2019/09/15 15:16:30 tnn Exp $ */
+/* $NetBSD: cpu.c,v 1.22 2019/10/14 22:53:05 jmcneill Exp $ */
 
 /*
  * Copyright (c) 2017 Ryo Shimizu 
@@ -27,7 +27,7 @@
  */
 
 #include 
-__KERNEL_RCSID(1, "$NetBSD: cpu.c,v 1.21 2019/09/15 15:16:30 tnn Exp $");
+__KERNEL_RCSID(1, "$NetBSD: cpu.c,v 1.22 2019/10/14 22:53:05 jmcneill Exp $");
 
 #include "locators.h"
 #include "opt_arm_debug.h"
@@ -432,14 +432,6 @@ cpu_identify2(device_t self, struct cpu_
 	}
 
 	aprint_normal("\n");
-
-	if ((id->ac_midr & CPU_PARTMASK) == (CPU_ID_CORTEXA72R0 & CPU_PARTMASK)
-	&& __SHIFTOUT(id->ac_midr, CPU_ID_REVISION_MASK) <= 3) {
-		aprint_normal_dev(self, "A72 errata #859971 present"
-		", workaround %s\n",
-		ISSET(reg_a72_cpuactlr_el1_read(), __BIT(32))
-		? "enabled" : "NOT enabled (U-Boot update needed)");
-	}
 }
 
 /*



CVS commit: src/sys/arch/aarch64/aarch64

2019-10-14 Thread Jared D. McNeill
Module Name:src
Committed By:   jmcneill
Date:   Mon Oct 14 22:53:05 UTC 2019

Modified Files:
src/sys/arch/aarch64/aarch64: cpu.c

Log Message:
Remove the A72 errata #859971 detection, it causes an illegal instruction on 
AWS A1 (virtualized)


To generate a diff of this commit:
cvs rdiff -u -r1.21 -r1.22 src/sys/arch/aarch64/aarch64/cpu.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/aarch64/aarch64

2019-09-29 Thread Nick Hudson
Module Name:src
Committed By:   skrll
Date:   Sun Sep 29 08:33:20 UTC 2019

Modified Files:
src/sys/arch/aarch64/aarch64: locore.S

Log Message:
Typo in comment


To generate a diff of this commit:
cvs rdiff -u -r1.40 -r1.41 src/sys/arch/aarch64/aarch64/locore.S

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/aarch64/aarch64

2019-09-29 Thread Nick Hudson
Module Name:src
Committed By:   skrll
Date:   Sun Sep 29 08:33:20 UTC 2019

Modified Files:
src/sys/arch/aarch64/aarch64: locore.S

Log Message:
Typo in comment


To generate a diff of this commit:
cvs rdiff -u -r1.40 -r1.41 src/sys/arch/aarch64/aarch64/locore.S

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/aarch64/aarch64/locore.S
diff -u src/sys/arch/aarch64/aarch64/locore.S:1.40 src/sys/arch/aarch64/aarch64/locore.S:1.41
--- src/sys/arch/aarch64/aarch64/locore.S:1.40	Sun Sep  8 12:17:23 2019
+++ src/sys/arch/aarch64/aarch64/locore.S	Sun Sep 29 08:33:20 2019
@@ -1,4 +1,4 @@
-/*	$NetBSD: locore.S,v 1.40 2019/09/08 12:17:23 jmcneill Exp $	*/
+/*	$NetBSD: locore.S,v 1.41 2019/09/29 08:33:20 skrll Exp $	*/
 
 /*
  * Copyright (c) 2017 Ryo Shimizu 
@@ -38,7 +38,7 @@
 #include 
 #include "assym.h"
 
-RCSID("$NetBSD: locore.S,v 1.40 2019/09/08 12:17:23 jmcneill Exp $")
+RCSID("$NetBSD: locore.S,v 1.41 2019/09/29 08:33:20 skrll Exp $")
 
 
 /*#define DEBUG_LOCORE			/* debug print */
@@ -799,7 +799,7 @@ init_mmutable:
 	adr	x0, start			/* va = start */
 	ADDR	x2, _end
 	sub	x2, x2, x0			/* size = _end - start */
-	add	x2, x2, #BOOTPAGE_ALLOC_MAX	/* for boopage_alloc() */
+	add	x2, x2, #BOOTPAGE_ALLOC_MAX	/* for bootpage_alloc() */
 	mov	x1, x0/* pa */
 	bl	pmapboot_enter
 	cbnz	x0, init_mmutable_error



CVS commit: src/sys/arch/aarch64/aarch64

2019-09-28 Thread Nick Hudson
Module Name:src
Committed By:   skrll
Date:   Sat Sep 28 07:06:50 UTC 2019

Modified Files:
src/sys/arch/aarch64/aarch64: trap.c

Log Message:
newline after break


To generate a diff of this commit:
cvs rdiff -u -r1.18 -r1.19 src/sys/arch/aarch64/aarch64/trap.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/aarch64/aarch64

2019-09-28 Thread Nick Hudson
Module Name:src
Committed By:   skrll
Date:   Sat Sep 28 07:06:50 UTC 2019

Modified Files:
src/sys/arch/aarch64/aarch64: trap.c

Log Message:
newline after break


To generate a diff of this commit:
cvs rdiff -u -r1.18 -r1.19 src/sys/arch/aarch64/aarch64/trap.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/aarch64/aarch64/trap.c
diff -u src/sys/arch/aarch64/aarch64/trap.c:1.18 src/sys/arch/aarch64/aarch64/trap.c:1.19
--- src/sys/arch/aarch64/aarch64/trap.c:1.18	Wed Aug  7 09:49:40 2019
+++ src/sys/arch/aarch64/aarch64/trap.c	Sat Sep 28 07:06:50 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: trap.c,v 1.18 2019/08/07 09:49:40 jmcneill Exp $ */
+/* $NetBSD: trap.c,v 1.19 2019/09/28 07:06:50 skrll Exp $ */
 
 /*-
  * Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -31,7 +31,7 @@
 
 #include 
 
-__KERNEL_RCSID(1, "$NetBSD: trap.c,v 1.18 2019/08/07 09:49:40 jmcneill Exp $");
+__KERNEL_RCSID(1, "$NetBSD: trap.c,v 1.19 2019/09/28 07:06:50 skrll Exp $");
 
 #include "opt_arm_intr_impl.h"
 #include "opt_compat_netbsd32.h"
@@ -348,10 +348,12 @@ trap_el0_32sync(struct trapframe *tf)
 	case ESR_EC_SVC_A32:
 		(*l->l_proc->p_md.md_syscall)(tf);
 		break;
+
 	case ESR_EC_FP_ACCESS:
 		fpu_load(l);
 		userret(l);
 		break;
+
 	case ESR_EC_FP_TRAP_A32:
 		do_trapsignal(l, SIGFPE, FPE_FLTUND, NULL, esr); /* XXX */
 		userret(l);
@@ -361,6 +363,7 @@ trap_el0_32sync(struct trapframe *tf)
 		do_trapsignal(l, SIGBUS, BUS_ADRALN, (void *)tf->tf_pc, esr);
 		userret(l);
 		break;
+
 	case ESR_EC_SP_ALIGNMENT:
 		do_trapsignal(l, SIGBUS, BUS_ADRALN,
 		(void *)tf->tf_reg[13], esr); /* sp is r13 on AArch32 */



CVS commit: src/sys/arch/aarch64/aarch64

2019-09-28 Thread Nick Hudson
Module Name:src
Committed By:   skrll
Date:   Sat Sep 28 07:06:32 UTC 2019

Modified Files:
src/sys/arch/aarch64/aarch64: aarch64_machdep.c

Log Message:
Whitespace


To generate a diff of this commit:
cvs rdiff -u -r1.31 -r1.32 src/sys/arch/aarch64/aarch64/aarch64_machdep.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/aarch64/aarch64

2019-09-28 Thread Nick Hudson
Module Name:src
Committed By:   skrll
Date:   Sat Sep 28 07:06:32 UTC 2019

Modified Files:
src/sys/arch/aarch64/aarch64: aarch64_machdep.c

Log Message:
Whitespace


To generate a diff of this commit:
cvs rdiff -u -r1.31 -r1.32 src/sys/arch/aarch64/aarch64/aarch64_machdep.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/aarch64/aarch64/aarch64_machdep.c
diff -u src/sys/arch/aarch64/aarch64/aarch64_machdep.c:1.31 src/sys/arch/aarch64/aarch64/aarch64_machdep.c:1.32
--- src/sys/arch/aarch64/aarch64/aarch64_machdep.c:1.31	Wed Sep 11 08:15:48 2019
+++ src/sys/arch/aarch64/aarch64/aarch64_machdep.c	Sat Sep 28 07:06:32 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: aarch64_machdep.c,v 1.31 2019/09/11 08:15:48 ryo Exp $ */
+/* $NetBSD: aarch64_machdep.c,v 1.32 2019/09/28 07:06:32 skrll Exp $ */
 
 /*-
  * Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
  */
 
 #include 
-__KERNEL_RCSID(1, "$NetBSD: aarch64_machdep.c,v 1.31 2019/09/11 08:15:48 ryo Exp $");
+__KERNEL_RCSID(1, "$NetBSD: aarch64_machdep.c,v 1.32 2019/09/28 07:06:32 skrll Exp $");
 
 #include "opt_arm_debug.h"
 #include "opt_ddb.h"
@@ -225,7 +225,6 @@ cpu_kernel_vm_init(uint64_t memory_start
 
 	aarch64_tlbi_all();
 
-
 	VPRINTF("%s: kernel phys start %lx end %lx+%lx\n", __func__,
 	kernstart_phys, kernend_phys, kernend_extra);
 	fdt_add_reserved_memory_range(kernstart_phys,



CVS commit: src/sys/arch/aarch64/aarch64

2019-09-22 Thread Jared D. McNeill
Module Name:src
Committed By:   jmcneill
Date:   Sun Sep 22 13:57:55 UTC 2019

Modified Files:
src/sys/arch/aarch64/aarch64: pmap.c

Log Message:
Disable translation table walks using TTBR0 while changing its value and
when deactivating a pmap. Fixes stability issues on Ampere eMAG CPUs.


To generate a diff of this commit:
cvs rdiff -u -r1.46 -r1.47 src/sys/arch/aarch64/aarch64/pmap.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/aarch64/aarch64

2019-09-22 Thread Jared D. McNeill
Module Name:src
Committed By:   jmcneill
Date:   Sun Sep 22 13:57:55 UTC 2019

Modified Files:
src/sys/arch/aarch64/aarch64: pmap.c

Log Message:
Disable translation table walks using TTBR0 while changing its value and
when deactivating a pmap. Fixes stability issues on Ampere eMAG CPUs.


To generate a diff of this commit:
cvs rdiff -u -r1.46 -r1.47 src/sys/arch/aarch64/aarch64/pmap.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/aarch64/aarch64/pmap.c
diff -u src/sys/arch/aarch64/aarch64/pmap.c:1.46 src/sys/arch/aarch64/aarch64/pmap.c:1.47
--- src/sys/arch/aarch64/aarch64/pmap.c:1.46	Fri Sep 20 05:35:27 2019
+++ src/sys/arch/aarch64/aarch64/pmap.c	Sun Sep 22 13:57:55 2019
@@ -1,4 +1,4 @@
-/*	$NetBSD: pmap.c,v 1.46 2019/09/20 05:35:27 ryo Exp $	*/
+/*	$NetBSD: pmap.c,v 1.47 2019/09/22 13:57:55 jmcneill Exp $	*/
 
 /*
  * Copyright (c) 2017 Ryo Shimizu 
@@ -27,7 +27,7 @@
  */
 
 #include 
-__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.46 2019/09/20 05:35:27 ryo Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.47 2019/09/22 13:57:55 jmcneill Exp $");
 
 #include "opt_arm_debug.h"
 #include "opt_ddb.h"
@@ -1274,7 +1274,7 @@ void
 pmap_activate(struct lwp *l)
 {
 	struct pmap *pm = l->l_proc->p_vmspace->vm_map.pmap;
-	uint64_t ttbr0;
+	uint64_t ttbr0, tcr;
 
 	UVMHIST_FUNC(__func__);
 	UVMHIST_CALLED(pmaphist);
@@ -1288,6 +1288,11 @@ pmap_activate(struct lwp *l)
 
 	UVMHIST_LOG(pmaphist, "lwp=%p (pid=%d)", l, l->l_proc->p_pid, 0, 0);
 
+	/* Disable translation table walks using TTBR0 */
+	tcr = reg_tcr_el1_read();
+	reg_tcr_el1_write(tcr | TCR_EPD0);
+	__asm __volatile("isb" ::: "memory");
+
 	/* XXX */
 	CTASSERT(PID_MAX <= 65535);	/* 16bit ASID */
 	if (pm->pm_asid == -1)
@@ -1296,6 +1301,11 @@ pmap_activate(struct lwp *l)
 	ttbr0 = ((uint64_t)pm->pm_asid << 48) | pm->pm_l0table_pa;
 	cpu_set_ttbr0(ttbr0);
 
+	/* Re-enable translation table walks using TTBR0 */
+	tcr = reg_tcr_el1_read();
+	reg_tcr_el1_write(tcr & ~TCR_EPD0);
+	__asm __volatile("isb" ::: "memory");
+
 	pm->pm_activated = true;
 
 	PMAP_COUNT(activate);
@@ -1305,6 +1315,7 @@ void
 pmap_deactivate(struct lwp *l)
 {
 	struct pmap *pm = l->l_proc->p_vmspace->vm_map.pmap;
+	uint64_t tcr;
 
 	UVMHIST_FUNC(__func__);
 	UVMHIST_CALLED(pmaphist);
@@ -1314,6 +1325,11 @@ pmap_deactivate(struct lwp *l)
 
 	UVMHIST_LOG(pmaphist, "lwp=%p, asid=%d", l, pm->pm_asid, 0, 0);
 
+	/* Disable translation table walks using TTBR0 */
+	tcr = reg_tcr_el1_read();
+	reg_tcr_el1_write(tcr | TCR_EPD0);
+	__asm __volatile("isb" ::: "memory");
+
 	/* XXX */
 	pm->pm_activated = false;
 



CVS commit: src/sys/arch/aarch64/aarch64

2019-09-19 Thread Ryo Shimizu
Module Name:src
Committed By:   ryo
Date:   Fri Sep 20 05:35:27 UTC 2019

Modified Files:
src/sys/arch/aarch64/aarch64: pmap.c

Log Message:
ref/mod bit should be set according to 'flags' argument, not 'prot'.  r1.44 was 
incomplete.


To generate a diff of this commit:
cvs rdiff -u -r1.45 -r1.46 src/sys/arch/aarch64/aarch64/pmap.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/aarch64/aarch64

2019-09-19 Thread Ryo Shimizu
Module Name:src
Committed By:   ryo
Date:   Fri Sep 20 05:35:27 UTC 2019

Modified Files:
src/sys/arch/aarch64/aarch64: pmap.c

Log Message:
ref/mod bit should be set according to 'flags' argument, not 'prot'.  r1.44 was 
incomplete.


To generate a diff of this commit:
cvs rdiff -u -r1.45 -r1.46 src/sys/arch/aarch64/aarch64/pmap.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/aarch64/aarch64/pmap.c
diff -u src/sys/arch/aarch64/aarch64/pmap.c:1.45 src/sys/arch/aarch64/aarch64/pmap.c:1.46
--- src/sys/arch/aarch64/aarch64/pmap.c:1.45	Fri Sep 13 18:07:30 2019
+++ src/sys/arch/aarch64/aarch64/pmap.c	Fri Sep 20 05:35:27 2019
@@ -1,4 +1,4 @@
-/*	$NetBSD: pmap.c,v 1.45 2019/09/13 18:07:30 ryo Exp $	*/
+/*	$NetBSD: pmap.c,v 1.46 2019/09/20 05:35:27 ryo Exp $	*/
 
 /*
  * Copyright (c) 2017 Ryo Shimizu 
@@ -27,7 +27,7 @@
  */
 
 #include 
-__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.45 2019/09/13 18:07:30 ryo Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.46 2019/09/20 05:35:27 ryo Exp $");
 
 #include "opt_arm_debug.h"
 #include "opt_ddb.h"
@@ -1724,6 +1724,8 @@ _pmap_enter(struct pmap *pm, vaddr_t va,
 	 */
 	if (prot & (VM_PROT_WRITE|VM_PROT_EXECUTE))
 		prot |= VM_PROT_READ;
+	if (flags & (VM_PROT_WRITE|VM_PROT_EXECUTE))
+		flags |= VM_PROT_READ;
 
 	mdattr = VM_PROT_READ | VM_PROT_WRITE;
 	if (need_update_pv) {
@@ -1750,7 +1752,7 @@ _pmap_enter(struct pmap *pm, vaddr_t va,
 	if (pg != NULL) {
 		/* update referenced/modified flags */
 		VM_PAGE_TO_MD(pg)->mdpg_flags |=
-		(prot & (VM_PROT_READ | VM_PROT_WRITE));
+		(flags & (VM_PROT_READ | VM_PROT_WRITE));
 		mdattr &= VM_PAGE_TO_MD(pg)->mdpg_flags;
 	}
 



CVS commit: src/sys/arch/aarch64

2019-09-15 Thread Tobias Nygren
Module Name:src
Committed By:   tnn
Date:   Sun Sep 15 15:16:30 UTC 2019

Modified Files:
src/sys/arch/aarch64/aarch64: cpu.c
src/sys/arch/aarch64/include: armreg.h

Log Message:
report A72 errata #859971 workaround status during boot


To generate a diff of this commit:
cvs rdiff -u -r1.20 -r1.21 src/sys/arch/aarch64/aarch64/cpu.c
cvs rdiff -u -r1.27 -r1.28 src/sys/arch/aarch64/include/armreg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/aarch64

2019-09-15 Thread Tobias Nygren
Module Name:src
Committed By:   tnn
Date:   Sun Sep 15 15:16:30 UTC 2019

Modified Files:
src/sys/arch/aarch64/aarch64: cpu.c
src/sys/arch/aarch64/include: armreg.h

Log Message:
report A72 errata #859971 workaround status during boot


To generate a diff of this commit:
cvs rdiff -u -r1.20 -r1.21 src/sys/arch/aarch64/aarch64/cpu.c
cvs rdiff -u -r1.27 -r1.28 src/sys/arch/aarch64/include/armreg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/aarch64/aarch64/cpu.c
diff -u src/sys/arch/aarch64/aarch64/cpu.c:1.20 src/sys/arch/aarch64/aarch64/cpu.c:1.21
--- src/sys/arch/aarch64/aarch64/cpu.c:1.20	Tue Jul 16 20:29:53 2019
+++ src/sys/arch/aarch64/aarch64/cpu.c	Sun Sep 15 15:16:30 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.c,v 1.20 2019/07/16 20:29:53 jmcneill Exp $ */
+/* $NetBSD: cpu.c,v 1.21 2019/09/15 15:16:30 tnn Exp $ */
 
 /*
  * Copyright (c) 2017 Ryo Shimizu 
@@ -27,7 +27,7 @@
  */
 
 #include 
-__KERNEL_RCSID(1, "$NetBSD: cpu.c,v 1.20 2019/07/16 20:29:53 jmcneill Exp $");
+__KERNEL_RCSID(1, "$NetBSD: cpu.c,v 1.21 2019/09/15 15:16:30 tnn Exp $");
 
 #include "locators.h"
 #include "opt_arm_debug.h"
@@ -432,6 +432,14 @@ cpu_identify2(device_t self, struct cpu_
 	}
 
 	aprint_normal("\n");
+
+	if ((id->ac_midr & CPU_PARTMASK) == (CPU_ID_CORTEXA72R0 & CPU_PARTMASK)
+	&& __SHIFTOUT(id->ac_midr, CPU_ID_REVISION_MASK) <= 3) {
+		aprint_normal_dev(self, "A72 errata #859971 present"
+		", workaround %s\n",
+		ISSET(reg_a72_cpuactlr_el1_read(), __BIT(32))
+		? "enabled" : "NOT enabled (U-Boot update needed)");
+	}
 }
 
 /*

Index: src/sys/arch/aarch64/include/armreg.h
diff -u src/sys/arch/aarch64/include/armreg.h:1.27 src/sys/arch/aarch64/include/armreg.h:1.28
--- src/sys/arch/aarch64/include/armreg.h:1.27	Wed Sep 11 18:19:35 2019
+++ src/sys/arch/aarch64/include/armreg.h	Sun Sep 15 15:16:30 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: armreg.h,v 1.27 2019/09/11 18:19:35 skrll Exp $ */
+/* $NetBSD: armreg.h,v 1.28 2019/09/15 15:16:30 tnn Exp $ */
 
 /*-
  * Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -260,6 +260,7 @@ AARCH64REG_READ_INLINE(id_aa64mmfr0_el1)
 #define	 ID_AA64MMFR0_EL1_PARANGE_16T	 4
 #define	 ID_AA64MMFR0_EL1_PARANGE_256T	 5
 
+AARCH64REG_READ_INLINE2(a72_cpuactlr_el1, s3_1_c15_c2_0)
 AARCH64REG_READ_INLINE(id_aa64mmfr1_el1)
 AARCH64REG_READ_INLINE(id_aa64mmfr2_el1)
 AARCH64REG_READ_INLINE(id_aa64pfr0_el1)



CVS commit: src/sys/arch/aarch64/aarch64

2019-09-15 Thread Nick Hudson
Module Name:src
Committed By:   skrll
Date:   Sun Sep 15 07:13:37 UTC 2019

Modified Files:
src/sys/arch/aarch64/aarch64: cpuswitch.S

Log Message:
Trailing whitespace


To generate a diff of this commit:
cvs rdiff -u -r1.11 -r1.12 src/sys/arch/aarch64/aarch64/cpuswitch.S

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/aarch64/aarch64

2019-09-15 Thread Nick Hudson
Module Name:src
Committed By:   skrll
Date:   Sun Sep 15 07:13:37 UTC 2019

Modified Files:
src/sys/arch/aarch64/aarch64: cpuswitch.S

Log Message:
Trailing whitespace


To generate a diff of this commit:
cvs rdiff -u -r1.11 -r1.12 src/sys/arch/aarch64/aarch64/cpuswitch.S

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/aarch64/aarch64/cpuswitch.S
diff -u src/sys/arch/aarch64/aarch64/cpuswitch.S:1.11 src/sys/arch/aarch64/aarch64/cpuswitch.S:1.12
--- src/sys/arch/aarch64/aarch64/cpuswitch.S:1.11	Thu Dec 27 09:55:27 2018
+++ src/sys/arch/aarch64/aarch64/cpuswitch.S	Sun Sep 15 07:13:37 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: cpuswitch.S,v 1.11 2018/12/27 09:55:27 mrg Exp $ */
+/* $NetBSD: cpuswitch.S,v 1.12 2019/09/15 07:13:37 skrll Exp $ */
 
 /*-
  * Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -37,7 +37,7 @@
 #include "opt_ddb.h"
 #include "opt_kasan.h"
 
-RCSID("$NetBSD: cpuswitch.S,v 1.11 2018/12/27 09:55:27 mrg Exp $")
+RCSID("$NetBSD: cpuswitch.S,v 1.12 2019/09/15 07:13:37 skrll Exp $")
 
 /*
  * At IPL_SCHED:
@@ -64,7 +64,7 @@ ENTRY_NP(cpu_switchto)
 	 * Save the current stack pointer and the CPACR and save them in
 	 * old lwp md area.
 	 */
-	mov	x4, sp 
+	mov	x4, sp
 	mrs	x5, cpacr_el1
 	str	x5, [x0, #L_MD_CPACR]
 	ldr	x6, [x0, #L_PCB]	/* x6 = lwp_getpcb(oldlwp) */



CVS commit: src/sys/arch/aarch64

2019-09-13 Thread Ryo Shimizu
Module Name:src
Committed By:   ryo
Date:   Fri Sep 13 18:07:30 UTC 2019

Modified Files:
src/sys/arch/aarch64/aarch64: pmap.c
src/sys/arch/aarch64/include: cpufunc.h

Log Message:
In pmap_devmap_bootstrap(), cpu_earlydevice_va_p() must not return true until 
*all* devmap tables have been enabled.
console mapping may be present in the last table.


To generate a diff of this commit:
cvs rdiff -u -r1.44 -r1.45 src/sys/arch/aarch64/aarch64/pmap.c
cvs rdiff -u -r1.6 -r1.7 src/sys/arch/aarch64/include/cpufunc.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/aarch64/aarch64/pmap.c
diff -u src/sys/arch/aarch64/aarch64/pmap.c:1.44 src/sys/arch/aarch64/aarch64/pmap.c:1.45
--- src/sys/arch/aarch64/aarch64/pmap.c:1.44	Sat Sep  7 09:57:37 2019
+++ src/sys/arch/aarch64/aarch64/pmap.c	Fri Sep 13 18:07:30 2019
@@ -1,4 +1,4 @@
-/*	$NetBSD: pmap.c,v 1.44 2019/09/07 09:57:37 ryo Exp $	*/
+/*	$NetBSD: pmap.c,v 1.45 2019/09/13 18:07:30 ryo Exp $	*/
 
 /*
  * Copyright (c) 2017 Ryo Shimizu 
@@ -27,7 +27,7 @@
  */
 
 #include 
-__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.44 2019/09/07 09:57:37 ryo Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.45 2019/09/13 18:07:30 ryo Exp $");
 
 #include "opt_arm_debug.h"
 #include "opt_ddb.h"
@@ -214,6 +214,7 @@ static vaddr_t pmap_maxkvaddr;
 
 vaddr_t virtual_avail, virtual_end;
 vaddr_t virtual_devmap_addr;
+bool pmap_devmap_bootstrap_done = false;
 
 static struct pool_cache _pmap_cache;
 static struct pool_cache _pmap_pv_pool;
@@ -338,6 +339,8 @@ pmap_devmap_bootstrap(vaddr_t l0pt, cons
 		table[i].pd_prot,
 		table[i].pd_flags);
 	}
+
+	pmap_devmap_bootstrap_done = true;
 }
 
 const struct pmap_devmap *

Index: src/sys/arch/aarch64/include/cpufunc.h
diff -u src/sys/arch/aarch64/include/cpufunc.h:1.6 src/sys/arch/aarch64/include/cpufunc.h:1.7
--- src/sys/arch/aarch64/include/cpufunc.h:1.6	Sat Sep  7 11:10:24 2019
+++ src/sys/arch/aarch64/include/cpufunc.h	Fri Sep 13 18:07:30 2019
@@ -1,4 +1,4 @@
-/*	$NetBSD: cpufunc.h,v 1.6 2019/09/07 11:10:24 ryo Exp $	*/
+/*	$NetBSD: cpufunc.h,v 1.7 2019/09/13 18:07:30 ryo Exp $	*/
 
 /*
  * Copyright (c) 2017 Ryo Shimizu 
@@ -148,14 +148,14 @@ cpu_clusterid(void)
 static inline bool
 cpu_earlydevice_va_p(void)
 {
-	extern vaddr_t virtual_devmap_addr;	/* in pmap.c */
+	extern bool pmap_devmap_bootstrap_done;	/* in pmap.c */
 
 	/* This function may be called before enabling MMU, or mapping KVA */
 	if ((reg_sctlr_el1_read() & SCTLR_M) == 0)
 		return false;
 
 	/* device mapping will be availabled after pmap_devmap_bootstrap() */
-	if (virtual_devmap_addr == 0)
+	if (!pmap_devmap_bootstrap_done)
 		return false;
 
 	return true;



CVS commit: src/sys/arch/aarch64

2019-09-13 Thread Ryo Shimizu
Module Name:src
Committed By:   ryo
Date:   Fri Sep 13 18:07:30 UTC 2019

Modified Files:
src/sys/arch/aarch64/aarch64: pmap.c
src/sys/arch/aarch64/include: cpufunc.h

Log Message:
In pmap_devmap_bootstrap(), cpu_earlydevice_va_p() must not return true until 
*all* devmap tables have been enabled.
console mapping may be present in the last table.


To generate a diff of this commit:
cvs rdiff -u -r1.44 -r1.45 src/sys/arch/aarch64/aarch64/pmap.c
cvs rdiff -u -r1.6 -r1.7 src/sys/arch/aarch64/include/cpufunc.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/aarch64/aarch64

2019-09-12 Thread Jared D. McNeill
Module Name:src
Committed By:   jmcneill
Date:   Thu Sep 12 09:05:28 UTC 2019

Modified Files:
src/sys/arch/aarch64/aarch64: cpufunc.c

Log Message:
Do not attempt to change coherency_unit at runtime. Instead, if the
required coherency unit is greater than COHERENCY_UNIT in a MULTIPROCESSOR
kernel, just panic instead.

This makes non-MULTIPROCESSOR kernels work again.


To generate a diff of this commit:
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/aarch64/aarch64/cpufunc.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/aarch64/aarch64

2019-09-12 Thread Jared D. McNeill
Module Name:src
Committed By:   jmcneill
Date:   Thu Sep 12 09:05:28 UTC 2019

Modified Files:
src/sys/arch/aarch64/aarch64: cpufunc.c

Log Message:
Do not attempt to change coherency_unit at runtime. Instead, if the
required coherency unit is greater than COHERENCY_UNIT in a MULTIPROCESSOR
kernel, just panic instead.

This makes non-MULTIPROCESSOR kernels work again.


To generate a diff of this commit:
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/aarch64/aarch64/cpufunc.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/aarch64/aarch64/cpufunc.c
diff -u src/sys/arch/aarch64/aarch64/cpufunc.c:1.5 src/sys/arch/aarch64/aarch64/cpufunc.c:1.6
--- src/sys/arch/aarch64/aarch64/cpufunc.c:1.5	Fri Dec 21 08:01:01 2018
+++ src/sys/arch/aarch64/aarch64/cpufunc.c	Thu Sep 12 09:05:28 2019
@@ -1,4 +1,4 @@
-/*	$NetBSD: cpufunc.c,v 1.5 2018/12/21 08:01:01 ryo Exp $	*/
+/*	$NetBSD: cpufunc.c,v 1.6 2019/09/12 09:05:28 jmcneill Exp $	*/
 
 /*
  * Copyright (c) 2017 Ryo Shimizu 
@@ -26,8 +26,10 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 
+#include "opt_multiprocessor.h"
+
 #include 
-__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.5 2018/12/21 08:01:01 ryo Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.6 2019/09/12 09:05:28 jmcneill Exp $");
 
 #include 
 #include 
@@ -135,9 +137,12 @@ aarch64_getcacheinfo(void)
 		arm_dcache_align = sizeof(int) << arm_dcache_maxline;
 		arm_dcache_align_mask = arm_dcache_align - 1;
 	}
-	/* update coherency_unit (in param.h) */
+
+#ifdef MULTIPROCESSOR
 	if (coherency_unit < arm_dcache_align)
-		coherency_unit = arm_dcache_align;
+		panic("coherency_unit %ld < arm_dcache_align %d; increase COHERENCY_UNIT",
+		coherency_unit, arm_dcache_align);
+#endif
 
 	/*
 	 * CLIDR -  Cache Level ID Register



CVS commit: src/sys/arch/aarch64/aarch64

2019-09-12 Thread Ryo Shimizu
Module Name:src
Committed By:   ryo
Date:   Thu Sep 12 06:12:56 UTC 2019

Modified Files:
src/sys/arch/aarch64/aarch64: cpufunc_asm_armv8.S

Log Message:
even if "no options MULTIPROCESSOR" requires isb after tlbi op. since it should 
be harmless, dsb is also added.
fixed a problem that rockpro64 doesn't boot without MULTIPROCESSOR.


To generate a diff of this commit:
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/aarch64/aarch64/cpufunc_asm_armv8.S

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/aarch64/aarch64/cpufunc_asm_armv8.S
diff -u src/sys/arch/aarch64/aarch64/cpufunc_asm_armv8.S:1.3 src/sys/arch/aarch64/aarch64/cpufunc_asm_armv8.S:1.4
--- src/sys/arch/aarch64/aarch64/cpufunc_asm_armv8.S:1.3	Fri Dec 21 08:01:01 2018
+++ src/sys/arch/aarch64/aarch64/cpufunc_asm_armv8.S	Thu Sep 12 06:12:56 2019
@@ -1,4 +1,4 @@
-/*	$NetBSD: cpufunc_asm_armv8.S,v 1.3 2018/12/21 08:01:01 ryo Exp $	*/
+/*	$NetBSD: cpufunc_asm_armv8.S,v 1.4 2019/09/12 06:12:56 ryo Exp $	*/
 
 /*-
  * Copyright (c) 2014 Robin Randhawa
@@ -243,16 +243,14 @@ ENTRY(aarch64_tlbi_by_asid_va)
 	/* x8 = bit 63[ASID]48, 47[RES0]44, 43[VA(55:12)]0 */
 	lsl	x8, x0, #48
 	bfxil	x8, x1, #12, #44
-#ifdef MULTIPROCESSOR
-	/* need dsb and isb for inner shareable? */
 	dsb	ishst
+#ifdef MULTIPROCESSOR
 	tlbi	vae1is, x8
-	dsb	ish
-	isb
 #else
-	/* no need dsb and isb for single entry */
 	tlbi	vae1, x8
 #endif
+	dsb	ish
+	isb
 	ret
 END(aarch64_tlbi_by_asid_va)
 
@@ -261,15 +259,13 @@ ENTRY(aarch64_tlbi_by_asid_va_ll)
 	/* x8 = bit 63[ASID]48, 47[RES0]44, 43[VA(55:12)]0 */
 	lsl	x8, x0, #48
 	bfxil	x8, x1, #12, #44
-#ifdef MULTIPROCESSOR
-	/* need dsb and isb for inner shareable? */
 	dsb	ishst
+#ifdef MULTIPROCESSOR
 	tlbi	vale1is, x8
-	dsb	ish
-	isb
 #else
-	/* no need dsb and isb for single entry */
 	tlbi	vale1, x8
 #endif
+	dsb	ish
+	isb
 	ret
 END(aarch64_tlbi_by_asid_va_ll)



CVS commit: src/sys/arch/aarch64/aarch64

2019-09-12 Thread Ryo Shimizu
Module Name:src
Committed By:   ryo
Date:   Thu Sep 12 06:12:56 UTC 2019

Modified Files:
src/sys/arch/aarch64/aarch64: cpufunc_asm_armv8.S

Log Message:
even if "no options MULTIPROCESSOR" requires isb after tlbi op. since it should 
be harmless, dsb is also added.
fixed a problem that rockpro64 doesn't boot without MULTIPROCESSOR.


To generate a diff of this commit:
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/aarch64/aarch64/cpufunc_asm_armv8.S

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/aarch64/include

2019-09-11 Thread Nick Hudson
Module Name:src
Committed By:   skrll
Date:   Wed Sep 11 18:23:31 UTC 2019

Modified Files:
src/sys/arch/aarch64/include: pte.h

Log Message:
Define PRIxPTE


To generate a diff of this commit:
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/aarch64/include/pte.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/aarch64/include/pte.h
diff -u src/sys/arch/aarch64/include/pte.h:1.9 src/sys/arch/aarch64/include/pte.h:1.10
--- src/sys/arch/aarch64/include/pte.h:1.9	Wed Sep 11 18:19:35 2019
+++ src/sys/arch/aarch64/include/pte.h	Wed Sep 11 18:23:31 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: pte.h,v 1.9 2019/09/11 18:19:35 skrll Exp $ */
+/* $NetBSD: pte.h,v 1.10 2019/09/11 18:23:31 skrll Exp $ */
 
 /*-
  * Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -36,7 +36,13 @@
 
 #ifndef _LOCORE
 typedef uint64_t pd_entry_t;	/* L0(512G) / L1(1G) / L2(2M) table entry */
+
+#ifndef __BSD_PTENTRY_T__
+#define __BSD_PTENTRY_T__
 typedef uint64_t pt_entry_t;	/* L3(4k) table entry */
+#define PRIxPTE PRIx64
+#endif /* __BSD_PTENTRY_T__ */
+
 #endif /* _LOCORE */
 
 /*



CVS commit: src/sys/arch/aarch64/include

2019-09-11 Thread Nick Hudson
Module Name:src
Committed By:   skrll
Date:   Wed Sep 11 18:23:31 UTC 2019

Modified Files:
src/sys/arch/aarch64/include: pte.h

Log Message:
Define PRIxPTE


To generate a diff of this commit:
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/aarch64/include/pte.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/aarch64/include

2019-09-11 Thread Nick Hudson
Module Name:src
Committed By:   skrll
Date:   Wed Sep 11 18:19:35 UTC 2019

Modified Files:
src/sys/arch/aarch64/include: armreg.h pte.h

Log Message:
Move the TCR and TTBR defines into armreg.h where they below.  NFCI.


To generate a diff of this commit:
cvs rdiff -u -r1.26 -r1.27 src/sys/arch/aarch64/include/armreg.h
cvs rdiff -u -r1.8 -r1.9 src/sys/arch/aarch64/include/pte.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/aarch64/include/armreg.h
diff -u src/sys/arch/aarch64/include/armreg.h:1.26 src/sys/arch/aarch64/include/armreg.h:1.27
--- src/sys/arch/aarch64/include/armreg.h:1.26	Mon Aug 12 23:31:48 2019
+++ src/sys/arch/aarch64/include/armreg.h	Wed Sep 11 18:19:35 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: armreg.h,v 1.26 2019/08/12 23:31:48 jmcneill Exp $ */
+/* $NetBSD: armreg.h,v 1.27 2019/09/11 18:19:35 skrll Exp $ */
 
 /*-
  * Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -646,7 +646,60 @@ AARCH64REG_WRITE_INLINE(spsr_el1)
 AARCH64REG_READ_INLINE(tcr_el1)		// Translation Control Register
 AARCH64REG_WRITE_INLINE(tcr_el1)
 
-#define TCR_PAGE_SIZE1(tcr)	(1L << ((1L << __SHIFTOUT(tcr, TCR_TG1)) + 8))
+
+/* TCR_EL1 - Translation Control Register */
+#define TCR_TBI1		__BIT(38)		/* ignore Top Byte TTBR1_EL1 */
+#define TCR_TBI0		__BIT(37)		/* ignore Top Byte TTBR0_EL1 */
+#define TCR_AS64K		__BIT(36)		/* Use 64K ASIDs */
+#define TCR_IPS			__BITS(34,32)		/* Intermediate PhysAdr Size */
+#define  TCR_IPS_4PB		__SHIFTIN(6,TCR_IPS)	/* 52 bits (  4 PB) */
+#define  TCR_IPS_256TB		__SHIFTIN(5,TCR_IPS)	/* 48 bits (256 TB) */
+#define  TCR_IPS_16TB		__SHIFTIN(4,TCR_IPS)	/* 44 bits  (16 TB) */
+#define  TCR_IPS_4TB		__SHIFTIN(3,TCR_IPS)	/* 42 bits  ( 4 TB) */
+#define  TCR_IPS_1TB		__SHIFTIN(2,TCR_IPS)	/* 40 bits  ( 1 TB) */
+#define  TCR_IPS_64GB		__SHIFTIN(1,TCR_IPS)	/* 36 bits  (64 GB) */
+#define  TCR_IPS_4GB		__SHIFTIN(0,TCR_IPS)	/* 32 bits   (4 GB) */
+#define TCR_TG1			__BITS(31,30)		/* TTBR1 Page Granule Size */
+#define  TCR_TG1_16KB		__SHIFTIN(1,TCR_TG1)	/* 16KB page size */
+#define  TCR_TG1_4KB		__SHIFTIN(2,TCR_TG1)	/* 4KB page size */
+#define  TCR_TG1_64KB		__SHIFTIN(3,TCR_TG1)	/* 64KB page size */
+#define TCR_SH1			__BITS(29,28)
+#define  TCR_SH1_NONE		__SHIFTIN(0,TCR_SH1)
+#define  TCR_SH1_OUTER		__SHIFTIN(2,TCR_SH1)
+#define  TCR_SH1_INNER		__SHIFTIN(3,TCR_SH1)
+#define TCR_ORGN1		__BITS(27,26)		/* TTBR1 Outer cacheability */
+#define  TCR_ORGN1_NC		__SHIFTIN(0,TCR_ORGN1)	/* Non Cacheable */
+#define  TCR_ORGN1_WB_WA	__SHIFTIN(1,TCR_ORGN1)	/* WriteBack WriteAllocate */
+#define  TCR_ORGN1_WT		__SHIFTIN(2,TCR_ORGN1)	/* WriteThrough */
+#define  TCR_ORGN1_WB		__SHIFTIN(3,TCR_ORGN1)	/* WriteBack */
+#define TCR_IRGN1		__BITS(25,24)		/* TTBR1 Inner cacheability */
+#define  TCR_IRGN1_NC		__SHIFTIN(0,TCR_IRGN1)	/* Non Cacheable */
+#define  TCR_IRGN1_WB_WA	__SHIFTIN(1,TCR_IRGN1)	/* WriteBack WriteAllocate */
+#define  TCR_IRGN1_WT		__SHIFTIN(2,TCR_IRGN1)	/* WriteThrough */
+#define  TCR_IRGN1_WB		__SHIFTIN(3,TCR_IRGN1)	/* WriteBack */
+#define TCR_EPD1		__BIT(23)		/* Walk Disable for TTBR1_EL1 */
+#define TCR_A1			__BIT(22)		/* ASID is in TTBR1_EL1 */
+#define TCR_T1SZ		__BITS(21,16)		/* Size offset for TTBR1_EL1 */
+#define TCR_TG0			__BITS(15,14)		/* TTBR0 Page Granule Size */
+#define  TCR_TG0_4KB		__SHIFTIN(0,TCR_TG0)	/* 4KB page size */
+#define  TCR_TG0_64KB		__SHIFTIN(1,TCR_TG0)	/* 64KB page size */
+#define  TCR_TG0_16KB		__SHIFTIN(2,TCR_TG0)	/* 16KB page size */
+#define TCR_SH0			__BITS(13,12)
+#define  TCR_SH0_NONE		__SHIFTIN(0,TCR_SH0)
+#define  TCR_SH0_OUTER		__SHIFTIN(2,TCR_SH0)
+#define  TCR_SH0_INNER		__SHIFTIN(3,TCR_SH0)
+#define TCR_ORGN0		__BITS(11,10)		/* TTBR0 Outer cacheability */
+#define  TCR_ORGN0_NC		__SHIFTIN(0,TCR_ORGN0)	/* Non Cacheable */
+#define  TCR_ORGN0_WB_WA	__SHIFTIN(1,TCR_ORGN0)	/* WriteBack WriteAllocate */
+#define  TCR_ORGN0_WT		__SHIFTIN(2,TCR_ORGN0)	/* WriteThrough */
+#define  TCR_ORGN0_WB		__SHIFTIN(3,TCR_ORGN0)	/* WriteBack */
+#define TCR_IRGN0		__BITS(9,8)		/* TTBR0 Inner cacheability */
+#define  TCR_IRGN0_NC		__SHIFTIN(0,TCR_IRGN0)	/* Non Cacheable */
+#define  TCR_IRGN0_WB_WA	__SHIFTIN(1,TCR_IRGN0)	/* WriteBack WriteAllocate */
+#define  TCR_IRGN0_WT		__SHIFTIN(2,TCR_IRGN0)	/* WriteThrough */
+#define  TCR_IRGN0_WB		__SHIFTIN(3,TCR_IRGN0)	/* WriteBack */
+#define TCR_EPD0		__BIT(7)		/* Walk Disable for TTBR0 */
+#define TCR_T0SZ		__BITS(5,0)		/* Size offset for TTBR0_EL1 */
 
 AARCH64REG_READ_INLINE(tpidr_el1)	// Thread ID Register (EL1)
 AARCH64REG_WRITE_INLINE(tpidr_el1)
@@ -659,6 +712,9 @@ AARCH64REG_WRITE_INLINE(ttbr0_el1)
 AARCH64REG_READ_INLINE(ttbr1_el1) // Translation Table Base Register 1 EL1
 AARCH64REG_WRITE_INLINE(ttbr1_el1)
 
+#define TTBR_ASID		__BITS(63,48)
+#define TTBR_BADDR		__BITS(47,0)
+
 AARCH64REG_READ_INLINE(vbar_el1)	// Vector Base Address Register
 AARCH64REG_WRITE_INLINE(vbar_el1)
 

Index: 

CVS commit: src/sys/arch/aarch64/include

2019-09-11 Thread Nick Hudson
Module Name:src
Committed By:   skrll
Date:   Wed Sep 11 18:19:35 UTC 2019

Modified Files:
src/sys/arch/aarch64/include: armreg.h pte.h

Log Message:
Move the TCR and TTBR defines into armreg.h where they below.  NFCI.


To generate a diff of this commit:
cvs rdiff -u -r1.26 -r1.27 src/sys/arch/aarch64/include/armreg.h
cvs rdiff -u -r1.8 -r1.9 src/sys/arch/aarch64/include/pte.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/aarch64/include

2019-09-11 Thread Jared D. McNeill
Module Name:src
Committed By:   jmcneill
Date:   Wed Sep 11 11:43:15 UTC 2019

Modified Files:
src/sys/arch/aarch64/include: pte.h

Log Message:
- Fix TCR_TG0 field definitions to match Armv8 ARM
- Rename TCR_IPS_64TB to TCR_IPS_16TB, add TCR_IPS_4PB
- Whitespace fixes


To generate a diff of this commit:
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/aarch64/include/pte.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/aarch64/include

2019-09-11 Thread Jared D. McNeill
Module Name:src
Committed By:   jmcneill
Date:   Wed Sep 11 11:43:15 UTC 2019

Modified Files:
src/sys/arch/aarch64/include: pte.h

Log Message:
- Fix TCR_TG0 field definitions to match Armv8 ARM
- Rename TCR_IPS_64TB to TCR_IPS_16TB, add TCR_IPS_4PB
- Whitespace fixes


To generate a diff of this commit:
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/aarch64/include/pte.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/aarch64/include/pte.h
diff -u src/sys/arch/aarch64/include/pte.h:1.7 src/sys/arch/aarch64/include/pte.h:1.8
--- src/sys/arch/aarch64/include/pte.h:1.7	Thu Aug 15 09:07:34 2019
+++ src/sys/arch/aarch64/include/pte.h	Wed Sep 11 11:43:15 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: pte.h,v 1.7 2019/08/15 09:07:34 skrll Exp $ */
+/* $NetBSD: pte.h,v 1.8 2019/09/11 11:43:15 jmcneill Exp $ */
 
 /*-
  * Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -134,8 +134,9 @@ typedef uint64_t pt_entry_t;	/* L3(4k) t
 #define TCR_TBI0		__BIT(37)		/* ignore Top Byte TTBR0_EL1 */
 #define TCR_AS64K		__BIT(36)		/* Use 64K ASIDs */
 #define TCR_IPS			__BITS(34,32)		/* Intermediate PhysAdr Size */
+#define  TCR_IPS_4PB		__SHIFTIN(6,TCR_IPS)	/* 52 bits (  4 PB) */
 #define  TCR_IPS_256TB		__SHIFTIN(5,TCR_IPS)	/* 48 bits (256 TB) */
-#define  TCR_IPS_64TB		__SHIFTIN(4,TCR_IPS)	/* 44 bits  (16 TB) */
+#define  TCR_IPS_16TB		__SHIFTIN(4,TCR_IPS)	/* 44 bits  (16 TB) */
 #define  TCR_IPS_4TB		__SHIFTIN(3,TCR_IPS)	/* 42 bits  ( 4 TB) */
 #define  TCR_IPS_1TB		__SHIFTIN(2,TCR_IPS)	/* 40 bits  ( 1 TB) */
 #define  TCR_IPS_64GB		__SHIFTIN(1,TCR_IPS)	/* 36 bits  (64 GB) */
@@ -162,9 +163,9 @@ typedef uint64_t pt_entry_t;	/* L3(4k) t
 #define TCR_A1			__BIT(22)		/* ASID is in TTBR1_EL1 */
 #define TCR_T1SZ		__BITS(21,16)		/* Size offset for TTBR1_EL1 */
 #define TCR_TG0			__BITS(15,14)		/* TTBR0 Page Granule Size */
-#define  TCR_TG0_16KB		__SHIFTIN(1,TCR_TG1)	/* 16KB page size */
-#define  TCR_TG0_4KB		__SHIFTIN(2,TCR_TG1)	/* 4KB page size */
-#define  TCR_TG0_64KB		__SHIFTIN(3,TCR_TG1)	/* 64KB page size */
+#define  TCR_TG0_4KB		__SHIFTIN(0,TCR_TG0)	/* 4KB page size */
+#define  TCR_TG0_64KB		__SHIFTIN(1,TCR_TG0)	/* 64KB page size */
+#define  TCR_TG0_16KB		__SHIFTIN(2,TCR_TG0)	/* 16KB page size */
 #define TCR_SH0			__BITS(13,12)
 #define  TCR_SH0_NONE		__SHIFTIN(0,TCR_SH0)
 #define  TCR_SH0_OUTER		__SHIFTIN(2,TCR_SH0)
@@ -176,7 +177,7 @@ typedef uint64_t pt_entry_t;	/* L3(4k) t
 #define  TCR_ORGN0_WB		__SHIFTIN(3,TCR_ORGN0)	/* WriteBack */
 #define TCR_IRGN0		__BITS(9,8)		/* TTBR0 Inner cacheability */
 #define  TCR_IRGN0_NC		__SHIFTIN(0,TCR_IRGN0)	/* Non Cacheable */
-#define  TCR_IRGN0_WB_WA		__SHIFTIN(1,TCR_IRGN0)	/* WriteBack WriteAllocate */
+#define  TCR_IRGN0_WB_WA	__SHIFTIN(1,TCR_IRGN0)	/* WriteBack WriteAllocate */
 #define  TCR_IRGN0_WT		__SHIFTIN(2,TCR_IRGN0)	/* WriteThrough */
 #define  TCR_IRGN0_WB		__SHIFTIN(3,TCR_IRGN0)	/* WriteBack */
 #define TCR_EPD0		__BIT(7)		/* Walk Disable for TTBR0 */



CVS commit: src/sys/arch/aarch64/aarch64

2019-09-11 Thread Ryo Shimizu
Module Name:src
Committed By:   ryo
Date:   Wed Sep 11 08:15:48 UTC 2019

Modified Files:
src/sys/arch/aarch64/aarch64: aarch64_machdep.c

Log Message:
used L3 even if L2 could cover the range. fix to use larger block if possible 
good enough.
pointed out by jmcneill@. thanks.


To generate a diff of this commit:
cvs rdiff -u -r1.30 -r1.31 src/sys/arch/aarch64/aarch64/aarch64_machdep.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/aarch64/aarch64/aarch64_machdep.c
diff -u src/sys/arch/aarch64/aarch64/aarch64_machdep.c:1.30 src/sys/arch/aarch64/aarch64/aarch64_machdep.c:1.31
--- src/sys/arch/aarch64/aarch64/aarch64_machdep.c:1.30	Mon Sep  9 17:02:36 2019
+++ src/sys/arch/aarch64/aarch64/aarch64_machdep.c	Wed Sep 11 08:15:48 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: aarch64_machdep.c,v 1.30 2019/09/09 17:02:36 ryo Exp $ */
+/* $NetBSD: aarch64_machdep.c,v 1.31 2019/09/11 08:15:48 ryo Exp $ */
 
 /*-
  * Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
  */
 
 #include 
-__KERNEL_RCSID(1, "$NetBSD: aarch64_machdep.c,v 1.30 2019/09/09 17:02:36 ryo Exp $");
+__KERNEL_RCSID(1, "$NetBSD: aarch64_machdep.c,v 1.31 2019/09/11 08:15:48 ryo Exp $");
 
 #include "opt_arm_debug.h"
 #include "opt_ddb.h"
@@ -144,7 +144,7 @@ cpu_kernel_vm_init(uint64_t memory_start
 		/* align the start address to L2 blocksize */
 		nblocks = ulmin(left / L3_SIZE,
 		Ln_ENTRIES - __SHIFTOUT(start, L3_ADDR_BITS));
-		if (nblocks > 0) {
+		if (((start & L3_ADDR_BITS) != 0) && (nblocks > 0)) {
 			mapsize = nblocks * L3_SIZE;
 			VPRINTF("Creating KSEG tables for %016lx-%016lx (L3)\n",
 			start, start + mapsize - 1);
@@ -159,7 +159,7 @@ cpu_kernel_vm_init(uint64_t memory_start
 		/* align the start address to L1 blocksize */
 		nblocks = ulmin(left / L2_SIZE,
 		Ln_ENTRIES - __SHIFTOUT(start, L2_ADDR_BITS));
-		if (nblocks > 0) {
+		if (((start & L2_ADDR_BITS) != 0) && (nblocks > 0)) {
 			mapsize = nblocks * L2_SIZE;
 			VPRINTF("Creating KSEG tables for %016lx-%016lx (L2)\n",
 			start, start + mapsize - 1);



CVS commit: src/sys/arch/aarch64/aarch64

2019-09-11 Thread Ryo Shimizu
Module Name:src
Committed By:   ryo
Date:   Wed Sep 11 08:15:48 UTC 2019

Modified Files:
src/sys/arch/aarch64/aarch64: aarch64_machdep.c

Log Message:
used L3 even if L2 could cover the range. fix to use larger block if possible 
good enough.
pointed out by jmcneill@. thanks.


To generate a diff of this commit:
cvs rdiff -u -r1.30 -r1.31 src/sys/arch/aarch64/aarch64/aarch64_machdep.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/aarch64/aarch64

2019-09-09 Thread Ryo Shimizu
Module Name:src
Committed By:   ryo
Date:   Mon Sep  9 17:02:36 UTC 2019

Modified Files:
src/sys/arch/aarch64/aarch64: aarch64_machdep.c

Log Message:
use L1-L3 blocks/pages for KSEG mappings to fit dramblocks exactly.
r1.29 and this changes avoid over cache prefetch problem (perhaps) with 
PMAP_MAP_POOLPAGE/KSEG on CortexA72, and be more stable for rockpro64.


To generate a diff of this commit:
cvs rdiff -u -r1.29 -r1.30 src/sys/arch/aarch64/aarch64/aarch64_machdep.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/aarch64/aarch64

2019-09-09 Thread Ryo Shimizu
Module Name:src
Committed By:   ryo
Date:   Mon Sep  9 17:02:36 UTC 2019

Modified Files:
src/sys/arch/aarch64/aarch64: aarch64_machdep.c

Log Message:
use L1-L3 blocks/pages for KSEG mappings to fit dramblocks exactly.
r1.29 and this changes avoid over cache prefetch problem (perhaps) with 
PMAP_MAP_POOLPAGE/KSEG on CortexA72, and be more stable for rockpro64.


To generate a diff of this commit:
cvs rdiff -u -r1.29 -r1.30 src/sys/arch/aarch64/aarch64/aarch64_machdep.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/aarch64/aarch64/aarch64_machdep.c
diff -u src/sys/arch/aarch64/aarch64/aarch64_machdep.c:1.29 src/sys/arch/aarch64/aarch64/aarch64_machdep.c:1.30
--- src/sys/arch/aarch64/aarch64/aarch64_machdep.c:1.29	Fri Sep  6 20:52:57 2019
+++ src/sys/arch/aarch64/aarch64/aarch64_machdep.c	Mon Sep  9 17:02:36 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: aarch64_machdep.c,v 1.29 2019/09/06 20:52:57 jmcneill Exp $ */
+/* $NetBSD: aarch64_machdep.c,v 1.30 2019/09/09 17:02:36 ryo Exp $ */
 
 /*-
  * Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
  */
 
 #include 
-__KERNEL_RCSID(1, "$NetBSD: aarch64_machdep.c,v 1.29 2019/09/06 20:52:57 jmcneill Exp $");
+__KERNEL_RCSID(1, "$NetBSD: aarch64_machdep.c,v 1.30 2019/09/09 17:02:36 ryo Exp $");
 
 #include "opt_arm_debug.h"
 #include "opt_ddb.h"
@@ -118,7 +118,6 @@ cpu_kernel_vm_init(uint64_t memory_start
 	extern char _end[];
 	extern char __data_start[];
 	extern char __rodata_start[];
-	uint64_t start, end;
 	u_int blk;
 
 	vaddr_t kernstart = trunc_page((vaddr_t)__kernel_text);
@@ -135,17 +134,79 @@ cpu_kernel_vm_init(uint64_t memory_start
 	LX_BLKPAG_PXN |
 	LX_BLKPAG_UXN;
 	for (blk = 0; blk < bootconfig.dramblocks; blk++) {
-		start = L2_TRUNC_BLOCK(bootconfig.dram[blk].address);
-		end = L2_ROUND_BLOCK(bootconfig.dram[blk].address +
+		uint64_t start, end, left, mapsize, nblocks;
+
+		start = trunc_page(bootconfig.dram[blk].address);
+		end = round_page(bootconfig.dram[blk].address +
 		(uint64_t)bootconfig.dram[blk].pages * PAGE_SIZE);
+		left = end - start;
+
+		/* align the start address to L2 blocksize */
+		nblocks = ulmin(left / L3_SIZE,
+		Ln_ENTRIES - __SHIFTOUT(start, L3_ADDR_BITS));
+		if (nblocks > 0) {
+			mapsize = nblocks * L3_SIZE;
+			VPRINTF("Creating KSEG tables for %016lx-%016lx (L3)\n",
+			start, start + mapsize - 1);
+			pmapboot_enter(AARCH64_PA_TO_KVA(start), start,
+			mapsize, L3_SIZE, ksegattr,
+			PMAPBOOT_ENTER_NOOVERWRITE, bootpage_alloc, NULL);
+
+			start += mapsize;
+			left -= mapsize;
+		}
+
+		/* align the start address to L1 blocksize */
+		nblocks = ulmin(left / L2_SIZE,
+		Ln_ENTRIES - __SHIFTOUT(start, L2_ADDR_BITS));
+		if (nblocks > 0) {
+			mapsize = nblocks * L2_SIZE;
+			VPRINTF("Creating KSEG tables for %016lx-%016lx (L2)\n",
+			start, start + mapsize - 1);
+			pmapboot_enter(AARCH64_PA_TO_KVA(start), start,
+			mapsize, L2_SIZE, ksegattr,
+			PMAPBOOT_ENTER_NOOVERWRITE, bootpage_alloc, NULL);
+			start += mapsize;
+			left -= mapsize;
+		}
 
-		VPRINTF("Creating KSEG tables for 0x%016lx-0x%016lx (L2)\n",
-		start, end);
-		pmapboot_enter(AARCH64_PA_TO_KVA(start), start, 
-		end - start, L2_SIZE, ksegattr, PMAPBOOT_ENTER_NOOVERWRITE,
-		bootpage_alloc, NULL);
-		aarch64_tlbi_all();
+		nblocks = left / L1_SIZE;
+		if (nblocks > 0) {
+			mapsize = nblocks * L1_SIZE;
+			VPRINTF("Creating KSEG tables for %016lx-%016lx (L1)\n",
+			start, start + mapsize - 1);
+			pmapboot_enter(AARCH64_PA_TO_KVA(start), start,
+			mapsize, L1_SIZE, ksegattr,
+			PMAPBOOT_ENTER_NOOVERWRITE, bootpage_alloc, NULL);
+			start += mapsize;
+			left -= mapsize;
+		}
+
+		if ((left & L2_ADDR_BITS) != 0) {
+			nblocks = left / L2_SIZE;
+			mapsize = nblocks * L2_SIZE;
+			VPRINTF("Creating KSEG tables for %016lx-%016lx (L2)\n",
+			start, start + mapsize - 1);
+			pmapboot_enter(AARCH64_PA_TO_KVA(start), start,
+			mapsize, L2_SIZE, ksegattr,
+			PMAPBOOT_ENTER_NOOVERWRITE, bootpage_alloc, NULL);
+			start += mapsize;
+			left -= mapsize;
+		}
+
+		if ((left & L3_ADDR_BITS) != 0) {
+			nblocks = left / L3_SIZE;
+			mapsize = nblocks * L3_SIZE;
+			VPRINTF("Creating KSEG tables for %016lx-%016lx (L3)\n",
+			start, start + mapsize - 1);
+			pmapboot_enter(AARCH64_PA_TO_KVA(start), start,
+			mapsize, L3_SIZE, ksegattr,
+			PMAPBOOT_ENTER_NOOVERWRITE, bootpage_alloc, NULL);
+			start += mapsize;
+			left -= mapsize;
+		}
 	}
+	aarch64_tlbi_all();
 
 	/*
 	 * at this point, whole kernel image is mapped as "rwx".



CVS commit: src/sys/arch/aarch64/aarch64

2019-09-08 Thread Jared D. McNeill
Module Name:src
Committed By:   jmcneill
Date:   Sun Sep  8 12:17:23 UTC 2019

Modified Files:
src/sys/arch/aarch64/aarch64: locore.S

Log Message:
Map device memory for early console XN


To generate a diff of this commit:
cvs rdiff -u -r1.39 -r1.40 src/sys/arch/aarch64/aarch64/locore.S

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/aarch64/aarch64/locore.S
diff -u src/sys/arch/aarch64/aarch64/locore.S:1.39 src/sys/arch/aarch64/aarch64/locore.S:1.40
--- src/sys/arch/aarch64/aarch64/locore.S:1.39	Wed Jul 17 08:39:03 2019
+++ src/sys/arch/aarch64/aarch64/locore.S	Sun Sep  8 12:17:23 2019
@@ -1,4 +1,4 @@
-/*	$NetBSD: locore.S,v 1.39 2019/07/17 08:39:03 skrll Exp $	*/
+/*	$NetBSD: locore.S,v 1.40 2019/09/08 12:17:23 jmcneill Exp $	*/
 
 /*
  * Copyright (c) 2017 Ryo Shimizu 
@@ -38,7 +38,7 @@
 #include 
 #include "assym.h"
 
-RCSID("$NetBSD: locore.S,v 1.39 2019/07/17 08:39:03 skrll Exp $")
+RCSID("$NetBSD: locore.S,v 1.40 2019/09/08 12:17:23 jmcneill Exp $")
 
 
 /*#define DEBUG_LOCORE			/* debug print */
@@ -766,6 +766,7 @@ init_mmutable:
 	adr	x6, bootpage_alloc		/* allocator */
 	mov	x5, xzr/* flags = 0 */
 	mov	x4, #LX_BLKPAG_ATTR_DEVICE_MEM|LX_BLKPAG_AP_RW	/* attr */
+	orr	x4, x4, #LX_BLKPAG_UXN|LX_BLKPAG_PXN
 	mov	x3, #L2_SIZE			/* blocksize */
 	mov	x2, #L2_SIZE			/* size */
 	ldr	x1, =CONSADDR			/* pa */
@@ -779,6 +780,7 @@ init_mmutable:
 	adr	x6, bootpage_alloc		/* allocator */
 	mov	x5, xzr/* flags = 0 */
 	mov	x4, #LX_BLKPAG_ATTR_DEVICE_MEM|LX_BLKPAG_AP_RW	/* attr */
+	orr	x4, x4, #LX_BLKPAG_UXN|LX_BLKPAG_PXN
 	mov	x3, #L2_SIZE			/* blocksize */
 	mov	x2, #(1024*1024*1024*4)		/* size */
 	mov	x1, xzr/* pa */



CVS commit: src/sys/arch/aarch64/aarch64

2019-09-08 Thread Jared D. McNeill
Module Name:src
Committed By:   jmcneill
Date:   Sun Sep  8 12:17:23 UTC 2019

Modified Files:
src/sys/arch/aarch64/aarch64: locore.S

Log Message:
Map device memory for early console XN


To generate a diff of this commit:
cvs rdiff -u -r1.39 -r1.40 src/sys/arch/aarch64/aarch64/locore.S

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/aarch64/aarch64

2019-09-07 Thread Ryo Shimizu
Module Name:src
Committed By:   ryo
Date:   Sat Sep  7 11:15:25 UTC 2019

Modified Files:
src/sys/arch/aarch64/aarch64: genassym.cf

Log Message:
add AARCH64_KSEG_MASK. pmap_page.S refer it. (but no functional changed)


To generate a diff of this commit:
cvs rdiff -u -r1.13 -r1.14 src/sys/arch/aarch64/aarch64/genassym.cf

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/aarch64/aarch64/genassym.cf
diff -u src/sys/arch/aarch64/aarch64/genassym.cf:1.13 src/sys/arch/aarch64/aarch64/genassym.cf:1.14
--- src/sys/arch/aarch64/aarch64/genassym.cf:1.13	Sat Jul 13 09:47:14 2019
+++ src/sys/arch/aarch64/aarch64/genassym.cf	Sat Sep  7 11:15:25 2019
@@ -1,4 +1,4 @@
-# $NetBSD: genassym.cf,v 1.13 2019/07/13 09:47:14 skrll Exp $
+# $NetBSD: genassym.cf,v 1.14 2019/09/07 11:15:25 ryo Exp $
 #-
 # Copyright (c) 2014 The NetBSD Foundation, Inc.
 # All rights reserved.
@@ -70,6 +70,7 @@ define	VM_MAX_KERNEL_ADDRESS	VM_MAX_KERN
 define	VM_KERNEL_IO_ADDRESS	VM_KERNEL_IO_ADDRESS
 define	VM_KERNEL_IO_SIZE	VM_KERNEL_IO_SIZE
 define	AARCH64_KSEG_START	AARCH64_KSEG_START
+define	AARCH64_KSEG_MASK	AARCH64_KSEG_MASK
 define	UPAGES			UPAGES
 define	USPACE			(UPAGES * PAGE_SIZE)
 



CVS commit: src/sys/arch/aarch64/aarch64

2019-09-07 Thread Ryo Shimizu
Module Name:src
Committed By:   ryo
Date:   Sat Sep  7 11:15:25 UTC 2019

Modified Files:
src/sys/arch/aarch64/aarch64: genassym.cf

Log Message:
add AARCH64_KSEG_MASK. pmap_page.S refer it. (but no functional changed)


To generate a diff of this commit:
cvs rdiff -u -r1.13 -r1.14 src/sys/arch/aarch64/aarch64/genassym.cf

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/aarch64/include

2019-09-07 Thread Ryo Shimizu
Module Name:src
Committed By:   ryo
Date:   Sat Sep  7 11:10:24 UTC 2019

Modified Files:
src/sys/arch/aarch64/include: cpufunc.h

Log Message:
add checking status of MMU and devmap to make _platform_early_putchar() 
available at all times.


To generate a diff of this commit:
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/aarch64/include/cpufunc.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/aarch64/include

2019-09-07 Thread Ryo Shimizu
Module Name:src
Committed By:   ryo
Date:   Sat Sep  7 11:10:24 UTC 2019

Modified Files:
src/sys/arch/aarch64/include: cpufunc.h

Log Message:
add checking status of MMU and devmap to make _platform_early_putchar() 
available at all times.


To generate a diff of this commit:
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/aarch64/include/cpufunc.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/aarch64/include/cpufunc.h
diff -u src/sys/arch/aarch64/include/cpufunc.h:1.5 src/sys/arch/aarch64/include/cpufunc.h:1.6
--- src/sys/arch/aarch64/include/cpufunc.h:1.5	Fri Dec 21 08:01:01 2018
+++ src/sys/arch/aarch64/include/cpufunc.h	Sat Sep  7 11:10:24 2019
@@ -1,4 +1,4 @@
-/*	$NetBSD: cpufunc.h,v 1.5 2018/12/21 08:01:01 ryo Exp $	*/
+/*	$NetBSD: cpufunc.h,v 1.6 2019/09/07 11:10:24 ryo Exp $	*/
 
 /*
  * Copyright (c) 2017 Ryo Shimizu 
@@ -148,8 +148,17 @@ cpu_clusterid(void)
 static inline bool
 cpu_earlydevice_va_p(void)
 {
+	extern vaddr_t virtual_devmap_addr;	/* in pmap.c */
 
-	return false;
+	/* This function may be called before enabling MMU, or mapping KVA */
+	if ((reg_sctlr_el1_read() & SCTLR_M) == 0)
+		return false;
+
+	/* device mapping will be availabled after pmap_devmap_bootstrap() */
+	if (virtual_devmap_addr == 0)
+		return false;
+
+	return true;
 }
 
 #endif /* _KERNEL */



CVS commit: src/sys/arch/aarch64/aarch64

2019-09-07 Thread Ryo Shimizu
Module Name:src
Committed By:   ryo
Date:   Sat Sep  7 09:57:37 UTC 2019

Modified Files:
src/sys/arch/aarch64/aarch64: pmap.c

Log Message:
- remove incorrect KASSERT. mmap(2) with prot=PROT_WRITE calls pmap_enter(..., 
PROT_WRITE) internally.
- fix to update page reference flags when only PROT_WRITE or PROT_EXECUTE 
specified


To generate a diff of this commit:
cvs rdiff -u -r1.43 -r1.44 src/sys/arch/aarch64/aarch64/pmap.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/aarch64/aarch64/pmap.c
diff -u src/sys/arch/aarch64/aarch64/pmap.c:1.43 src/sys/arch/aarch64/aarch64/pmap.c:1.44
--- src/sys/arch/aarch64/aarch64/pmap.c:1.43	Thu Aug 15 10:24:26 2019
+++ src/sys/arch/aarch64/aarch64/pmap.c	Sat Sep  7 09:57:37 2019
@@ -1,4 +1,4 @@
-/*	$NetBSD: pmap.c,v 1.43 2019/08/15 10:24:26 skrll Exp $	*/
+/*	$NetBSD: pmap.c,v 1.44 2019/09/07 09:57:37 ryo Exp $	*/
 
 /*
  * Copyright (c) 2017 Ryo Shimizu 
@@ -27,7 +27,7 @@
  */
 
 #include 
-__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.43 2019/08/15 10:24:26 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.44 2019/09/07 09:57:37 ryo Exp $");
 
 #include "opt_arm_debug.h"
 #include "opt_ddb.h"
@@ -1718,9 +1718,8 @@ _pmap_enter(struct pmap *pm, vaddr_t va,
 	/*
 	 * read permission is treated as an access permission internally.
 	 * require to add PROT_READ even if only PROT_WRITE or PROT_EXEC
-	 * for wired mapping.
 	 */
-	if ((flags & PMAP_WIRED) && (prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)))
+	if (prot & (VM_PROT_WRITE|VM_PROT_EXECUTE))
 		prot |= VM_PROT_READ;
 
 	mdattr = VM_PROT_READ | VM_PROT_WRITE;
@@ -1748,7 +1747,7 @@ _pmap_enter(struct pmap *pm, vaddr_t va,
 	if (pg != NULL) {
 		/* update referenced/modified flags */
 		VM_PAGE_TO_MD(pg)->mdpg_flags |=
-		(flags & (VM_PROT_READ | VM_PROT_WRITE));
+		(prot & (VM_PROT_READ | VM_PROT_WRITE));
 		mdattr &= VM_PAGE_TO_MD(pg)->mdpg_flags;
 	}
 
@@ -1818,8 +1817,6 @@ _pmap_enter(struct pmap *pm, vaddr_t va,
 int
 pmap_enter(struct pmap *pm, vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags)
 {
-	KASSERT((prot & VM_PROT_READ) || !(prot & VM_PROT_WRITE));
-
 	return _pmap_enter(pm, va, pa, prot, flags, false);
 }
 



CVS commit: src/sys/arch/aarch64/aarch64

2019-09-07 Thread Ryo Shimizu
Module Name:src
Committed By:   ryo
Date:   Sat Sep  7 09:57:37 UTC 2019

Modified Files:
src/sys/arch/aarch64/aarch64: pmap.c

Log Message:
- remove incorrect KASSERT. mmap(2) with prot=PROT_WRITE calls pmap_enter(..., 
PROT_WRITE) internally.
- fix to update page reference flags when only PROT_WRITE or PROT_EXECUTE 
specified


To generate a diff of this commit:
cvs rdiff -u -r1.43 -r1.44 src/sys/arch/aarch64/aarch64/pmap.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/aarch64/aarch64

2019-09-07 Thread Ryo Shimizu
Module Name:src
Committed By:   ryo
Date:   Sat Sep  7 09:27:25 UTC 2019

Modified Files:
src/sys/arch/aarch64/aarch64: db_machdep.c

Log Message:
prevent switching to CPUs that are not responding to IPI_DDB.


To generate a diff of this commit:
cvs rdiff -u -r1.18 -r1.19 src/sys/arch/aarch64/aarch64/db_machdep.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/aarch64/aarch64/db_machdep.c
diff -u src/sys/arch/aarch64/aarch64/db_machdep.c:1.18 src/sys/arch/aarch64/aarch64/db_machdep.c:1.19
--- src/sys/arch/aarch64/aarch64/db_machdep.c:1.18	Sat Sep  7 09:21:17 2019
+++ src/sys/arch/aarch64/aarch64/db_machdep.c	Sat Sep  7 09:27:25 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: db_machdep.c,v 1.18 2019/09/07 09:21:17 ryo Exp $ */
+/* $NetBSD: db_machdep.c,v 1.19 2019/09/07 09:27:25 ryo Exp $ */
 
 /*-
  * Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
  */
 
 #include 
-__KERNEL_RCSID(0, "$NetBSD: db_machdep.c,v 1.18 2019/09/07 09:21:17 ryo Exp $");
+__KERNEL_RCSID(0, "$NetBSD: db_machdep.c,v 1.19 2019/09/07 09:27:25 ryo Exp $");
 
 #ifdef _KERNEL_OPT
 #include "opt_compat_netbsd32.h"
@@ -868,24 +868,39 @@ db_md_watch_cmd(db_expr_t addr, bool hav
 volatile struct cpu_info *db_trigger;
 volatile struct cpu_info *db_onproc;
 volatile struct cpu_info *db_newcpu;
+volatile int db_readytoswitch[MAXCPUS];
 
 #ifdef _KERNEL
 void
 db_md_switch_cpu_cmd(db_expr_t addr, bool have_addr, db_expr_t count,
 const char *modif)
 {
+	struct cpu_info *new_ci = NULL;
 	u_int cpuno = (u_int)addr;
+	int i;
+
+	membar_consumer();
 
-	if (!have_addr || (cpuno >= ncpu)) {
-		db_printf("cpu: 0..%d\n", ncpu - 1);
+	if (!have_addr) {
+		for (i = 0; i < ncpu; i++) {
+			if (db_readytoswitch[i] != 0)
+db_printf("cpu%d: ready\n", i);
+			else
+db_printf("cpu%d: not responding\n", i);
+		}
 		return;
 	}
 
-	struct cpu_info *new_ci = cpu_lookup(cpuno);
+	if (cpuno < ncpu)
+		new_ci = cpu_lookup(cpuno);
 	if (new_ci == NULL) {
 		db_printf("cpu %u does not exist", cpuno);
 		return;
 	}
+	if (db_readytoswitch[new_ci->ci_index] == 0) {
+		db_printf("cpu %u is not responding", cpuno);
+		return;
+	}
 
 	if (new_ci == curcpu())
 		return;
@@ -940,6 +955,8 @@ kdb_trap(int type, struct trapframe *tf)
 		db_trigger = ci;
 		membar_producer();
 	}
+	db_readytoswitch[ci->ci_index] = 1;
+	membar_producer();
 #endif
 
 	for (;;) {
@@ -993,6 +1010,8 @@ kdb_trap(int type, struct trapframe *tf)
 		__asm __volatile ("sev; sev; sev");
 	}
 	db_trigger = NULL;
+	db_readytoswitch[ci->ci_index] = 0;
+	membar_producer();
 #endif
 
 	return 1;



CVS commit: src/sys/arch/aarch64/aarch64

2019-09-07 Thread Ryo Shimizu
Module Name:src
Committed By:   ryo
Date:   Sat Sep  7 09:27:25 UTC 2019

Modified Files:
src/sys/arch/aarch64/aarch64: db_machdep.c

Log Message:
prevent switching to CPUs that are not responding to IPI_DDB.


To generate a diff of this commit:
cvs rdiff -u -r1.18 -r1.19 src/sys/arch/aarch64/aarch64/db_machdep.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/aarch64/aarch64

2019-09-07 Thread Ryo Shimizu
Module Name:src
Committed By:   ryo
Date:   Sat Sep  7 09:21:17 UTC 2019

Modified Files:
src/sys/arch/aarch64/aarch64: db_machdep.c

Log Message:
add "machine cpuinfo/a" to show cpuinfo[] of all cpus


To generate a diff of this commit:
cvs rdiff -u -r1.17 -r1.18 src/sys/arch/aarch64/aarch64/db_machdep.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/aarch64/aarch64

2019-09-07 Thread Ryo Shimizu
Module Name:src
Committed By:   ryo
Date:   Sat Sep  7 09:21:17 UTC 2019

Modified Files:
src/sys/arch/aarch64/aarch64: db_machdep.c

Log Message:
add "machine cpuinfo/a" to show cpuinfo[] of all cpus


To generate a diff of this commit:
cvs rdiff -u -r1.17 -r1.18 src/sys/arch/aarch64/aarch64/db_machdep.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/aarch64/aarch64/db_machdep.c
diff -u src/sys/arch/aarch64/aarch64/db_machdep.c:1.17 src/sys/arch/aarch64/aarch64/db_machdep.c:1.18
--- src/sys/arch/aarch64/aarch64/db_machdep.c:1.17	Sun Aug 11 15:52:55 2019
+++ src/sys/arch/aarch64/aarch64/db_machdep.c	Sat Sep  7 09:21:17 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: db_machdep.c,v 1.17 2019/08/11 15:52:55 skrll Exp $ */
+/* $NetBSD: db_machdep.c,v 1.18 2019/09/07 09:21:17 ryo Exp $ */
 
 /*-
  * Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
  */
 
 #include 
-__KERNEL_RCSID(0, "$NetBSD: db_machdep.c,v 1.17 2019/08/11 15:52:55 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: db_machdep.c,v 1.18 2019/09/07 09:21:17 ryo Exp $");
 
 #ifdef _KERNEL_OPT
 #include "opt_compat_netbsd32.h"
@@ -260,19 +260,17 @@ dump_trapframe(struct trapframe *tf, voi
 }
 
 #if defined(_KERNEL)
-void
-db_md_cpuinfo_cmd(db_expr_t addr, bool have_addr, db_expr_t count,
-const char *modif)
+static void
+show_cpuinfo(struct cpu_info *ci)
 {
-	struct cpu_info *ci, cpuinfobuf;
+	struct cpu_info cpuinfobuf;
 	cpuid_t cpuid;
 	int i;
 
-	ci = curcpu();
 	db_read_bytes((db_addr_t)ci, sizeof(cpuinfobuf), (char *));
 
 	cpuid = cpuinfobuf.ci_cpuid;
-	db_printf("cpu_info=%p\n", ci);
+	db_printf("cpu_info=%p, cpu_name=%s\n", ci, cpuinfobuf.ci_cpuname);
 	db_printf("%p cpu[%lu].ci_cpuid= %lu\n",
 	>ci_cpuid, cpuid, cpuinfobuf.ci_cpuid);
 	db_printf("%p cpu[%lu].ci_curlwp   = %p\n",
@@ -296,6 +294,34 @@ db_md_cpuinfo_cmd(db_expr_t addr, bool h
 }
 
 void
+db_md_cpuinfo_cmd(db_expr_t addr, bool have_addr, db_expr_t count,
+const char *modif)
+{
+#ifdef MULTIPROCESSOR
+	CPU_INFO_ITERATOR cii;
+	struct cpu_info *ci;
+	bool showall = false;
+
+	if (modif != NULL) {
+		for (; *modif != '\0'; modif++) {
+			switch (*modif) {
+			case 'a':
+showall = true;
+break;
+			}
+		}
+	}
+
+	if (showall) {
+		for (CPU_INFO_FOREACH(cii, ci)) {
+			show_cpuinfo(ci);
+		}
+	} else
+#endif /* MULTIPROCESSOR */
+		show_cpuinfo(curcpu());
+}
+
+void
 db_md_frame_cmd(db_expr_t addr, bool have_addr, db_expr_t count,
 const char *modif)
 {



CVS commit: src/sys/arch/aarch64/aarch64

2019-09-06 Thread Jared D. McNeill
Module Name:src
Committed By:   jmcneill
Date:   Fri Sep  6 20:52:57 UTC 2019

Modified Files:
src/sys/arch/aarch64/aarch64: aarch64_machdep.c

Log Message:
Do not assume that DRAM is linear when creating KSEG mappings. Instead,
create L2 blocks to cover all ranges specified in the memory map.


To generate a diff of this commit:
cvs rdiff -u -r1.28 -r1.29 src/sys/arch/aarch64/aarch64/aarch64_machdep.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/aarch64/aarch64

2019-09-06 Thread Jared D. McNeill
Module Name:src
Committed By:   jmcneill
Date:   Fri Sep  6 20:52:57 UTC 2019

Modified Files:
src/sys/arch/aarch64/aarch64: aarch64_machdep.c

Log Message:
Do not assume that DRAM is linear when creating KSEG mappings. Instead,
create L2 blocks to cover all ranges specified in the memory map.


To generate a diff of this commit:
cvs rdiff -u -r1.28 -r1.29 src/sys/arch/aarch64/aarch64/aarch64_machdep.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/aarch64/aarch64/aarch64_machdep.c
diff -u src/sys/arch/aarch64/aarch64/aarch64_machdep.c:1.28 src/sys/arch/aarch64/aarch64/aarch64_machdep.c:1.29
--- src/sys/arch/aarch64/aarch64/aarch64_machdep.c:1.28	Sun Jan 27 02:08:36 2019
+++ src/sys/arch/aarch64/aarch64/aarch64_machdep.c	Fri Sep  6 20:52:57 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: aarch64_machdep.c,v 1.28 2019/01/27 02:08:36 pgoyette Exp $ */
+/* $NetBSD: aarch64_machdep.c,v 1.29 2019/09/06 20:52:57 jmcneill Exp $ */
 
 /*-
  * Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
  */
 
 #include 
-__KERNEL_RCSID(1, "$NetBSD: aarch64_machdep.c,v 1.28 2019/01/27 02:08:36 pgoyette Exp $");
+__KERNEL_RCSID(1, "$NetBSD: aarch64_machdep.c,v 1.29 2019/09/06 20:52:57 jmcneill Exp $");
 
 #include "opt_arm_debug.h"
 #include "opt_ddb.h"
@@ -112,12 +112,14 @@ int dumpsize = 0;   /* also 
 longdumplo = 0;
 
 void
-cpu_kernel_vm_init(uint64_t memory_start, uint64_t memory_size)
+cpu_kernel_vm_init(uint64_t memory_start __unused, uint64_t memory_size __unused)
 {
 	extern char __kernel_text[];
 	extern char _end[];
 	extern char __data_start[];
 	extern char __rodata_start[];
+	uint64_t start, end;
+	u_int blk;
 
 	vaddr_t kernstart = trunc_page((vaddr_t)__kernel_text);
 	vaddr_t kernend = round_page((vaddr_t)_end);
@@ -127,17 +129,23 @@ cpu_kernel_vm_init(uint64_t memory_start
 	vaddr_t rodata_start = (vaddr_t)__rodata_start;
 
 	/* add KSEG mappings of whole memory */
-	VPRINTF("Creating KSEG tables for 0x%016lx-0x%016lx\n",
-	memory_start, memory_start + memory_size);
 	const pt_entry_t ksegattr =
 	LX_BLKPAG_ATTR_NORMAL_WB |
 	LX_BLKPAG_AP_RW |
 	LX_BLKPAG_PXN |
 	LX_BLKPAG_UXN;
-	pmapboot_enter(AARCH64_PA_TO_KVA(memory_start), memory_start,
-	memory_size, L1_SIZE, ksegattr, PMAPBOOT_ENTER_NOOVERWRITE,
-	bootpage_alloc, NULL);
-	aarch64_tlbi_all();
+	for (blk = 0; blk < bootconfig.dramblocks; blk++) {
+		start = L2_TRUNC_BLOCK(bootconfig.dram[blk].address);
+		end = L2_ROUND_BLOCK(bootconfig.dram[blk].address +
+		(uint64_t)bootconfig.dram[blk].pages * PAGE_SIZE);
+
+		VPRINTF("Creating KSEG tables for 0x%016lx-0x%016lx (L2)\n",
+		start, end);
+		pmapboot_enter(AARCH64_PA_TO_KVA(start), start, 
+		end - start, L2_SIZE, ksegattr, PMAPBOOT_ENTER_NOOVERWRITE,
+		bootpage_alloc, NULL);
+		aarch64_tlbi_all();
+	}
 
 	/*
 	 * at this point, whole kernel image is mapped as "rwx".



CVS commit: src/sys/arch/aarch64/aarch64

2019-08-15 Thread Nick Hudson
Module Name:src
Committed By:   skrll
Date:   Thu Aug 15 10:24:26 UTC 2019

Modified Files:
src/sys/arch/aarch64/aarch64: pmap.c

Log Message:
Make pmap_db_pte_print more terse so it's quicker on serial consoles


To generate a diff of this commit:
cvs rdiff -u -r1.42 -r1.43 src/sys/arch/aarch64/aarch64/pmap.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/aarch64/aarch64

2019-08-15 Thread Nick Hudson
Module Name:src
Committed By:   skrll
Date:   Thu Aug 15 10:24:26 UTC 2019

Modified Files:
src/sys/arch/aarch64/aarch64: pmap.c

Log Message:
Make pmap_db_pte_print more terse so it's quicker on serial consoles


To generate a diff of this commit:
cvs rdiff -u -r1.42 -r1.43 src/sys/arch/aarch64/aarch64/pmap.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/aarch64/aarch64/pmap.c
diff -u src/sys/arch/aarch64/aarch64/pmap.c:1.42 src/sys/arch/aarch64/aarch64/pmap.c:1.43
--- src/sys/arch/aarch64/aarch64/pmap.c:1.42	Mon Aug 12 10:28:04 2019
+++ src/sys/arch/aarch64/aarch64/pmap.c	Thu Aug 15 10:24:26 2019
@@ -1,4 +1,4 @@
-/*	$NetBSD: pmap.c,v 1.42 2019/08/12 10:28:04 skrll Exp $	*/
+/*	$NetBSD: pmap.c,v 1.43 2019/08/15 10:24:26 skrll Exp $	*/
 
 /*
  * Copyright (c) 2017 Ryo Shimizu 
@@ -27,7 +27,7 @@
  */
 
 #include 
-__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.42 2019/08/12 10:28:04 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.43 2019/08/15 10:24:26 skrll Exp $");
 
 #include "opt_arm_debug.h"
 #include "opt_ddb.h"
@@ -2366,11 +2366,9 @@ pmap_db_pte_print(pt_entry_t pte, int le
 		pr(", PA=%lx", l3pte_pa(pte));
 
 		pr(", %s", (pte & LX_BLKPAG_UXN) ?
-		"UXN  " :
-		"user-exec");
+		"UXN" : "UX ");
 		pr(", %s", (pte & LX_BLKPAG_PXN) ?
-		   "PXN" :
-		   "kernel-exec");
+		   "PXN" :  "PX ");
 
 		if (pte & LX_BLKPAG_CONTIG)
 			pr(", CONTIG");
@@ -2401,13 +2399,13 @@ pmap_db_pte_print(pt_entry_t pte, int le
 
 		switch (pte & LX_BLKPAG_ATTR_MASK) {
 		case LX_BLKPAG_ATTR_NORMAL_WB:
-			pr(", WRITEBACK");
+			pr(", WB");
 			break;
 		case LX_BLKPAG_ATTR_NORMAL_NC:
-			pr(", NOCACHE");
+			pr(", NC");
 			break;
 		case LX_BLKPAG_ATTR_NORMAL_WT:
-			pr(", WHITETHRU");
+			pr(", WT");
 			break;
 		case LX_BLKPAG_ATTR_DEVICE_MEM:
 			pr(", DEVICE");
@@ -2421,7 +2419,7 @@ pmap_db_pte_print(pt_entry_t pte, int le
 		if (pte & LX_BLKPAG_OS_WRITE)
 			pr(", pmap_write");
 		if (pte & LX_BLKPAG_OS_WIRED)
-			pr(", pmap_wired");
+			pr(", wired");
 	} else {
 		pr(" **ILLEGAL TYPE**");
 	}



CVS commit: src/sys/arch/aarch64/include

2019-08-15 Thread Nick Hudson
Module Name:src
Committed By:   skrll
Date:   Thu Aug 15 09:07:34 UTC 2019

Modified Files:
src/sys/arch/aarch64/include: pte.h

Log Message:
Indent the field value defines.  NFCI.


To generate a diff of this commit:
cvs rdiff -u -r1.6 -r1.7 src/sys/arch/aarch64/include/pte.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/aarch64/include/pte.h
diff -u src/sys/arch/aarch64/include/pte.h:1.6 src/sys/arch/aarch64/include/pte.h:1.7
--- src/sys/arch/aarch64/include/pte.h:1.6	Tue Aug 13 08:27:42 2019
+++ src/sys/arch/aarch64/include/pte.h	Thu Aug 15 09:07:34 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: pte.h,v 1.6 2019/08/13 08:27:42 skrll Exp $ */
+/* $NetBSD: pte.h,v 1.7 2019/08/15 09:07:34 skrll Exp $ */
 
 /*-
  * Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -44,17 +44,17 @@ typedef uint64_t pt_entry_t;	/* L3(4k) t
  */
 #define LX_TBL_NSTABLE		__BIT(63)	/* inherited next level */
 #define LX_TBL_APTABLE		__BITS(62,61)	/* inherited next level */
-#define LX_TBL_APTABLE_NOEFFECT		__SHIFTIN(0,LX_TBL_APTABLE)
-#define LX_TBL_APTABLE_EL0_NOACCESS	__SHIFTIN(1,LX_TBL_APTABLE)
-#define LX_TBL_APTABLE_RO		__SHIFTIN(2,LX_TBL_APTABLE)
-#define LX_TBL_APTABLE_RO_EL0_NOREAD	__SHIFTIN(3,LX_TBL_APTABLE)
+#define  LX_TBL_APTABLE_NOEFFECT	__SHIFTIN(0,LX_TBL_APTABLE)
+#define  LX_TBL_APTABLE_EL0_NOACCESS	__SHIFTIN(1,LX_TBL_APTABLE)
+#define  LX_TBL_APTABLE_RO		__SHIFTIN(2,LX_TBL_APTABLE)
+#define  LX_TBL_APTABLE_RO_EL0_NOREAD	__SHIFTIN(3,LX_TBL_APTABLE)
 #define LX_TBL_UXNTABLE		__BIT(60)	/* inherited next level */
 #define LX_TBL_PXNTABLE		__BIT(59)	/* inherited next level */
 #define LX_BLKPAG_OS		__BITS(58, 55)
-# define LX_BLKPAG_OS_0		__SHIFTIN(1,LX_BLKPAG_OS)
-# define LX_BLKPAG_OS_1		__SHIFTIN(2,LX_BLKPAG_OS)
-# define LX_BLKPAG_OS_2		__SHIFTIN(4,LX_BLKPAG_OS)
-# define LX_BLKPAG_OS_3		__SHIFTIN(8,LX_BLKPAG_OS)
+#define  LX_BLKPAG_OS_0		__SHIFTIN(1,LX_BLKPAG_OS)
+#define  LX_BLKPAG_OS_1		__SHIFTIN(2,LX_BLKPAG_OS)
+#define  LX_BLKPAG_OS_2		__SHIFTIN(4,LX_BLKPAG_OS)
+#define  LX_BLKPAG_OS_3		__SHIFTIN(8,LX_BLKPAG_OS)
 #define LX_BLKPAG_UXN		__BIT(54)	/* Unprivileged Execute Never */
 #define LX_BLKPAG_PXN		__BIT(53)	/* Privileged Execute Never */
 #define LX_BLKPAG_CONTIG	__BIT(52)	/* Hint of TLB cache */
@@ -64,12 +64,12 @@ typedef uint64_t pt_entry_t;	/* L3(4k) t
 #define LX_BLKPAG_NG		__BIT(11)	/* Not Global */
 #define LX_BLKPAG_AF		__BIT(10)	/* Access Flag */
 #define LX_BLKPAG_SH		__BITS(9,8)	/* Shareability */
-#define LX_BLKPAG_SH_NS		__SHIFTIN(0,LX_BLKPAG_SH) /* Non Shareable */
-#define LX_BLKPAG_SH_OS		__SHIFTIN(2,LX_BLKPAG_SH) /* Outer Shareable */
-#define LX_BLKPAG_SH_IS		__SHIFTIN(3,LX_BLKPAG_SH) /* Inner Shareable */
+#define  LX_BLKPAG_SH_NS	__SHIFTIN(0,LX_BLKPAG_SH) /* Non Shareable */
+#define  LX_BLKPAG_SH_OS	__SHIFTIN(2,LX_BLKPAG_SH) /* Outer Shareable */
+#define  LX_BLKPAG_SH_IS	__SHIFTIN(3,LX_BLKPAG_SH) /* Inner Shareable */
 #define LX_BLKPAG_AP		__BIT(7)
-#define LX_BLKPAG_AP_RW		__SHIFTIN(0,LX_BLKPAG_AP) /* RW */
-#define LX_BLKPAG_AP_RO		__SHIFTIN(1,LX_BLKPAG_AP) /* RO */
+#define  LX_BLKPAG_AP_RW	__SHIFTIN(0,LX_BLKPAG_AP) /* RW */
+#define  LX_BLKPAG_AP_RO	__SHIFTIN(1,LX_BLKPAG_AP) /* RO */
 #define LX_BLKPAG_APUSER	__BIT(6)
 #define LX_BLKPAG_NS		__BIT(5)
 #define LX_BLKPAG_ATTR_INDX	__BITS(4,2)	/* refer MAIR_EL1 attr */
@@ -78,9 +78,9 @@ typedef uint64_t pt_entry_t;	/* L3(4k) t
 #define  LX_BLKPAG_ATTR_INDX_2	__SHIFTIN(2,LX_BLKPAG_ATTR_INDX)
 #define  LX_BLKPAG_ATTR_INDX_3	__SHIFTIN(3,LX_BLKPAG_ATTR_INDX)
 #define LX_TYPE			__BIT(1)
-#define LX_TYPE_BLK		__SHIFTIN(0, LX_TYPE)
-#define LX_TYPE_TBL		__SHIFTIN(1, LX_TYPE)
-#define L3_TYPE_PAG		__SHIFTIN(1, LX_TYPE)
+#define  LX_TYPE_BLK		__SHIFTIN(0, LX_TYPE)
+#define  LX_TYPE_TBL		__SHIFTIN(1, LX_TYPE)
+#define  L3_TYPE_PAG		__SHIFTIN(1, LX_TYPE)
 #define LX_VALID		__BIT(0)
 
 #define L1_BLK_OA		__BITS(47, 30)	/* 1GB */
@@ -130,57 +130,57 @@ typedef uint64_t pt_entry_t;	/* L3(4k) t
 
 
 /* TCR_EL1 - Translation Control Register */
-#define TCR_TBI1	__BIT(38)		/* ignore Top Byte TTBR1_EL1 */
-#define TCR_TBI0	__BIT(37)		/* ignore Top Byte TTBR0_EL1 */
-#define TCR_AS64K	__BIT(36)		/* Use 64K ASIDs */
-#define TCR_IPS		__BITS(34,32)		/* Intermediate PhysAdr Size */
-#define TCR_IPS_256TB	__SHIFTIN(5,TCR_IPS)	/* 48 bits (256 TB) */
-#define TCR_IPS_64TB	__SHIFTIN(4,TCR_IPS)	/* 44 bits  (16 TB) */
-#define TCR_IPS_4TB	__SHIFTIN(3,TCR_IPS)	/* 42 bits  ( 4 TB) */
-#define TCR_IPS_1TB	__SHIFTIN(2,TCR_IPS)	/* 40 bits  ( 1 TB) */
-#define TCR_IPS_64GB	__SHIFTIN(1,TCR_IPS)	/* 36 bits  (64 GB) */
-#define TCR_IPS_4GB	__SHIFTIN(0,TCR_IPS)	/* 32 bits   (4 GB) */
-#define TCR_TG1		__BITS(31,30)		/* TTBR1 Page Granule Size */
-#define TCR_TG1_16KB	__SHIFTIN(1,TCR_TG1)	/* 16KB page size */
-#define TCR_TG1_4KB	__SHIFTIN(2,TCR_TG1)	/* 4KB page size */
-#define TCR_TG1_64KB	__SHIFTIN(3,TCR_TG1)	/* 64KB page size */
-#define TCR_SH1		

CVS commit: src/sys/arch/aarch64/include

2019-08-15 Thread Nick Hudson
Module Name:src
Committed By:   skrll
Date:   Thu Aug 15 09:07:34 UTC 2019

Modified Files:
src/sys/arch/aarch64/include: pte.h

Log Message:
Indent the field value defines.  NFCI.


To generate a diff of this commit:
cvs rdiff -u -r1.6 -r1.7 src/sys/arch/aarch64/include/pte.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/aarch64/include

2019-08-13 Thread Nick Hudson
Module Name:src
Committed By:   skrll
Date:   Tue Aug 13 08:27:42 UTC 2019

Modified Files:
src/sys/arch/aarch64/include: pte.h

Log Message:
Add DBM


To generate a diff of this commit:
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/aarch64/include/pte.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/aarch64/include

2019-08-13 Thread Nick Hudson
Module Name:src
Committed By:   skrll
Date:   Tue Aug 13 08:27:42 UTC 2019

Modified Files:
src/sys/arch/aarch64/include: pte.h

Log Message:
Add DBM


To generate a diff of this commit:
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/aarch64/include/pte.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/aarch64/include/pte.h
diff -u src/sys/arch/aarch64/include/pte.h:1.5 src/sys/arch/aarch64/include/pte.h:1.6
--- src/sys/arch/aarch64/include/pte.h:1.5	Thu Oct  4 09:09:29 2018
+++ src/sys/arch/aarch64/include/pte.h	Tue Aug 13 08:27:42 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: pte.h,v 1.5 2018/10/04 09:09:29 ryo Exp $ */
+/* $NetBSD: pte.h,v 1.6 2019/08/13 08:27:42 skrll Exp $ */
 
 /*-
  * Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -58,6 +58,7 @@ typedef uint64_t pt_entry_t;	/* L3(4k) t
 #define LX_BLKPAG_UXN		__BIT(54)	/* Unprivileged Execute Never */
 #define LX_BLKPAG_PXN		__BIT(53)	/* Privileged Execute Never */
 #define LX_BLKPAG_CONTIG	__BIT(52)	/* Hint of TLB cache */
+#define LX_BLKPAG_DBM		__BIT(51)	/* Dirty Bit Modifier (V8.1) */
 #define LX_TBL_PA		__BITS(47, 12)
 #define LX_BLKPAG_OA		__BITS(47, 12)
 #define LX_BLKPAG_NG		__BIT(11)	/* Not Global */



CVS commit: src/sys/arch/aarch64/aarch64

2019-08-12 Thread Nick Hudson
Module Name:src
Committed By:   skrll
Date:   Mon Aug 12 15:47:02 UTC 2019

Modified Files:
src/sys/arch/aarch64/aarch64: efi_machdep.c

Log Message:
Trailing whitespace


To generate a diff of this commit:
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/aarch64/aarch64/efi_machdep.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/aarch64/aarch64

2019-08-12 Thread Nick Hudson
Module Name:src
Committed By:   skrll
Date:   Mon Aug 12 15:47:02 UTC 2019

Modified Files:
src/sys/arch/aarch64/aarch64: efi_machdep.c

Log Message:
Trailing whitespace


To generate a diff of this commit:
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/aarch64/aarch64/efi_machdep.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/aarch64/aarch64/efi_machdep.c
diff -u src/sys/arch/aarch64/aarch64/efi_machdep.c:1.3 src/sys/arch/aarch64/aarch64/efi_machdep.c:1.4
--- src/sys/arch/aarch64/aarch64/efi_machdep.c:1.3	Wed Oct 31 14:15:12 2018
+++ src/sys/arch/aarch64/aarch64/efi_machdep.c	Mon Aug 12 15:47:02 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: efi_machdep.c,v 1.3 2018/10/31 14:15:12 jmcneill Exp $ */
+/* $NetBSD: efi_machdep.c,v 1.4 2019/08/12 15:47:02 skrll Exp $ */
 
 /*-
  * Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
  */
 
 #include 
-__KERNEL_RCSID(0, "$NetBSD: efi_machdep.c,v 1.3 2018/10/31 14:15:12 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: efi_machdep.c,v 1.4 2019/08/12 15:47:02 skrll Exp $");
 
 #include 
 #include 
@@ -40,7 +40,7 @@ __KERNEL_RCSID(0, "$NetBSD: efi_machdep.
 
 void
 arm_efirt_md_map_range(vaddr_t va, paddr_t pa, size_t sz, enum arm_efirt_mem_type type)
-{   
+{
 	pt_entry_t attr;
 
 	switch (type) {



CVS commit: src/sys/arch/aarch64

2019-08-12 Thread Nick Hudson
Module Name:src
Committed By:   skrll
Date:   Mon Aug 12 10:28:04 UTC 2019

Modified Files:
src/sys/arch/aarch64/aarch64: pmap.c
src/sys/arch/aarch64/include: pmap.h

Log Message:
Use PMAP_DEV in DEVMAP_ENTRY rather than pmap_map_chunk.  It's clearer and
means pmap_map_chunk can be made to map other memory types.


To generate a diff of this commit:
cvs rdiff -u -r1.41 -r1.42 src/sys/arch/aarch64/aarch64/pmap.c
cvs rdiff -u -r1.24 -r1.25 src/sys/arch/aarch64/include/pmap.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/aarch64/aarch64/pmap.c
diff -u src/sys/arch/aarch64/aarch64/pmap.c:1.41 src/sys/arch/aarch64/aarch64/pmap.c:1.42
--- src/sys/arch/aarch64/aarch64/pmap.c:1.41	Fri May 17 06:05:07 2019
+++ src/sys/arch/aarch64/aarch64/pmap.c	Mon Aug 12 10:28:04 2019
@@ -1,4 +1,4 @@
-/*	$NetBSD: pmap.c,v 1.41 2019/05/17 06:05:07 mrg Exp $	*/
+/*	$NetBSD: pmap.c,v 1.42 2019/08/12 10:28:04 skrll Exp $	*/
 
 /*
  * Copyright (c) 2017 Ryo Shimizu 
@@ -27,7 +27,7 @@
  */
 
 #include 
-__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.41 2019/05/17 06:05:07 mrg Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.42 2019/08/12 10:28:04 skrll Exp $");
 
 #include "opt_arm_debug.h"
 #include "opt_ddb.h"
@@ -283,7 +283,7 @@ pmap_map_chunk(vaddr_t va, paddr_t pa, v
 	blocksize = L2_SIZE;
 
 	attr = _pmap_pte_adjust_prot(L2_BLOCK, prot, VM_PROT_ALL, false);
-	attr = _pmap_pte_adjust_cacheflags(attr, flags | PMAP_DEV);
+	attr = _pmap_pte_adjust_cacheflags(attr, flags);
 	/* user cannot execute, and kernel follows the prot */
 	attr |= (LX_BLKPAG_UXN|LX_BLKPAG_PXN);
 	if (prot & VM_PROT_EXECUTE)

Index: src/sys/arch/aarch64/include/pmap.h
diff -u src/sys/arch/aarch64/include/pmap.h:1.24 src/sys/arch/aarch64/include/pmap.h:1.25
--- src/sys/arch/aarch64/include/pmap.h:1.24	Mon Apr  8 21:18:22 2019
+++ src/sys/arch/aarch64/include/pmap.h	Mon Aug 12 10:28:04 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: pmap.h,v 1.24 2019/04/08 21:18:22 ryo Exp $ */
+/* $NetBSD: pmap.h,v 1.25 2019/08/12 10:28:04 skrll Exp $ */
 
 /*-
  * Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -207,7 +207,7 @@ paddr_t pmap_alloc_pdp(struct pmap *, st
 		.pd_pa = DEVMAP_TRUNC_ADDR(pa),		\
 		.pd_size = DEVMAP_ROUND_SIZE(sz),	\
 		.pd_prot = VM_PROT_READ|VM_PROT_WRITE,	\
-		.pd_flags = PMAP_NOCACHE		\
+		.pd_flags = PMAP_DEV			\
 	}
 #define	DEVMAP_ENTRY_END	{ 0 }
 



CVS commit: src/sys/arch/aarch64

2019-08-12 Thread Nick Hudson
Module Name:src
Committed By:   skrll
Date:   Mon Aug 12 10:28:04 UTC 2019

Modified Files:
src/sys/arch/aarch64/aarch64: pmap.c
src/sys/arch/aarch64/include: pmap.h

Log Message:
Use PMAP_DEV in DEVMAP_ENTRY rather than pmap_map_chunk.  It's clearer and
means pmap_map_chunk can be made to map other memory types.


To generate a diff of this commit:
cvs rdiff -u -r1.41 -r1.42 src/sys/arch/aarch64/aarch64/pmap.c
cvs rdiff -u -r1.24 -r1.25 src/sys/arch/aarch64/include/pmap.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/aarch64/include

2019-08-10 Thread Nick Hudson
Module Name:src
Committed By:   skrll
Date:   Sat Aug 10 16:46:07 UTC 2019

Modified Files:
src/sys/arch/aarch64/include: bus_funcs.h

Log Message:
Really provide bus_funcs.h


To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/aarch64/include/bus_funcs.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/aarch64/include

2019-08-10 Thread Nick Hudson
Module Name:src
Committed By:   skrll
Date:   Sat Aug 10 16:46:07 UTC 2019

Modified Files:
src/sys/arch/aarch64/include: bus_funcs.h

Log Message:
Really provide bus_funcs.h


To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/aarch64/include/bus_funcs.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/aarch64/include/bus_funcs.h
diff -u src/sys/arch/aarch64/include/bus_funcs.h:1.2 src/sys/arch/aarch64/include/bus_funcs.h:1.3
--- src/sys/arch/aarch64/include/bus_funcs.h:1.2	Sun Apr  1 04:35:03 2018
+++ src/sys/arch/aarch64/include/bus_funcs.h	Sat Aug 10 16:46:07 2019
@@ -1,3 +1,3 @@
-/*	$NetBSD: bus_funcs.h,v 1.2 2018/04/01 04:35:03 ryo Exp $	*/
+/*	$NetBSD: bus_funcs.h,v 1.3 2019/08/10 16:46:07 skrll Exp $	*/
 
-#include 
+#include 



CVS commit: src/sys/arch/aarch64/aarch64

2019-08-07 Thread Jared D. McNeill
Module Name:src
Committed By:   jmcneill
Date:   Wed Aug  7 09:49:40 UTC 2019

Modified Files:
src/sys/arch/aarch64/aarch64: trap.c

Log Message:
trap_el0_32sync: add missing break to ESR_EC_FP_TRAP_A32 case


To generate a diff of this commit:
cvs rdiff -u -r1.17 -r1.18 src/sys/arch/aarch64/aarch64/trap.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



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