On Wed, Sep 11, 2024 at 05:17:45 +, matthew green wrote:
> Module Name: src
> Committed By: mrg
> Date: Wed Sep 11 05:17:45 UTC 2024
>
> Modified Files:
> src/sys/arch/x86/x86: intr.c
>
> Log Message:
> apply some more diagnostic checks for x86 interrupts
How does this mix wi
Module Name:src
Committed By: mrg
Date: Wed Sep 11 05:17:45 UTC 2024
Modified Files:
src/sys/arch/x86/x86: intr.c
Log Message:
apply some more diagnostic checks for x86 interrupts
convert intr_biglock_wrapper() into a slight less complete
intr_wrapper(), and move the kern
Module Name:src
Committed By: mrg
Date: Wed Sep 11 05:17:45 UTC 2024
Modified Files:
src/sys/arch/x86/x86: intr.c
Log Message:
apply some more diagnostic checks for x86 interrupts
convert intr_biglock_wrapper() into a slight less complete
intr_wrapper(), and move the kern
Module Name:src
Committed By: riastradh
Date: Thu Aug 1 11:18:54 UTC 2024
Modified Files:
src/sys/arch/x86/x86: cpu_rng.c
Log Message:
x86/cpu_rng.c: Archive more links.
Why do major hardware manufacturers consistently seem to think links
should just stop working after a
Module Name:src
Committed By: riastradh
Date: Thu Aug 1 11:18:54 UTC 2024
Modified Files:
src/sys/arch/x86/x86: cpu_rng.c
Log Message:
x86/cpu_rng.c: Archive more links.
Why do major hardware manufacturers consistently seem to think links
should just stop working after a
Module Name:src
Committed By: riastradh
Date: Wed Jul 31 22:44:49 UTC 2024
Modified Files:
src/sys/arch/x86/x86: cpu_rng.c
Log Message:
x86/cpu_rng.c: Add reference for Intel's hardware design.
Not normative, unverifiable, possibly outdated -- but still a useful
descripti
Module Name:src
Committed By: riastradh
Date: Wed Jul 31 22:44:49 UTC 2024
Modified Files:
src/sys/arch/x86/x86: cpu_rng.c
Log Message:
x86/cpu_rng.c: Add reference for Intel's hardware design.
Not normative, unverifiable, possibly outdated -- but still a useful
descripti
Module Name:src
Committed By: gutteridge
Date: Mon Jul 15 01:57:23 UTC 2024
Modified Files:
src/sys/arch/x86/x86: coretemp.c
Log Message:
coretemp.c: drop redundant condition (NFCI)
Checking for a processor model upper limit has no point inside a block
that is already lim
Module Name:src
Committed By: gutteridge
Date: Mon Jul 15 01:57:23 UTC 2024
Modified Files:
src/sys/arch/x86/x86: coretemp.c
Log Message:
coretemp.c: drop redundant condition (NFCI)
Checking for a processor model upper limit has no point inside a block
that is already lim
Module Name:src
Committed By: andvar
Date: Mon Jul 1 19:40:03 UTC 2024
Modified Files:
src/sys/arch/x86/include: specialreg.h
src/sys/arch/x86/x86: identcpu.c
Log Message:
Disable the VIA Alternate Instructions according the VIA documentation:
* C7 and above do no
Module Name:src
Committed By: andvar
Date: Mon Jul 1 19:40:03 UTC 2024
Modified Files:
src/sys/arch/x86/include: specialreg.h
src/sys/arch/x86/x86: identcpu.c
Log Message:
Disable the VIA Alternate Instructions according the VIA documentation:
* C7 and above do no
Module Name:src
Committed By: andvar
Date: Sun Jun 30 15:49:56 UTC 2024
Modified Files:
src/sys/arch/x86/x86: identcpu.c
Log Message:
Move determination of the largest VIA CPU extended function value
to the intended place where the checks are performed.
Currently the valu
Module Name:src
Committed By: andvar
Date: Sun Jun 30 15:49:56 UTC 2024
Modified Files:
src/sys/arch/x86/x86: identcpu.c
Log Message:
Move determination of the largest VIA CPU extended function value
to the intended place where the checks are performed.
Currently the valu
Module Name:src
Committed By: riastradh
Date: Fri Jun 21 17:24:08 UTC 2024
Modified Files:
src/sys/arch/x86/x86: fpu.c
Log Message:
x86/fpu.c: Nix trailing whitespace.
No functional change intended.
To generate a diff of this commit:
cvs rdiff -u -r1.88 -r1.89 src/sys/a
Module Name:src
Committed By: riastradh
Date: Fri Jun 21 17:24:08 UTC 2024
Modified Files:
src/sys/arch/x86/x86: fpu.c
Log Message:
x86/fpu.c: Nix trailing whitespace.
No functional change intended.
To generate a diff of this commit:
cvs rdiff -u -r1.88 -r1.89 src/sys/a
Module Name:src
Committed By: riastradh
Date: Sun Jun 9 20:07:33 UTC 2024
Modified Files:
src/sys/arch/x86/x86: cpu_rng.c
Log Message:
x86/cpu_rng: Fix false alarm rate of CPU RNG health test.
Lower it from 1/2^32 (about one in four billion) to 1/2^256
(approximately not
Module Name:src
Committed By: riastradh
Date: Sun Jun 9 20:07:33 UTC 2024
Modified Files:
src/sys/arch/x86/x86: cpu_rng.c
Log Message:
x86/cpu_rng: Fix false alarm rate of CPU RNG health test.
Lower it from 1/2^32 (about one in four billion) to 1/2^256
(approximately not
Module Name:src
Committed By: riastradh
Date: Tue Jun 4 21:42:58 UTC 2024
Modified Files:
src/sys/arch/x86/x86: bus_dma.c
Log Message:
x86: Teach bus_dmamem_map about BUS_DMA_PREFETCHABLE.
PR port-amd64/58308
To generate a diff of this commit:
cvs rdiff -u -r1.90 -r1.9
Module Name:src
Committed By: riastradh
Date: Tue Jun 4 21:42:58 UTC 2024
Modified Files:
src/sys/arch/x86/x86: bus_dma.c
Log Message:
x86: Teach bus_dmamem_map about BUS_DMA_PREFETCHABLE.
PR port-amd64/58308
To generate a diff of this commit:
cvs rdiff -u -r1.90 -r1.9
Module Name:src
Committed By: manu
Date: Fri May 17 00:37:14 UTC 2024
Modified Files:
src/sys/arch/x86/x86: fpu.c
Log Message:
iWorkaround panic: fpudna from userland
i386 Xen PV domU get spurious fpudna traps from userland. Older eager FPU
contact switching code took car
Module Name:src
Committed By: manu
Date: Fri May 17 00:37:14 UTC 2024
Modified Files:
src/sys/arch/x86/x86: fpu.c
Log Message:
iWorkaround panic: fpudna from userland
i386 Xen PV domU get spurious fpudna traps from userland. Older eager FPU
contact switching code took car
Module Name:src
Committed By: msaitoh
Date: Sun May 12 23:41:10 UTC 2024
Modified Files:
src/sys/arch/x86/include: specialreg.h
Log Message:
s/RPMQUERY/RMPQUERY/
To generate a diff of this commit:
cvs rdiff -u -r1.210 -r1.211 src/sys/arch/x86/include/specialreg.h
Please
Module Name:src
Committed By: msaitoh
Date: Sun May 12 23:41:10 UTC 2024
Modified Files:
src/sys/arch/x86/include: specialreg.h
Log Message:
s/RPMQUERY/RMPQUERY/
To generate a diff of this commit:
cvs rdiff -u -r1.210 -r1.211 src/sys/arch/x86/include/specialreg.h
Please
Module Name:src
Committed By: andvar
Date: Mon Apr 29 21:29:48 UTC 2024
Modified Files:
src/sys/arch/x86/pci: dwiic_pci.c
Log Message:
Make dwiic_pci compile without ACPI option.
To generate a diff of this commit:
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/x86/pci/dwiic_pci.
Module Name:src
Committed By: andvar
Date: Mon Apr 29 21:29:48 UTC 2024
Modified Files:
src/sys/arch/x86/pci: dwiic_pci.c
Log Message:
Make dwiic_pci compile without ACPI option.
To generate a diff of this commit:
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/x86/pci/dwiic_pci.
Module Name:src
Committed By: andvar
Date: Mon Apr 22 23:07:47 UTC 2024
Modified Files:
src/sys/arch/x86/x86: cpu.c
Log Message:
Surround full mp_cpu_start() method with NLAPIC > 0 guard.
Initialization is based on x86_ipi* functions, which are implemented only
when lapic
Module Name:src
Committed By: andvar
Date: Mon Apr 22 23:07:47 UTC 2024
Modified Files:
src/sys/arch/x86/x86: cpu.c
Log Message:
Surround full mp_cpu_start() method with NLAPIC > 0 guard.
Initialization is based on x86_ipi* functions, which are implemented only
when lapic
Module Name:src
Committed By: andvar
Date: Mon Apr 22 22:29:29 UTC 2024
Modified Files:
src/sys/arch/x86/x86: intr.c
Log Message:
Add opt_pci.h include to fix NO_PCI_MSI_MSIX build.
(Path from Paolo Pisati in current_users@)
While here:
Simplify mp_cpu_start() ifdefs. MUL
Module Name:src
Committed By: andvar
Date: Mon Apr 22 22:29:29 UTC 2024
Modified Files:
src/sys/arch/x86/x86: intr.c
Log Message:
Add opt_pci.h include to fix NO_PCI_MSI_MSIX build.
(Path from Paolo Pisati in current_users@)
While here:
Simplify mp_cpu_start() ifdefs. MUL
Module Name:src
Committed By: andvar
Date: Sat Apr 13 09:12:09 UTC 2024
Modified Files:
src/sys/arch/x86/x86: viac7temp.c
Log Message:
viac7temp(4): define module metadata using MODULE() macro and implement
viac7temp_modcmd() to handle module load/unload events.
Fixes PR
Module Name:src
Committed By: andvar
Date: Sat Apr 13 09:12:09 UTC 2024
Modified Files:
src/sys/arch/x86/x86: viac7temp.c
Log Message:
viac7temp(4): define module metadata using MODULE() macro and implement
viac7temp_modcmd() to handle module load/unload events.
Fixes PR
Module Name:src
Committed By: gutteridge
Date: Tue Mar 12 02:26:16 UTC 2024
Modified Files:
src/sys/arch/x86/x86: coretemp.c
Log Message:
coretemp.c: don't accept impossibly low TjMax values
r. 1.39 introduced a regression where instead of applying a reasonable
default ma
Module Name:src
Committed By: gutteridge
Date: Tue Mar 12 02:26:16 UTC 2024
Modified Files:
src/sys/arch/x86/x86: coretemp.c
Log Message:
coretemp.c: don't accept impossibly low TjMax values
r. 1.39 introduced a regression where instead of applying a reasonable
default ma
Module Name:src
Committed By: gutteridge
Date: Thu Feb 29 01:59:12 UTC 2024
Modified Files:
src/sys/arch/x86/x86: coretemp.c
Log Message:
coretemp.c: fix grammar in a warning message
(I get several of these warnings on boot on a particular machine. Now,
it also seems that
Module Name:src
Committed By: gutteridge
Date: Thu Feb 29 01:59:12 UTC 2024
Modified Files:
src/sys/arch/x86/x86: coretemp.c
Log Message:
coretemp.c: fix grammar in a warning message
(I get several of these warnings on boot on a particular machine. Now,
it also seems that
Module Name:src
Committed By: andvar
Date: Sun Feb 25 18:27:54 UTC 2024
Modified Files:
src/sys/arch/x86/x86: lapic.c
Log Message:
s/asynchronious/asynchronous/ in comment.
To generate a diff of this commit:
cvs rdiff -u -r1.89 -r1.90 src/sys/arch/x86/x86/lapic.c
Please
Module Name:src
Committed By: andvar
Date: Sun Feb 25 18:27:54 UTC 2024
Modified Files:
src/sys/arch/x86/x86: lapic.c
Log Message:
s/asynchronious/asynchronous/ in comment.
To generate a diff of this commit:
cvs rdiff -u -r1.89 -r1.90 src/sys/arch/x86/x86/lapic.c
Please
Module Name:src
Committed By: mrg
Date: Mon Feb 19 20:10:09 UTC 2024
Modified Files:
src/sys/arch/x86/x86: tsc.c
Log Message:
remove unintended printf() in previous. (thx dh)
To generate a diff of this commit:
cvs rdiff -u -r1.59 -r1.60 src/sys/arch/x86/x86/tsc.c
Pleas
Module Name:src
Committed By: mrg
Date: Mon Feb 19 20:10:09 UTC 2024
Modified Files:
src/sys/arch/x86/x86: tsc.c
Log Message:
remove unintended printf() in previous. (thx dh)
To generate a diff of this commit:
cvs rdiff -u -r1.59 -r1.60 src/sys/arch/x86/x86/tsc.c
Pleas
Module Name:src
Committed By: mrg
Date: Mon Feb 19 09:22:31 UTC 2024
Modified Files:
src/sys/arch/x86/x86: tsc.c
Log Message:
make TSC get a quality of -100 on AMD Family 15h and 16h
this should "fix" PR#56322 and is known as AMD errata
"778: Processor Core Time Stamp Cou
Module Name:src
Committed By: mrg
Date: Mon Feb 19 09:22:31 UTC 2024
Modified Files:
src/sys/arch/x86/x86: tsc.c
Log Message:
make TSC get a quality of -100 on AMD Family 15h and 16h
this should "fix" PR#56322 and is known as AMD errata
"778: Processor Core Time Stamp Cou
Module Name:src
Committed By: christos
Date: Tue Jan 2 19:28:25 UTC 2024
Modified Files:
src/sys/arch/x86/include: ieee.h
Log Message:
use sized types
To generate a diff of this commit:
cvs rdiff -u -r1.12 -r1.13 src/sys/arch/x86/include/ieee.h
Please note that diffs a
Module Name:src
Committed By: christos
Date: Tue Jan 2 19:28:25 UTC 2024
Modified Files:
src/sys/arch/x86/include: ieee.h
Log Message:
use sized types
To generate a diff of this commit:
cvs rdiff -u -r1.12 -r1.13 src/sys/arch/x86/include/ieee.h
Please note that diffs a
Module Name:src
Committed By: mlelstv
Date: Wed Nov 29 11:40:37 UTC 2023
Modified Files:
src/sys/arch/x86/x86: intr.c
Log Message:
Fix use-after-free (source->is_type) when detecting unsharable
interrupts. Doesn't solve the interrupt conflict itself, but
avoids a panic.
Module Name:src
Committed By: gutteridge
Date: Tue Nov 21 23:22:23 UTC 2023
Modified Files:
src/sys/arch/x86/pci: pci_machdep.c pci_msi_machdep.c
Log Message:
pci_machdep.c & pci_msi_machdep.c: comment fixes
Correct spelling and grammar in some comments.
To generate a d
Module Name:src
Committed By: gutteridge
Date: Tue Nov 21 23:22:23 UTC 2023
Modified Files:
src/sys/arch/x86/pci: pci_machdep.c pci_msi_machdep.c
Log Message:
pci_machdep.c & pci_msi_machdep.c: comment fixes
Correct spelling and grammar in some comments.
To generate a d
Module Name:src
Committed By: mrg
Date: Fri Oct 27 06:31:49 UTC 2023
Modified Files:
src/sys/arch/x86/include: specialreg.h
Log Message:
add MSR stuff for AMD errata 1474.
To generate a diff of this commit:
cvs rdiff -u -r1.208 -r1.209 src/sys/arch/x86/include/specialreg
Module Name:src
Committed By: mrg
Date: Fri Oct 27 06:31:49 UTC 2023
Modified Files:
src/sys/arch/x86/include: specialreg.h
Log Message:
add MSR stuff for AMD errata 1474.
To generate a diff of this commit:
cvs rdiff -u -r1.208 -r1.209 src/sys/arch/x86/include/specialreg
Module Name:src
Committed By: mrg
Date: Fri Oct 27 05:45:00 UTC 2023
Modified Files:
src/sys/arch/x86/x86: errata.c
Log Message:
x86: handle AMD errata 1474: A CPU core may hang after about 1044 days
from the new comment:
* This requires disabling CC6 power level, which
Module Name:src
Committed By: mrg
Date: Fri Oct 27 05:45:00 UTC 2023
Modified Files:
src/sys/arch/x86/x86: errata.c
Log Message:
x86: handle AMD errata 1474: A CPU core may hang after about 1044 days
from the new comment:
* This requires disabling CC6 power level, which
Module Name:src
Committed By: mrg
Date: Fri Oct 27 03:06:04 UTC 2023
Modified Files:
src/sys/arch/x86/x86: errata.c
Log Message:
x86: add names for errata that don't have actual numbers
zenbleed is reported as "erratum 65535" currently, this adds a name
for it, and enable
Module Name:src
Committed By: mrg
Date: Fri Oct 27 03:06:04 UTC 2023
Modified Files:
src/sys/arch/x86/x86: errata.c
Log Message:
x86: add names for errata that don't have actual numbers
zenbleed is reported as "erratum 65535" currently, this adds a name
for it, and enable
Module Name:src
Committed By: bouyer
Date: Thu Oct 19 14:59:46 UTC 2023
Modified Files:
src/sys/arch/x86/acpi: acpi_wakeup.c
src/sys/arch/x86/x86: genfb_machdep.c
Log Message:
Move definition of acpi_md_vesa_modenum to acpi_wakeup.c; allows building
kernels without
Module Name:src
Committed By: bouyer
Date: Thu Oct 19 14:59:46 UTC 2023
Modified Files:
src/sys/arch/x86/acpi: acpi_wakeup.c
src/sys/arch/x86/x86: genfb_machdep.c
Log Message:
Move definition of acpi_md_vesa_modenum to acpi_wakeup.c; allows building
kernels without
Module Name:src
Committed By: riastradh
Date: Tue Oct 17 14:17:42 UTC 2023
Modified Files:
src/sys/arch/x86/x86: identcpu.c
Log Message:
Revert "x86: Panic early if fpu save size is too large, take 2."
Apparently this is too early to print anything useful, so it just
caus
Module Name:src
Committed By: riastradh
Date: Tue Oct 17 14:17:42 UTC 2023
Modified Files:
src/sys/arch/x86/x86: identcpu.c
Log Message:
Revert "x86: Panic early if fpu save size is too large, take 2."
Apparently this is too early to print anything useful, so it just
caus
Module Name:src
Committed By: riastradh
Date: Tue Oct 17 11:12:33 UTC 2023
Modified Files:
src/sys/arch/x86/x86: identcpu.c
Log Message:
x86: Panic early if fpu save size is too large, take 2.
This shouldn't break any existing systems (for real this time), but
it should m
Module Name:src
Committed By: riastradh
Date: Tue Oct 17 11:12:33 UTC 2023
Modified Files:
src/sys/arch/x86/x86: identcpu.c
Log Message:
x86: Panic early if fpu save size is too large, take 2.
This shouldn't break any existing systems (for real this time), but
it should m
Module Name:src
Committed By: riastradh
Date: Tue Oct 17 11:11:49 UTC 2023
Modified Files:
src/sys/arch/x86/x86: identcpu.c
Log Message:
x86: Remove incomplete fpu save size check.
Will fix it later, but this makes pullups easier.
To generate a diff of this commit:
cvs
Module Name:src
Committed By: riastradh
Date: Tue Oct 17 11:11:49 UTC 2023
Modified Files:
src/sys/arch/x86/x86: identcpu.c
Log Message:
x86: Remove incomplete fpu save size check.
Will fix it later, but this makes pullups easier.
To generate a diff of this commit:
cvs
Module Name:src
Committed By: bouyer
Date: Mon Oct 16 17:27:03 UTC 2023
Modified Files:
src/sys/arch/x86/acpi: acpi_machdep.c acpi_wakeup.c
src/sys/arch/x86/include: genfb_machdep.h
src/sys/arch/x86/pci: pci_machdep.c
src/sys/arch/x86/x86: genfb_mach
Module Name:src
Committed By: bouyer
Date: Mon Oct 16 17:27:03 UTC 2023
Modified Files:
src/sys/arch/x86/acpi: acpi_machdep.c acpi_wakeup.c
src/sys/arch/x86/include: genfb_machdep.h
src/sys/arch/x86/pci: pci_machdep.c
src/sys/arch/x86/x86: genfb_mach
Module Name:src
Committed By: riastradh
Date: Sun Oct 15 16:11:22 UTC 2023
Modified Files:
src/sys/arch/x86/x86: identcpu.c
Log Message:
x86: Disable savefpu size check for now.
This is apparently so broken that the error check for what should
have been a safe size fails,
Module Name:src
Committed By: riastradh
Date: Sun Oct 15 16:11:22 UTC 2023
Modified Files:
src/sys/arch/x86/x86: identcpu.c
Log Message:
x86: Disable savefpu size check for now.
This is apparently so broken that the error check for what should
have been a safe size fails,
Module Name:src
Committed By: riastradh
Date: Sun Oct 15 13:13:22 UTC 2023
Modified Files:
src/sys/arch/x86/x86: identcpu.c
Log Message:
x86: Panic if cpuid's fpu save size is larger than we support.
Ideally this wouldn't panic, but the alternative right now is to
crash i
Module Name:src
Committed By: riastradh
Date: Sun Oct 15 13:13:22 UTC 2023
Modified Files:
src/sys/arch/x86/x86: identcpu.c
Log Message:
x86: Panic if cpuid's fpu save size is larger than we support.
Ideally this wouldn't panic, but the alternative right now is to
crash i
Module Name:src
Committed By: christos
Date: Sat Sep 16 13:37:10 UTC 2023
Modified Files:
src/sys/arch/x86/include: ieee.h
Log Message:
protect against multiple inclusion
To generate a diff of this commit:
cvs rdiff -u -r1.11 -r1.12 src/sys/arch/x86/include/ieee.h
Pleas
Module Name:src
Committed By: christos
Date: Sat Sep 16 13:37:10 UTC 2023
Modified Files:
src/sys/arch/x86/include: ieee.h
Log Message:
protect against multiple inclusion
To generate a diff of this commit:
cvs rdiff -u -r1.11 -r1.12 src/sys/arch/x86/include/ieee.h
Pleas
Module Name:src
Committed By: ad
Date: Sat Sep 9 18:37:03 UTC 2023
Modified Files:
src/sys/arch/x86/x86: tsc.c
Log Message:
tsc_get_timecount(): cover the backwards check by DIAGNOSTIC since it has
proven the point by now.
To generate a diff of this commit:
cvs rdiff -u
Module Name:src
Committed By: ad
Date: Sat Sep 9 18:37:03 UTC 2023
Modified Files:
src/sys/arch/x86/x86: tsc.c
Log Message:
tsc_get_timecount(): cover the backwards check by DIAGNOSTIC since it has
proven the point by now.
To generate a diff of this commit:
cvs rdiff -u
Module Name:src
Committed By: msaitoh
Date: Mon Aug 7 09:27:14 UTC 2023
Modified Files:
src/sys/arch/x86/x86: procfs_machdep.c
Log Message:
Update /proc/cpuinfo.
- Move "ssbd" to an unused Linux mapping.
- Update unused Linux mappings.
To generate a diff of this comm
Module Name:src
Committed By: msaitoh
Date: Mon Aug 7 09:27:14 UTC 2023
Modified Files:
src/sys/arch/x86/x86: procfs_machdep.c
Log Message:
Update /proc/cpuinfo.
- Move "ssbd" to an unused Linux mapping.
- Update unused Linux mappings.
To generate a diff of this comm
Module Name:src
Committed By: msaitoh
Date: Mon Aug 7 06:23:40 UTC 2023
Modified Files:
src/sys/arch/x86/pci: pci_machdep.c
Log Message:
Fix detection of availability of MSI/MSI-X on some systems.
Try to find all functions on bus 0, device 0 to find a PCI host bridge.
So
Module Name:src
Committed By: msaitoh
Date: Mon Aug 7 06:23:40 UTC 2023
Modified Files:
src/sys/arch/x86/pci: pci_machdep.c
Log Message:
Fix detection of availability of MSI/MSI-X on some systems.
Try to find all functions on bus 0, device 0 to find a PCI host bridge.
So
Module Name:src
Committed By: mrg
Date: Fri Jul 28 05:02:13 UTC 2023
Modified Files:
src/sys/arch/x86/x86: errata.c
Log Message:
x86: make the CPUID list for errata be far less confusing
the 0x8001 CPUID result needs some parsing to match against
actual family/model/s
Module Name:src
Committed By: mrg
Date: Fri Jul 28 05:02:13 UTC 2023
Modified Files:
src/sys/arch/x86/x86: errata.c
Log Message:
x86: make the CPUID list for errata be far less confusing
the 0x8001 CPUID result needs some parsing to match against
actual family/model/s
Module Name:src
Committed By: msaitoh
Date: Fri Jul 28 02:28:33 UTC 2023
Modified Files:
src/sys/arch/x86/pci: amdsmn.c
Log Message:
Add Zen4 Phoenix support.
To generate a diff of this commit:
cvs rdiff -u -r1.16 -r1.17 src/sys/arch/x86/pci/amdsmn.c
Please note that di
Module Name:src
Committed By: msaitoh
Date: Fri Jul 28 02:28:33 UTC 2023
Modified Files:
src/sys/arch/x86/pci: amdsmn.c
Log Message:
Add Zen4 Phoenix support.
To generate a diff of this commit:
cvs rdiff -u -r1.16 -r1.17 src/sys/arch/x86/pci/amdsmn.c
Please note that di
Module Name:src
Committed By: msaitoh
Date: Fri Jul 28 02:05:26 UTC 2023
Modified Files:
src/sys/arch/x86/pci: amdzentemp.c
Log Message:
Add Zen2 Mendocino APU support.
To generate a diff of this commit:
cvs rdiff -u -r1.19 -r1.20 src/sys/arch/x86/pci/amdzentemp.c
Pleas
Module Name:src
Committed By: msaitoh
Date: Fri Jul 28 02:05:26 UTC 2023
Modified Files:
src/sys/arch/x86/pci: amdzentemp.c
Log Message:
Add Zen2 Mendocino APU support.
To generate a diff of this commit:
cvs rdiff -u -r1.19 -r1.20 src/sys/arch/x86/pci/amdzentemp.c
Pleas
Module Name:src
Committed By: msaitoh
Date: Fri Jul 28 00:11:15 UTC 2023
Modified Files:
src/sys/arch/x86/pci: amdzentemp.c
Log Message:
Add Zen4 Ryzen "Phoenix" support.
To generate a diff of this commit:
cvs rdiff -u -r1.18 -r1.19 src/sys/arch/x86/pci/amdzentemp.c
Ple
Module Name:src
Committed By: msaitoh
Date: Fri Jul 28 00:11:15 UTC 2023
Modified Files:
src/sys/arch/x86/pci: amdzentemp.c
Log Message:
Add Zen4 Ryzen "Phoenix" support.
To generate a diff of this commit:
cvs rdiff -u -r1.18 -r1.19 src/sys/arch/x86/pci/amdzentemp.c
Ple
Module Name:src
Committed By: msaitoh
Date: Thu Jul 27 00:34:07 UTC 2023
Modified Files:
src/sys/arch/x86/include: specialreg.h
Log Message:
Add AMD IBPB_RET and BusLockThreshold.
To generate a diff of this commit:
cvs rdiff -u -r1.207 -r1.208 src/sys/arch/x86/include/sp
Module Name:src
Committed By: msaitoh
Date: Thu Jul 27 00:34:07 UTC 2023
Modified Files:
src/sys/arch/x86/include: specialreg.h
Log Message:
Add AMD IBPB_RET and BusLockThreshold.
To generate a diff of this commit:
cvs rdiff -u -r1.207 -r1.208 src/sys/arch/x86/include/sp
Module Name:src
Committed By: riastradh
Date: Wed Jul 26 21:45:29 UTC 2023
Modified Files:
src/sys/arch/x86/x86: pmap.c
Log Message:
x86/pmap: Print quantities in failed assertions in pmap_load.
To generate a diff of this commit:
cvs rdiff -u -r1.424 -r1.425 src/sys/arch
Module Name:src
Committed By: riastradh
Date: Wed Jul 26 21:45:29 UTC 2023
Modified Files:
src/sys/arch/x86/x86: pmap.c
Log Message:
x86/pmap: Print quantities in failed assertions in pmap_load.
To generate a diff of this commit:
cvs rdiff -u -r1.424 -r1.425 src/sys/arch
Module Name:src
Committed By: mrg
Date: Wed Jul 26 00:19:04 UTC 2023
Modified Files:
src/sys/arch/x86/x86: errata.c
Log Message:
fix the cpuids for the zen2 client CPUs.
i'm not exactly how i came up with the values i had, though one
of them was still valid and matched my
Module Name:src
Committed By: mrg
Date: Wed Jul 26 00:19:04 UTC 2023
Modified Files:
src/sys/arch/x86/x86: errata.c
Log Message:
fix the cpuids for the zen2 client CPUs.
i'm not exactly how i came up with the values i had, though one
of them was still valid and matched my
Module Name:src
Committed By: mrg
Date: Tue Jul 25 01:09:05 UTC 2023
Modified Files:
src/sys/arch/x86/include: specialreg.h
src/sys/arch/x86/x86: errata.c
Log Message:
x86: turn off zenbleed chicken bit on Zen2 cpus.
this is based upon Taylor's original work. i j
Module Name:src
Committed By: mrg
Date: Tue Jul 25 01:09:05 UTC 2023
Modified Files:
src/sys/arch/x86/include: specialreg.h
src/sys/arch/x86/x86: errata.c
Log Message:
x86: turn off zenbleed chicken bit on Zen2 cpus.
this is based upon Taylor's original work. i j
Module Name:src
Committed By: riastradh
Date: Mon Jul 24 23:42:00 UTC 2023
Modified Files:
src/sys/arch/x86/x86: errata.c
Log Message:
x86/errata.c: Only say the errata revision search for cpu0.
To generate a diff of this commit:
cvs rdiff -u -r1.29 -r1.30 src/sys/arch/x
Module Name:src
Committed By: riastradh
Date: Mon Jul 24 23:42:00 UTC 2023
Modified Files:
src/sys/arch/x86/x86: errata.c
Log Message:
x86/errata.c: Only say the errata revision search for cpu0.
To generate a diff of this commit:
cvs rdiff -u -r1.29 -r1.30 src/sys/arch/x
Module Name:src
Committed By: riastradh
Date: Mon Jul 24 22:21:09 UTC 2023
Modified Files:
src/sys/arch/x86/x86: errata.c
Log Message:
x86/errata.c: Say what revision we're searching for.
To generate a diff of this commit:
cvs rdiff -u -r1.28 -r1.29 src/sys/arch/x86/x86/
Module Name:src
Committed By: riastradh
Date: Mon Jul 24 22:21:09 UTC 2023
Modified Files:
src/sys/arch/x86/x86: errata.c
Log Message:
x86/errata.c: Say what revision we're searching for.
To generate a diff of this commit:
cvs rdiff -u -r1.28 -r1.29 src/sys/arch/x86/x86/
Module Name:src
Committed By: riastradh
Date: Mon Jul 24 22:20:53 UTC 2023
Modified Files:
src/sys/arch/x86/x86: errata.c
Log Message:
x86/errata.c: Link to original AMD errata guide.
This one is no longer updated; need to link to newer ones for
individual families too.
Module Name:src
Committed By: riastradh
Date: Mon Jul 24 22:20:53 UTC 2023
Modified Files:
src/sys/arch/x86/x86: errata.c
Log Message:
x86/errata.c: Link to original AMD errata guide.
This one is no longer updated; need to link to newer ones for
individual families too.
Module Name:src
Committed By: riastradh
Date: Tue Jul 18 12:34:25 UTC 2023
Modified Files:
src/sys/arch/x86/x86: fpu.c
Log Message:
x86/fpu: In kernel mode fpu traps, print the instruction pointer.
To generate a diff of this commit:
cvs rdiff -u -r1.86 -r1.87 src/sys/arc
Module Name:src
Committed By: riastradh
Date: Tue Jul 18 12:34:25 UTC 2023
Modified Files:
src/sys/arch/x86/x86: fpu.c
Log Message:
x86/fpu: In kernel mode fpu traps, print the instruction pointer.
To generate a diff of this commit:
cvs rdiff -u -r1.86 -r1.87 src/sys/arc
Module Name:src
Committed By: msaitoh
Date: Thu Jul 13 09:12:24 UTC 2023
Modified Files:
src/sys/arch/x86/x86: coretemp.c
Log Message:
coretemp(4): Change limits of Tjmax.
- Change the lower limit from 70 to 60. At least, some BIOSes can change
the value down to 62.
Module Name:src
Committed By: msaitoh
Date: Thu Jul 13 09:12:24 UTC 2023
Modified Files:
src/sys/arch/x86/x86: coretemp.c
Log Message:
coretemp(4): Change limits of Tjmax.
- Change the lower limit from 70 to 60. At least, some BIOSes can change
the value down to 62.
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