CVS commit: src/sys/arch/x86/include

2019-11-17 Thread SAITOH Masanobu
Module Name:src
Committed By:   msaitoh
Date:   Sun Nov 17 15:31:05 UTC 2019

Modified Files:
src/sys/arch/x86/include: specialreg.h

Log Message:
Add the following bit definitions from the latest Intel SDM:
 - CET shadow stack
 - Fast Short REP MOV
 - Hybrid part
 - CET Indirect Branch Tracking


To generate a diff of this commit:
cvs rdiff -u -r1.157 -r1.158 src/sys/arch/x86/include/specialreg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2019-11-17 Thread SAITOH Masanobu
Module Name:src
Committed By:   msaitoh
Date:   Sun Nov 17 15:31:05 UTC 2019

Modified Files:
src/sys/arch/x86/include: specialreg.h

Log Message:
Add the following bit definitions from the latest Intel SDM:
 - CET shadow stack
 - Fast Short REP MOV
 - Hybrid part
 - CET Indirect Branch Tracking


To generate a diff of this commit:
cvs rdiff -u -r1.157 -r1.158 src/sys/arch/x86/include/specialreg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/x86/include/specialreg.h
diff -u src/sys/arch/x86/include/specialreg.h:1.157 src/sys/arch/x86/include/specialreg.h:1.158
--- src/sys/arch/x86/include/specialreg.h:1.157	Tue Nov 12 18:00:13 2019
+++ src/sys/arch/x86/include/specialreg.h	Sun Nov 17 15:31:05 2019
@@ -1,4 +1,4 @@
-/*	$NetBSD: specialreg.h,v 1.157 2019/11/12 18:00:13 maxv Exp $	*/
+/*	$NetBSD: specialreg.h,v 1.158 2019/11/17 15:31:05 msaitoh Exp $	*/
 
 /*
  * Copyright (c) 2014-2019 The NetBSD Foundation, Inc.
@@ -447,6 +447,7 @@
 #define CPUID_SEF_OSPKE		__BIT(4)  /* OS has set CR4.PKE to ena. protec. keys */
 #define CPUID_SEF_WAITPKG	__BIT(5)  /* TPAUSE,UMONITOR,UMWAIT */
 #define CPUID_SEF_AVX512_VBMI2	__BIT(6)  /* AVX-512 Vector Byte Manipulation 2 */
+#define CPUID_SEF_CET_SS	__BIT(7)  /* CET shadow stack */
 #define CPUID_SEF_GFNI		__BIT(8)
 #define CPUID_SEF_VAES		__BIT(9)
 #define CPUID_SEF_VPCLMULQDQ	__BIT(10)
@@ -462,7 +463,7 @@
 
 #define CPUID_SEF_FLAGS1	"\177\20" \
 	"b\0PREFETCHWT1\0" "b\1AVX512_VBMI\0" "b\2UMIP\0" "b\3PKU\0"	\
-	"b\4OSPKE\0"	"b\5WAITPKG\0"	"b\6AVX512_VBMI2\0"		  \
+	"b\4OSPKE\0"	"b\5WAITPKG\0"	"b\6AVX512_VBMI2\0" "b\7CET_SS\0" \
 	"b\10GFNI\0"	"b\11VAES\0"	"b\12VPCLMULQDQ\0" "b\13AVX512_VNNI\0"\
 	"b\14AVX512_BITALG\0"		"b\16AVX512_VPOPCNTDQ\0"	\
 	"f\21\5MAWAU\0"			\
@@ -473,8 +474,11 @@
 /* %edx */
 #define CPUID_SEF_AVX512_4VNNIW	__BIT(2)
 #define CPUID_SEF_AVX512_4FMAPS	__BIT(3)
+#define CPUID_SEF_FSREP_MOV	__BIT(4)  /* Fast Short REP MOV */
 #define CPUID_SEF_MD_CLEAR	__BIT(10)
 #define CPUID_SEF_TSX_FORCE_ABORT __BIT(13) /* MSR_TSX_FORCE_ABORT bit 0 */
+#define CPUID_SEF_HYBRID	__BIT(15) /* Hybrid part */
+#define CPUID_SEF_CET_IBT	__BIT(20) /* CET Indirect Branch Tracking */
 #define CPUID_SEF_IBRS		__BIT(26) /* IBRS / IBPB Speculation Control */
 #define CPUID_SEF_STIBP		__BIT(27) /* STIBP Speculation Control */
 #define CPUID_SEF_L1D_FLUSH	__BIT(28) /* IA32_FLUSH_CMD MSR */
@@ -484,8 +488,10 @@
 
 #define CPUID_SEF_FLAGS2	"\20" \
 "\3" "AVX512_4VNNIW" "\4" "AVX512_4FMAPS" \
+	"\5" "FSREP_MOV"		\
 "\13" "MD_CLEAR"			\
-			"\16" "TSX_FORCE_ABORT"\
+			"\16" "TSX_FORCE_ABORT"		"\20" "HYBRID"	\
+	"\25" "CET_IBT"			\
 	"\33" "IBRS"	"\34" "STIBP"	\
 	"\35" "L1D_FLUSH" "\36" "ARCH_CAP" "\37CORE_CAP"	"\40" "SSBD"
 



CVS commit: src/sys/arch/x86/include

2019-10-29 Thread SAITOH Masanobu
Module Name:src
Committed By:   msaitoh
Date:   Wed Oct 30 05:35:36 UTC 2019

Modified Files:
src/sys/arch/x86/include: specialreg.h

Log Message:
- GMET is not bit 11 but 17.
- Add unknown CPUID Fn8000_000a %edx bit 20.


To generate a diff of this commit:
cvs rdiff -u -r1.155 -r1.156 src/sys/arch/x86/include/specialreg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/x86/include/specialreg.h
diff -u src/sys/arch/x86/include/specialreg.h:1.155 src/sys/arch/x86/include/specialreg.h:1.156
--- src/sys/arch/x86/include/specialreg.h:1.155	Tue Oct  8 03:16:21 2019
+++ src/sys/arch/x86/include/specialreg.h	Wed Oct 30 05:35:36 2019
@@ -1,4 +1,4 @@
-/*	$NetBSD: specialreg.h,v 1.155 2019/10/08 03:16:21 msaitoh Exp $	*/
+/*	$NetBSD: specialreg.h,v 1.156 2019/10/30 05:35:36 msaitoh Exp $	*/
 
 /*
  * Copyright (c) 2014-2019 The NetBSD Foundation, Inc.
@@ -755,19 +755,20 @@
 #define CPUID_AMD_SVM_FlushByASID	0x0040
 #define CPUID_AMD_SVM_DecodeAssist	0x0080
 #define CPUID_AMD_SVM_PauseFilter	0x0400
-#define CPUID_AMD_SVM_GMET		0x0800
 #define CPUID_AMD_SVM_PFThreshold	0x1000 /* PAUSE filter threshold */
 #define CPUID_AMD_SVM_AVIC		0x2000 /* AMD Virtual intr. ctrl */
 #define CPUID_AMD_SVM_V_VMSAVE_VMLOAD	0x8000 /* Virtual VM{SAVE/LOAD} */
 #define CPUID_AMD_SVM_vGIF		0x0001 /* Virtualized GIF */
+#define CPUID_AMD_SVM_GMET		0x0002
 #define CPUID_AMD_SVM_FLAGS	 "\20" \
 	"\1" "NP"	"\2" "LbrVirt"	"\3" "SVML"	"\4" "NRIPS"	\
 	"\5" "TSCRate"	"\6" "VMCBCleanBits" \
 			"\7" "FlushByASID" "\10" "DecodeAssist"	\
-	"\11" "B08"	"\12" "B09"	"\13" "PauseFilter" "\14" "GMET" \
+	"\11" "B08"	"\12" "B09"	"\13" "PauseFilter" "\14" "B11"	\
 	"\15" "PFThreshold" "\16" "AVIC" "\17" "B14"			\
 		"\20" "V_VMSAVE_VMLOAD"	\
-	"\21" "VGIF"
+	"\21" "VGIF"	"\22" "GMET"	\
+	"\25" "B20"
 
 /*
  * AMD Fn8000_0001d Cache Topology Information.



CVS commit: src/sys/arch/x86/include

2019-10-29 Thread SAITOH Masanobu
Module Name:src
Committed By:   msaitoh
Date:   Wed Oct 30 05:35:36 UTC 2019

Modified Files:
src/sys/arch/x86/include: specialreg.h

Log Message:
- GMET is not bit 11 but 17.
- Add unknown CPUID Fn8000_000a %edx bit 20.


To generate a diff of this commit:
cvs rdiff -u -r1.155 -r1.156 src/sys/arch/x86/include/specialreg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2019-10-17 Thread Emmanuel Dreyfus
Module Name:src
Committed By:   manu
Date:   Fri Oct 18 00:54:48 UTC 2019

Modified Files:
src/sys/arch/x86/include: efi.h

Log Message:
Add UEFI boot services and I/O method protoypes


To generate a diff of this commit:
cvs rdiff -u -r1.8 -r1.9 src/sys/arch/x86/include/efi.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2019-10-17 Thread Emmanuel Dreyfus
Module Name:src
Committed By:   manu
Date:   Fri Oct 18 00:54:48 UTC 2019

Modified Files:
src/sys/arch/x86/include: efi.h

Log Message:
Add UEFI boot services and I/O method protoypes


To generate a diff of this commit:
cvs rdiff -u -r1.8 -r1.9 src/sys/arch/x86/include/efi.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/x86/include/efi.h
diff -u src/sys/arch/x86/include/efi.h:1.8 src/sys/arch/x86/include/efi.h:1.9
--- src/sys/arch/x86/include/efi.h:1.8	Sun Oct 22 00:59:28 2017
+++ src/sys/arch/x86/include/efi.h	Fri Oct 18 00:54:48 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: efi.h,v 1.8 2017/10/22 00:59:28 maya Exp $   */
+/* $NetBSD: efi.h,v 1.9 2019/10/18 00:54:48 manu Exp $   */
 
 /*-
  * Copyright (c) 2004 Marcel Moolenaar
@@ -63,6 +63,12 @@ enum efi_reset {
 typedef uint16_t   efi_char;
 typedef unsigned long efi_status;
 
+#if defined(__amd64__)
+typedef uint64_t uintn;
+#elif defined(__i386__)
+typedef uint32_t uintn;
+#endif
+
 struct efi_cfgtbl {
struct uuid ct_uuid;
void   *ct_data;
@@ -149,6 +155,133 @@ struct efi_rt {
efi_char *);
 };
 
+typedef uintn efi_tpl;
+typedef void *efi_event;
+typedef void (*efi_event_notify)(efi_event, void *);
+typedef void *efi_handle;
+typedef struct {
+	uint8_t type;
+	uint8_t subtype;
+	uint8_t ldnegth[2];
+} efi_device_path;
+
+struct efi_bs {
+   struct efi_tblhdr bs_hdr;
+#define		EFI_BS_SIG  0x56524553544f4f42UL
+   efi_tpl (*bs_raisetpl)(efi_tpl);
+   void(*bs_restoretpl)(efi_tpl);
+   efi_status  (*bs_allocatepages)(uint32_t, uint32_t,
+	   uintn, paddr_t *);
+   efi_status  (*bs_freepages)(paddr_t, uintn);
+   efi_status  (*bs_getmemorymap)(uintn *, struct efi_md *,
+	   uintn *, uintn *, uint32_t *);
+   efi_status  (*bs_allocatepool)(uint32_t, uintn, void **);
+   efi_status  (*bs_freepool)(void *);
+   efi_status  (*bs_createevent)(uint32_t, efi_tpl, efi_event_notify,
+	   void *, efi_event *);
+   efi_status  (*bs_settimer)(efi_event, uint32_t, uint64_t);
+   efi_status  (*bs_waitforevent)(uintn, efi_event *, uintn *);
+   efi_status  (*bs_signalevent)(efi_event);
+   efi_status  (*bs_closeevent)(efi_event);
+   efi_status  (*bs_checkevent)(efi_event);
+   efi_status  (*bs_installprotocolinterface)(efi_handle *,
+	   struct uuid *, uint32_t, void *);
+   efi_status  (*bs_reinstallprotocolinterface)(efi_handle *,
+	   struct uuid *, void *, void *);
+   efi_status  (*bs_uninstallprotocolinterface)(efi_handle *,
+	   struct uuid *, void *);
+   efi_status  (*bs_handleprotocol)(efi_handle,
+	   struct uuid *, void **);
+   efi_status  (*bs_pchandleprotocol)(efi_handle,
+	   struct uuid *, void **);
+   efi_status  (*bs_registerprotocolnotify)(struct uuid *, efi_event,
+	   void **);
+   efi_status  (*bs_locatehandle)(uint32_t, struct uuid *, void *,
+	   uintn *, efi_handle *);
+   efi_status  (*bs_locatedevicepath)(struct uuid *, efi_device_path **,
+	   efi_handle *);
+   efi_status  (*bs_installconfigurationtable)(struct uuid *, void *);
+   efi_status  (*bs_loadimage)(uint8_t, efi_handle, efi_device_path *,
+	   void *, uintn, efi_handle *);
+   efi_status  (*bs_startimage)(efi_handle, uintn *, efi_char **);
+   efi_status  (*bs_exit)(efi_handle, efi_status, uintn, efi_char *);
+   efi_status  (*bs_unloadimage)(efi_handle);
+   efi_status  (*bs_exitbootservices)(efi_handle, uintn);
+   efi_status  (*bs_getnextmonotoniccount)(uint64_t *);
+   efi_status  (*bs_stall)(uintn);
+   efi_status  (*bs_setwatchdogtimer)(uintn, uint64_t,
+	   uintn, efi_char *);
+   efi_status  (*bs_connectcontroller)(efi_handle, efi_handle *,
+	efi_device_path *, uint8_t);
+   efi_status  (*bs_disconnectcontroller)(efi_handle, efi_handle,
+	efi_handle);
+   efi_status  (*bs_openprotocol)(efi_handle, struct uuid *, void **,
+	efi_handle, efi_handle, uint32_t);
+   efi_status  (*bs_closeprotocol)(efi_handle, struct uuid *,
+	efi_handle, efi_handle);
+   efi_status  (*bs_openprotocolinformation)(efi_handle, efi_handle,
+	uint32_t, uint32_t);
+   efi_status  (*bs_protocolsperhandle)(efi_handle,
+	struct uuid ***, uintn *);
+   efi_status  (*bs_locatehandlebuffer)(uint32_t, struct uuid *,
+	void *, uintn *, efi_handle **);
+   efi_status  (*bs_locateprotocol)(struct uuid *, void *, void **);
+   efi_status  (*bs_installmultipleprotocolinterfaces)(efi_handle *,
+	...);
+   efi_status  (*bs_uninstallmultipleprotocolinterfaces)(efi_handle,
+	...);
+   efi_status  (*bs_calculatecrc32)(void *, uintn, uint32_t *);
+   efi_status  

CVS commit: src/sys/arch/x86/include

2019-10-09 Thread Maxime Villard
Module Name:src
Committed By:   maxv
Date:   Wed Oct  9 17:28:46 UTC 2019

Modified Files:
src/sys/arch/x86/include: pte.h

Log Message:
Add new bits.


To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/x86/include/pte.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/x86/include/pte.h
diff -u src/sys/arch/x86/include/pte.h:1.2 src/sys/arch/x86/include/pte.h:1.3
--- src/sys/arch/x86/include/pte.h:1.2	Sat Oct  5 07:30:03 2019
+++ src/sys/arch/x86/include/pte.h	Wed Oct  9 17:28:46 2019
@@ -1,4 +1,4 @@
-/*	$NetBSD: pte.h,v 1.2 2019/10/05 07:30:03 maxv Exp $	*/
+/*	$NetBSD: pte.h,v 1.3 2019/10/09 17:28:46 maxv Exp $	*/
 
 /*
  * Copyright (c) 2010 The NetBSD Foundation, Inc.
@@ -39,12 +39,14 @@
 #define PGC_UC		(PTE_PWT | PTE_PCD)	/* hard UC */
 
 /*
- * page protection exception bits
+ * Page protection exception bits
  */
-
-#define PGEX_P		0x01	/* protection violation (vs. no mapping) */
-#define PGEX_W		0x02	/* exception during a write cycle */
-#define PGEX_U		0x04	/* exception while in user mode (upl) */
-#define PGEX_X		0x10	/* exception during instruction fetch */
+#define PGEX_P		0x0001	/* the page was present */
+#define PGEX_W		0x0002	/* exception during a write cycle */
+#define PGEX_U		0x0004	/* exception while in user mode */
+#define PGEX_RSVD	0x0008	/* a reserved bit was set in the page tables */
+#define PGEX_X		0x0010	/* exception during instruction fetch */
+#define PGEX_PK		0x0020	/* access disallowed by protection key */
+#define PGEX_SGX	0x8000	/* violation of sgx-specific access rights */
 
 #endif /* _X86_PTE_H */



CVS commit: src/sys/arch/x86/include

2019-10-09 Thread Maxime Villard
Module Name:src
Committed By:   maxv
Date:   Wed Oct  9 17:28:46 UTC 2019

Modified Files:
src/sys/arch/x86/include: pte.h

Log Message:
Add new bits.


To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/x86/include/pte.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2019-10-07 Thread SAITOH Masanobu
Module Name:src
Committed By:   msaitoh
Date:   Tue Oct  8 03:16:21 UTC 2019

Modified Files:
src/sys/arch/x86/include: specialreg.h

Log Message:
 Fix AMD Fn8000_0001f %eax bit 0's name.


To generate a diff of this commit:
cvs rdiff -u -r1.154 -r1.155 src/sys/arch/x86/include/specialreg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/x86/include/specialreg.h
diff -u src/sys/arch/x86/include/specialreg.h:1.154 src/sys/arch/x86/include/specialreg.h:1.155
--- src/sys/arch/x86/include/specialreg.h:1.154	Thu Oct  3 15:21:44 2019
+++ src/sys/arch/x86/include/specialreg.h	Tue Oct  8 03:16:21 2019
@@ -1,4 +1,4 @@
-/*	$NetBSD: specialreg.h,v 1.154 2019/10/03 15:21:44 msaitoh Exp $	*/
+/*	$NetBSD: specialreg.h,v 1.155 2019/10/08 03:16:21 msaitoh Exp $	*/
 
 /*
  * Copyright (c) 2014-2019 The NetBSD Foundation, Inc.
@@ -792,7 +792,7 @@
 #define CPUID_AMD_ENCMEM_VTE	__BIT(16)  /* Virtual Transparent Encryption */
 
 #define CPUID_AMD_ENCMEM_FLAGS	 "\20"	  \
-	"\1" "NP"	"\2" "SEV"	"\3" "PageFlushMsr"	"\4" "SEV-ES" \
+	"\1" "SME"	"\2" "SEV"	"\3" "PageFlushMsr"	"\4" "SEV-ES" \
 	"\21" "VTE"
 
 /*



CVS commit: src/sys/arch/x86/include

2019-10-07 Thread SAITOH Masanobu
Module Name:src
Committed By:   msaitoh
Date:   Tue Oct  8 03:16:21 UTC 2019

Modified Files:
src/sys/arch/x86/include: specialreg.h

Log Message:
 Fix AMD Fn8000_0001f %eax bit 0's name.


To generate a diff of this commit:
cvs rdiff -u -r1.154 -r1.155 src/sys/arch/x86/include/specialreg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2019-10-05 Thread Maxime Villard
Module Name:src
Committed By:   maxv
Date:   Sat Oct  5 07:30:03 UTC 2019

Modified Files:
src/sys/arch/x86/include: pmap.h pte.h

Log Message:
Switch to the new PTE naming. No binary diff (tested with MKREPRO).


To generate a diff of this commit:
cvs rdiff -u -r1.102 -r1.103 src/sys/arch/x86/include/pmap.h
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/x86/include/pte.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2019-10-05 Thread Maxime Villard
Module Name:src
Committed By:   maxv
Date:   Sat Oct  5 07:30:03 UTC 2019

Modified Files:
src/sys/arch/x86/include: pmap.h pte.h

Log Message:
Switch to the new PTE naming. No binary diff (tested with MKREPRO).


To generate a diff of this commit:
cvs rdiff -u -r1.102 -r1.103 src/sys/arch/x86/include/pmap.h
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/x86/include/pte.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/x86/include/pmap.h
diff -u src/sys/arch/x86/include/pmap.h:1.102 src/sys/arch/x86/include/pmap.h:1.103
--- src/sys/arch/x86/include/pmap.h:1.102	Wed Aug  7 06:23:48 2019
+++ src/sys/arch/x86/include/pmap.h	Sat Oct  5 07:30:03 2019
@@ -1,4 +1,4 @@
-/*	$NetBSD: pmap.h,v 1.102 2019/08/07 06:23:48 maxv Exp $	*/
+/*	$NetBSD: pmap.h,v 1.103 2019/10/05 07:30:03 maxv Exp $	*/
 
 /*
  * Copyright (c) 1997 Charles D. Cranor and Washington University.
@@ -315,8 +315,8 @@ struct pmap {
  */
 extern u_long PDPpaddr;
 
-extern pd_entry_t pmap_pg_g;			/* do we support PG_G? */
-extern pd_entry_t pmap_pg_nx;			/* do we support PG_NX? */
+extern pd_entry_t pmap_pg_g;			/* do we support PTE_G? */
+extern pd_entry_t pmap_pg_nx;			/* do we support PTE_NX? */
 extern int pmap_largepages;
 extern long nkptp[PTP_LEVELS];
 
@@ -526,7 +526,7 @@ kvtopte(vaddr_t va)
 	KASSERT(va >= VM_MIN_KERNEL_ADDRESS);
 
 	pde = L2_BASE + pl2_i(va);
-	if (*pde & PG_PS)
+	if (*pde & PTE_PS)
 		return ((pt_entry_t *)pde);
 
 	return (PTE_BASE + pl1_i(va));
@@ -560,7 +560,7 @@ xpmap_ptetomach(pt_entry_t *pte)
 	va = ((va & XPTE_MASK) >> XPTE_SHIFT) | (vaddr_t) PTE_BASE;
 	up_pte = (pt_entry_t *) va;
 
-	return (paddr_t) (((*up_pte) & PG_FRAME) + (((vaddr_t) pte) & (~PG_FRAME & ~VA_SIGN_MASK)));
+	return (paddr_t) (((*up_pte) & PTE_FRAME) + (((vaddr_t) pte) & (~PTE_FRAME & ~VA_SIGN_MASK)));
 }
 
 /* Xen helpers to change bits of a pte */

Index: src/sys/arch/x86/include/pte.h
diff -u src/sys/arch/x86/include/pte.h:1.1 src/sys/arch/x86/include/pte.h:1.2
--- src/sys/arch/x86/include/pte.h:1.1	Tue Jul  6 20:50:35 2010
+++ src/sys/arch/x86/include/pte.h	Sat Oct  5 07:30:03 2019
@@ -1,4 +1,4 @@
-/*	$NetBSD: pte.h,v 1.1 2010/07/06 20:50:35 cegger Exp $	*/
+/*	$NetBSD: pte.h,v 1.2 2019/10/05 07:30:03 maxv Exp $	*/
 
 /*
  * Copyright (c) 2010 The NetBSD Foundation, Inc.
@@ -33,10 +33,10 @@
 #define _X86_PTE_H
 
 /* Cacheability bits when we are using PAT */
-#define PGC_WB  0   /* The default */
-#define PGC_WC  PG_WT   /* WT and CD is WC */
-#define PGC_UCMINUS PG_N/* UC but mtrr can override */
-#define PGC_UC  (PG_WT | PG_N)  /* hard UC */
+#define PGC_WB		0			/* The default */
+#define PGC_WC		PTE_PWT			/* WT and CD is WC */
+#define PGC_UCMINUS	PTE_PCD			/* UC but mtrr can override */
+#define PGC_UC		(PTE_PWT | PTE_PCD)	/* hard UC */
 
 /*
  * page protection exception bits



CVS commit: src/sys/arch/x86/include

2019-09-26 Thread SAITOH Masanobu
Module Name:src
Committed By:   msaitoh
Date:   Thu Sep 26 06:42:53 UTC 2019

Modified Files:
src/sys/arch/x86/include: specialreg.h

Log Message:
 Define CPUID_CAPEX_FLAGS's bit 10 correctly.


To generate a diff of this commit:
cvs rdiff -u -r1.152 -r1.153 src/sys/arch/x86/include/specialreg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2019-09-26 Thread SAITOH Masanobu
Module Name:src
Committed By:   msaitoh
Date:   Thu Sep 26 06:42:53 UTC 2019

Modified Files:
src/sys/arch/x86/include: specialreg.h

Log Message:
 Define CPUID_CAPEX_FLAGS's bit 10 correctly.


To generate a diff of this commit:
cvs rdiff -u -r1.152 -r1.153 src/sys/arch/x86/include/specialreg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/x86/include/specialreg.h
diff -u src/sys/arch/x86/include/specialreg.h:1.152 src/sys/arch/x86/include/specialreg.h:1.153
--- src/sys/arch/x86/include/specialreg.h:1.152	Mon Sep  9 05:28:32 2019
+++ src/sys/arch/x86/include/specialreg.h	Thu Sep 26 06:42:52 2019
@@ -1,4 +1,4 @@
-/*	$NetBSD: specialreg.h,v 1.152 2019/09/09 05:28:32 msaitoh Exp $	*/
+/*	$NetBSD: specialreg.h,v 1.153 2019/09/26 06:42:52 msaitoh Exp $	*/
 
 /*
  * Copyright (c) 2014-2019 The NetBSD Foundation, Inc.
@@ -740,7 +740,7 @@
 #define CPUID_CAPEX_FLAGS	"\20"	 \
 	"\1CLZERO"	"\2IRPERF"	"\3XSAVEERPTR"			 \
 	"\5RDPRU"			"\7B6" \
-	"\11MCOMMIT"	"\12WBNOINVD"	"\12B10"			 \
+	"\11MCOMMIT"	"\12WBNOINVD"	"\13B10"			 \
 	"\15IBPB"	"\16B13"	"\17IBRS"	"\20STIBP"	 \
 	"\21IBRS_ALWAYSON" "\22STIBP_ALWAYSON" "\23PREFER_IBRS"	"\24B19" \
 	"\31SSBD"	"\32VIRT_SSBD"	"\33SSB_NO"



CVS commit: src/sys/arch/x86/include

2019-09-08 Thread SAITOH Masanobu
Module Name:src
Committed By:   msaitoh
Date:   Mon Sep  9 05:28:32 UTC 2019

Modified Files:
src/sys/arch/x86/include: specialreg.h

Log Message:
 Add MCOMMIT instruction.


To generate a diff of this commit:
cvs rdiff -u -r1.151 -r1.152 src/sys/arch/x86/include/specialreg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2019-09-08 Thread SAITOH Masanobu
Module Name:src
Committed By:   msaitoh
Date:   Mon Sep  9 05:28:32 UTC 2019

Modified Files:
src/sys/arch/x86/include: specialreg.h

Log Message:
 Add MCOMMIT instruction.


To generate a diff of this commit:
cvs rdiff -u -r1.151 -r1.152 src/sys/arch/x86/include/specialreg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/x86/include/specialreg.h
diff -u src/sys/arch/x86/include/specialreg.h:1.151 src/sys/arch/x86/include/specialreg.h:1.152
--- src/sys/arch/x86/include/specialreg.h:1.151	Fri Aug 30 13:11:28 2019
+++ src/sys/arch/x86/include/specialreg.h	Mon Sep  9 05:28:32 2019
@@ -1,4 +1,4 @@
-/*	$NetBSD: specialreg.h,v 1.151 2019/08/30 13:11:28 msaitoh Exp $	*/
+/*	$NetBSD: specialreg.h,v 1.152 2019/09/09 05:28:32 msaitoh Exp $	*/
 
 /*
  * Copyright (c) 2014-2019 The NetBSD Foundation, Inc.
@@ -725,6 +725,7 @@
 #define CPUID_CAPEX_IRPERF	__BIT(1)	/* InstRetCntMsr */
 #define CPUID_CAPEX_XSAVEERPTR	__BIT(2)	/* RstrFpErrPtrs by XRSTOR */
 #define CPUID_CAPEX_RDPRU	__BIT(4)	/* RDPRU instruction */
+#define CPUID_CAPEX_MCOMMIT	__BIT(8)	/* MCOMMIT instruction */
 #define CPUID_CAPEX_WBNOINVD	__BIT(9)	/* WBNOINVD instruction */
 #define CPUID_CAPEX_IBPB	__BIT(12)	/* Speculation Control IBPB */
 #define CPUID_CAPEX_IBRS	__BIT(14)	/* Speculation Control IBRS */
@@ -739,7 +740,7 @@
 #define CPUID_CAPEX_FLAGS	"\20"	 \
 	"\1CLZERO"	"\2IRPERF"	"\3XSAVEERPTR"			 \
 	"\5RDPRU"			"\7B6" \
-	"\11B8"		"\12WBNOINVD"	"\12B10"			 \
+	"\11MCOMMIT"	"\12WBNOINVD"	"\12B10"			 \
 	"\15IBPB"	"\16B13"	"\17IBRS"	"\20STIBP"	 \
 	"\21IBRS_ALWAYSON" "\22STIBP_ALWAYSON" "\23PREFER_IBRS"	"\24B19" \
 	"\31SSBD"	"\32VIRT_SSBD"	"\33SSB_NO"



CVS commit: src/sys/arch/x86/include

2019-09-07 Thread Maxime Villard
Module Name:src
Committed By:   maxv
Date:   Sat Sep  7 11:09:03 UTC 2019

Modified Files:
src/sys/arch/x86/include: cpufunc.h

Log Message:
Add a memory barrier on wrmsr, because some MSRs control memory access
rights (we don't use them though). Also add barriers on fninit and clts
for safety.


To generate a diff of this commit:
cvs rdiff -u -r1.34 -r1.35 src/sys/arch/x86/include/cpufunc.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2019-09-07 Thread Maxime Villard
Module Name:src
Committed By:   maxv
Date:   Sat Sep  7 11:09:03 UTC 2019

Modified Files:
src/sys/arch/x86/include: cpufunc.h

Log Message:
Add a memory barrier on wrmsr, because some MSRs control memory access
rights (we don't use them though). Also add barriers on fninit and clts
for safety.


To generate a diff of this commit:
cvs rdiff -u -r1.34 -r1.35 src/sys/arch/x86/include/cpufunc.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/x86/include/cpufunc.h
diff -u src/sys/arch/x86/include/cpufunc.h:1.34 src/sys/arch/x86/include/cpufunc.h:1.35
--- src/sys/arch/x86/include/cpufunc.h:1.34	Fri Jul  5 17:08:55 2019
+++ src/sys/arch/x86/include/cpufunc.h	Sat Sep  7 11:09:03 2019
@@ -1,4 +1,4 @@
-/*	$NetBSD: cpufunc.h,v 1.34 2019/07/05 17:08:55 maxv Exp $	*/
+/*	$NetBSD: cpufunc.h,v 1.35 2019/09/07 11:09:03 maxv Exp $	*/
 
 /*
  * Copyright (c) 1998, 2007, 2019 The NetBSD Foundation, Inc.
@@ -271,7 +271,7 @@ union savefpu;
 static inline void
 fninit(void)
 {
-	__asm volatile ("fninit");
+	__asm volatile ("fninit" ::: "memory");
 }
 
 static inline void
@@ -303,7 +303,7 @@ fnstsw(uint16_t *val)
 static inline void
 clts(void)
 {
-	__asm volatile ("clts");
+	__asm volatile ("clts" ::: "memory");
 }
 
 void	stts(void);
@@ -433,6 +433,7 @@ wrmsr(u_int msr, uint64_t val)
 		"wrmsr"
 		:
 		: "a" (low), "d" (high), "c" (msr)
+		: "memory"
 	);
 }
 



CVS commit: src/sys/arch/x86/include

2019-08-30 Thread SAITOH Masanobu
Module Name:src
Committed By:   msaitoh
Date:   Fri Aug 30 13:11:28 UTC 2019

Modified Files:
src/sys/arch/x86/include: specialreg.h

Log Message:
 Add definitions of AMD's CPUID Fn8000_0008 %ebx.


To generate a diff of this commit:
cvs rdiff -u -r1.150 -r1.151 src/sys/arch/x86/include/specialreg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/x86/include/specialreg.h
diff -u src/sys/arch/x86/include/specialreg.h:1.150 src/sys/arch/x86/include/specialreg.h:1.151
--- src/sys/arch/x86/include/specialreg.h:1.150	Fri Jul 26 10:03:40 2019
+++ src/sys/arch/x86/include/specialreg.h	Fri Aug 30 13:11:28 2019
@@ -1,4 +1,4 @@
-/*	$NetBSD: specialreg.h,v 1.150 2019/07/26 10:03:40 msaitoh Exp $	*/
+/*	$NetBSD: specialreg.h,v 1.151 2019/08/30 13:11:28 msaitoh Exp $	*/
 
 /*
  * Copyright (c) 2014-2019 The NetBSD Foundation, Inc.
@@ -712,6 +712,38 @@
 	"\11" "TSC"	"\12" "CPB"	"\13" "EffFreq"	"\14" "PROCFI"	  \
 	"\15" "PROCPR"	"\16" "CONNSTBY" "\17" "RAPL"
 
+/*
+ * AMD Processor Capacity Parameters and Extended Features
+ * CPUID Fn8000_0008
+ * %eax: Long Mode Size Identifiers
+ * %ebx: Extended Feature Identifiers
+ * %ecx: Size Identifiers
+ */
+
+/* %ebx */
+#define CPUID_CAPEX_CLZERO	__BIT(0)	/* CLZERO instruction */
+#define CPUID_CAPEX_IRPERF	__BIT(1)	/* InstRetCntMsr */
+#define CPUID_CAPEX_XSAVEERPTR	__BIT(2)	/* RstrFpErrPtrs by XRSTOR */
+#define CPUID_CAPEX_RDPRU	__BIT(4)	/* RDPRU instruction */
+#define CPUID_CAPEX_WBNOINVD	__BIT(9)	/* WBNOINVD instruction */
+#define CPUID_CAPEX_IBPB	__BIT(12)	/* Speculation Control IBPB */
+#define CPUID_CAPEX_IBRS	__BIT(14)	/* Speculation Control IBRS */
+#define CPUID_CAPEX_STIBP	__BIT(15)	/* Speculation Control STIBP */
+#define CPUID_CAPEX_IBRS_ALWAYSON __BIT(16)	/* IBRS always on mode */
+#define CPUID_CAPEX_STIBP_ALWAYSON __BIT(17)	/* STIBP always on mode */
+#define CPUID_CAPEX_PREFER_IBRS	__BIT(18)	/* IBRS preferred */
+#define CPUID_CAPEX_SSBD	__BIT(24)	/* Speculation Control SSBD */
+#define CPUID_CAPEX_VIRT_SSBD	__BIT(25)	/* Virt Spec Control SSBD */
+#define CPUID_CAPEX_SSB_NO	__BIT(26)	/* SSBD not required */
+
+#define CPUID_CAPEX_FLAGS	"\20"	 \
+	"\1CLZERO"	"\2IRPERF"	"\3XSAVEERPTR"			 \
+	"\5RDPRU"			"\7B6" \
+	"\11B8"		"\12WBNOINVD"	"\12B10"			 \
+	"\15IBPB"	"\16B13"	"\17IBRS"	"\20STIBP"	 \
+	"\21IBRS_ALWAYSON" "\22STIBP_ALWAYSON" "\23PREFER_IBRS"	"\24B19" \
+	"\31SSBD"	"\32VIRT_SSBD"	"\33SSB_NO"
+
 /* AMD Fn800a %edx features (SVM features) */
 #define CPUID_AMD_SVM_NP		0x0001
 #define CPUID_AMD_SVM_LbrVirt		0x0002



CVS commit: src/sys/arch/x86/include

2019-08-30 Thread SAITOH Masanobu
Module Name:src
Committed By:   msaitoh
Date:   Fri Aug 30 13:11:28 UTC 2019

Modified Files:
src/sys/arch/x86/include: specialreg.h

Log Message:
 Add definitions of AMD's CPUID Fn8000_0008 %ebx.


To generate a diff of this commit:
cvs rdiff -u -r1.150 -r1.151 src/sys/arch/x86/include/specialreg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2019-07-24 Thread SAITOH Masanobu
Module Name:src
Committed By:   msaitoh
Date:   Wed Jul 24 10:45:47 UTC 2019

Modified Files:
src/sys/arch/x86/include: cacheinfo.h

Log Message:
 It seems that AMD zen2's CPUID 0x8006 leaf's spec has changed.
The EDX register's acsociativity field has 9. In the latest available document,
it's a reserved value. I have no access to zen2's document, but many websites
say that the acsociativity is 16. Add it.


To generate a diff of this commit:
cvs rdiff -u -r1.26 -r1.27 src/sys/arch/x86/include/cacheinfo.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/x86/include/cacheinfo.h
diff -u src/sys/arch/x86/include/cacheinfo.h:1.26 src/sys/arch/x86/include/cacheinfo.h:1.27
--- src/sys/arch/x86/include/cacheinfo.h:1.26	Mon Mar 12 07:35:45 2018
+++ src/sys/arch/x86/include/cacheinfo.h	Wed Jul 24 10:45:47 2019
@@ -1,4 +1,4 @@
-/*	$NetBSD: cacheinfo.h,v 1.26 2018/03/12 07:35:45 msaitoh Exp $	*/
+/*	$NetBSD: cacheinfo.h,v 1.27 2019/07/24 10:45:47 msaitoh Exp $	*/
 
 #ifndef _X86_CACHEINFO_H_
 #define _X86_CACHEINFO_H_
@@ -362,6 +362,7 @@ __CI_TBL(0, 0x02,2, 0, 0, NULL), \
 __CI_TBL(0, 0x04,4, 0, 0, NULL), \
 __CI_TBL(0, 0x06,8, 0, 0, NULL), \
 __CI_TBL(0, 0x08,   16, 0, 0, NULL), \
+__CI_TBL(0, 0x09,   16, 0, 0, NULL), \
 __CI_TBL(0, 0x0a,   32, 0, 0, NULL), \
 __CI_TBL(0, 0x0b,   48, 0, 0, NULL), \
 __CI_TBL(0, 0x0c,   64, 0, 0, NULL), \



CVS commit: src/sys/arch/x86/include

2019-07-24 Thread SAITOH Masanobu
Module Name:src
Committed By:   msaitoh
Date:   Wed Jul 24 10:45:47 UTC 2019

Modified Files:
src/sys/arch/x86/include: cacheinfo.h

Log Message:
 It seems that AMD zen2's CPUID 0x8006 leaf's spec has changed.
The EDX register's acsociativity field has 9. In the latest available document,
it's a reserved value. I have no access to zen2's document, but many websites
say that the acsociativity is 16. Add it.


To generate a diff of this commit:
cvs rdiff -u -r1.26 -r1.27 src/sys/arch/x86/include/cacheinfo.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2019-07-13 Thread SAITOH Masanobu
Module Name:src
Committed By:   msaitoh
Date:   Sat Jul 13 09:28:03 UTC 2019

Modified Files:
src/sys/arch/x86/include: specialreg.h

Log Message:
 Define some new bits of CPUID Fn8000_0007 %edx AMD Advanced Power Management
leaf.


To generate a diff of this commit:
cvs rdiff -u -r1.148 -r1.149 src/sys/arch/x86/include/specialreg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2019-07-13 Thread SAITOH Masanobu
Module Name:src
Committed By:   msaitoh
Date:   Sat Jul 13 09:28:03 UTC 2019

Modified Files:
src/sys/arch/x86/include: specialreg.h

Log Message:
 Define some new bits of CPUID Fn8000_0007 %edx AMD Advanced Power Management
leaf.


To generate a diff of this commit:
cvs rdiff -u -r1.148 -r1.149 src/sys/arch/x86/include/specialreg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/x86/include/specialreg.h
diff -u src/sys/arch/x86/include/specialreg.h:1.148 src/sys/arch/x86/include/specialreg.h:1.149
--- src/sys/arch/x86/include/specialreg.h:1.148	Wed Jun 26 12:29:00 2019
+++ src/sys/arch/x86/include/specialreg.h	Sat Jul 13 09:28:03 2019
@@ -1,4 +1,4 @@
-/*	$NetBSD: specialreg.h,v 1.148 2019/06/26 12:29:00 mgorny Exp $	*/
+/*	$NetBSD: specialreg.h,v 1.149 2019/07/13 09:28:03 msaitoh Exp $	*/
 
 /*
  * Copyright (c) 2014-2019 The NetBSD Foundation, Inc.
@@ -701,12 +701,16 @@
 #define CPUID_APM_TSC	0x0100	/* TSC invariant */
 #define CPUID_APM_CPB	0x0200	/* Core performance boost */
 #define CPUID_APM_EFF	0x0400	/* Effective Frequency (read-only) */
-
-#define CPUID_APM_FLAGS		"\20" \
-	"\1" "TS"	"\2" "FID"	"\3" "VID"	"\4" "TTP" \
-	"\5" "HTC"	"\6" "STC"	"\7" "100"	"\10" "HWP" \
-	"\11" "TSC"	"\12" "CPB"	"\13" "EffFreq"	"\14" "B11" \
-	"\15" "B12"
+#define CPUID_APM_PROCFI 0x0800	/* Proc Feedback Interface */
+#define CPUID_APM_PROCPR 0x1000	/* Proc Power Reporting  */
+#define CPUID_APM_CONNSTBY 0x2000	/* Connected Standby */
+#define CPUID_APM_RAPL	0x4000	/* Running Average Power Limit */
+
+#define CPUID_APM_FLAGS		"\20"	  \
+	"\1" "TS"	"\2" "FID"	"\3" "VID"	"\4" "TTP"	  \
+	"\5" "HTC"	"\6" "STC"	"\7" "100"	"\10" "HWP"	  \
+	"\11" "TSC"	"\12" "CPB"	"\13" "EffFreq"	"\14" "PROCFI"	  \
+	"\15" "PROCPR"	"\16" "CONNSTBY" "\17" "RAPL"
 
 /* AMD Fn800a %edx features (SVM features) */
 #define CPUID_AMD_SVM_NP		0x0001



CVS commit: src/sys/arch/x86/include

2019-06-20 Thread NONAKA Kimihiro
Module Name:src
Committed By:   nonaka
Date:   Fri Jun 21 02:08:55 UTC 2019

Modified Files:
src/sys/arch/x86/include: bootinfo.h

Log Message:
PR/54147: Increase BOOTINFO_MAXSIZE to 16Kib.

Some systems require a larger bootinfo size for memory descriptors.


To generate a diff of this commit:
cvs rdiff -u -r1.29 -r1.30 src/sys/arch/x86/include/bootinfo.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/x86/include/bootinfo.h
diff -u src/sys/arch/x86/include/bootinfo.h:1.29 src/sys/arch/x86/include/bootinfo.h:1.30
--- src/sys/arch/x86/include/bootinfo.h:1.29	Fri Apr 13 11:24:34 2018
+++ src/sys/arch/x86/include/bootinfo.h	Fri Jun 21 02:08:55 2019
@@ -1,4 +1,4 @@
-/*	$NetBSD: bootinfo.h,v 1.29 2018/04/13 11:24:34 nonaka Exp $	*/
+/*	$NetBSD: bootinfo.h,v 1.30 2019/06/21 02:08:55 nonaka Exp $	*/
 
 /*
  * Copyright (c) 1997
@@ -251,7 +251,7 @@ struct btinfo_efimemmap {
 
 #ifdef _KERNEL
 
-#define BOOTINFO_MAXSIZE 8192
+#define BOOTINFO_MAXSIZE 16384
 
 #ifndef _LOCORE
 /*



CVS commit: src/sys/arch/x86/include

2019-06-20 Thread NONAKA Kimihiro
Module Name:src
Committed By:   nonaka
Date:   Fri Jun 21 02:08:55 UTC 2019

Modified Files:
src/sys/arch/x86/include: bootinfo.h

Log Message:
PR/54147: Increase BOOTINFO_MAXSIZE to 16Kib.

Some systems require a larger bootinfo size for memory descriptors.


To generate a diff of this commit:
cvs rdiff -u -r1.29 -r1.30 src/sys/arch/x86/include/bootinfo.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2019-06-13 Thread SAITOH Masanobu
Module Name:src
Committed By:   msaitoh
Date:   Thu Jun 13 15:10:27 UTC 2019

Modified Files:
src/sys/arch/x86/include: i82489reg.h

Log Message:
Indent consistently. No functional change.


To generate a diff of this commit:
cvs rdiff -u -r1.17 -r1.18 src/sys/arch/x86/include/i82489reg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/x86/include/i82489reg.h
diff -u src/sys/arch/x86/include/i82489reg.h:1.17 src/sys/arch/x86/include/i82489reg.h:1.18
--- src/sys/arch/x86/include/i82489reg.h:1.17	Thu Jun 13 07:44:27 2019
+++ src/sys/arch/x86/include/i82489reg.h	Thu Jun 13 15:10:27 2019
@@ -1,4 +1,4 @@
-/*	$NetBSD: i82489reg.h,v 1.17 2019/06/13 07:44:27 msaitoh Exp $	*/
+/*	$NetBSD: i82489reg.h,v 1.18 2019/06/13 15:10:27 msaitoh Exp $	*/
 
 /*-
  * Copyright (c) 1998, 2008 The NetBSD Foundation, Inc.
@@ -35,36 +35,36 @@
  * "local" APIC.
  */
 
-#define	LAPIC_ID		0x020	/* ID. (xAPIC: RW, x2APIC: RO) */
+#define	LAPIC_ID	0x020	/* ID. (xAPIC: RW, x2APIC: RO) */
 #	define LAPIC_ID_MASK		0xff00
 #	define LAPIC_ID_SHIFT		24
 
-#define LAPIC_VERS		0x030	/* Version. RO */
+#define LAPIC_VERS	0x030	/* Version. RO */
 #	define LAPIC_VERSION_MASK	0x00ff
 #	define LAPIC_VERSION_LVT_MASK	0x00ff
 #	define LAPIC_VERSION_LVT_SHIFT	16
 #	define LAPIC_VERSION_DIRECTED_EOI 0x0100
 #	define LAPIC_VERSION_EXTAPIC_SPACE 0x8000
 
-#define LAPIC_TPRI		0x080	/* Task Prio. RW */
+#define LAPIC_TPRI	0x080	/* Task Prio. RW */
 #	define LAPIC_TPRI_MASK		0x00ff
 #	define LAPIC_TPRI_INT_MASK	0x00f0
 #	define LAPIC_TPRI_SUB_MASK	0x000f
 
-#define LAPIC_APRI		0x090	/* Arbitration prio (xAPIC: RO, x2APIC: NA) */
+#define LAPIC_APRI	0x090	/* Arbitration prio (xAPIC: RO, x2APIC: NA) */
 #	define LAPIC_APRI_MASK		0x00ff
 
-#define LAPIC_PPRI		0x0a0	/* Processor prio. RO */
-#define LAPIC_EOI		0x0b0	/* End Int. W */
-#define LAPIC_RRR		0x0c0	/* Remote read (xAPIC: RO, x2APIC: NA) */
-#define LAPIC_LDR		0x0d0	/* Logical dest. (xAPIC: RW, x2APIC: RO) */
+#define LAPIC_PPRI	0x0a0	/* Processor prio. RO */
+#define LAPIC_EOI	0x0b0	/* End Int. W */
+#define LAPIC_RRR	0x0c0	/* Remote read (xAPIC: RO, x2APIC: NA) */
+#define LAPIC_LDR	0x0d0	/* Logical dest. (xAPIC: RW, x2APIC: RO) */
 
-#define LAPIC_DFR		0x0e0	/* Dest. format (xAPIC: RW, x2APIC: NA) */
+#define LAPIC_DFR	0x0e0	/* Dest. format (xAPIC: RW, x2APIC: NA) */
 #	define LAPIC_DFR_MASK		0xf000
 #	define LAPIC_DFR_FLAT		0xf000
 #	define LAPIC_DFR_CLUSTER	0x
 
-#define LAPIC_SVR		0x0f0	/* Spurious intvec RW */
+#define LAPIC_SVR	0x0f0	/* Spurious intvec RW */
 #	define LAPIC_SVR_VECTOR_MASK	0x00ff
 #	define LAPIC_SVR_VEC_FIX	0x000f
 #	define LAPIC_SVR_VEC_PROG	0x00f0
@@ -74,14 +74,14 @@
 #	define LAPIC_SVR_FDIS		0x0200
 #	define LAPIC_SVR_EOI_BC_DIS	0x1000
 
-#define LAPIC_ISR	0x100		/* In-Service Status RO */
-#define LAPIC_TMR	0x180		/* Trigger Mode RO */
-#define LAPIC_IRR	0x200		/* Interrupt Req RO */
-#define LAPIC_ESR	0x280		/* Err status. RW */
+#define LAPIC_ISR	0x100	/* In-Service Status RO */
+#define LAPIC_TMR	0x180	/* Trigger Mode RO */
+#define LAPIC_IRR	0x200	/* Interrupt Req RO */
+#define LAPIC_ESR	0x280	/* Err status. RW */
 
-#define LAPIC_LVT_CMCI	0x2f0		/* Loc.vec (CMCI) RW */
+#define LAPIC_LVT_CMCI	0x2f0	/* Loc.vec (CMCI) RW */
 
-#define LAPIC_ICRLO	0x300		/* Int. cmd. (xAPIC: RW, x2APIC: RW64) */
+#define LAPIC_ICRLO	0x300	/* Int. cmd. (xAPIC: RW, x2APIC: RW64) */
 #	define LAPIC_DLMODE_MASK	0x0700	/* Delivery Mode */
 #	define LAPIC_DLMODE_FIXED	0x
 #	define LAPIC_DLMODE_LOW		0x0100	/* N/A in x2APIC mode */
@@ -111,17 +111,17 @@
 #	define LAPIC_DEST_ALLINCL	0x0008
 #	define LAPIC_DEST_ALLEXCL	0x000c
 
-#define LAPIC_ICRHI	0x310		/* Int. cmd. (xAPIC: RW, x2APIC: NA) */
+#define LAPIC_ICRHI	0x310	/* Int. cmd. (xAPIC: RW, x2APIC: NA) */
 
-#define LAPIC_LVTT	0x320		/* Loc.vec.(timer) RW */
+#define LAPIC_LVTT	0x320	/* Loc.vec.(timer) RW */
 #	define LAPIC_LVTT_VEC_MASK	0x00ff
 #	define LAPIC_LVTT_DS		0x1000
 #	define LAPIC_LVTT_M		0x0001
 #	define LAPIC_LVTT_TM		0x0002
 
-#define LAPIC_TMINT	0x330		/* Loc.vec (Thermal) RW */
-#define LAPIC_PCINT	0x340		/* Loc.vec (Perf Mon) RW */
-#define LAPIC_LVINT0	0x350		/* Loc.vec (LINT0) RW */
+#define LAPIC_TMINT	0x330	/* Loc.vec (Thermal) RW */
+#define LAPIC_PCINT	0x340	/* Loc.vec (Perf Mon) RW */
+#define LAPIC_LVINT0	0x350	/* Loc.vec (LINT0) RW */
 #	define LAPIC_LVT_DM_MASK	0x0700
 #	define LAPIC_LVT_DM_FIXED	0x
 #	define LAPIC_LVT_DM_SMI		0x0200
@@ -134,12 +134,12 @@
 #	define LAPIC_INP_POL		0x2000
 #	define LAPIC_PEND_SEND		0x1000
 
-#define LAPIC_LVINT1	0x360		/* Loc.vec (LINT1) RW */
-#define LAPIC_LVERR	0x370		/* Loc.vec (ERROR) RW */
-#define LAPIC_ICR_TIMER	0x380		/* Initial count RW */
-#define LAPIC_CCR_TIMER	0x390		/* Current count RO */
+#define LAPIC_LVINT1	0x360	

CVS commit: src/sys/arch/x86/include

2019-06-13 Thread SAITOH Masanobu
Module Name:src
Committed By:   msaitoh
Date:   Thu Jun 13 15:10:27 UTC 2019

Modified Files:
src/sys/arch/x86/include: i82489reg.h

Log Message:
Indent consistently. No functional change.


To generate a diff of this commit:
cvs rdiff -u -r1.17 -r1.18 src/sys/arch/x86/include/i82489reg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2019-06-13 Thread SAITOH Masanobu
Module Name:src
Committed By:   msaitoh
Date:   Thu Jun 13 07:44:27 UTC 2019

Modified Files:
src/sys/arch/x86/include: i82489reg.h

Log Message:
 Modify LAPIC_LVT_CMCI's comment to be consistent with other LVT's.
No functional change.


To generate a diff of this commit:
cvs rdiff -u -r1.16 -r1.17 src/sys/arch/x86/include/i82489reg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/x86/include/i82489reg.h
diff -u src/sys/arch/x86/include/i82489reg.h:1.16 src/sys/arch/x86/include/i82489reg.h:1.17
--- src/sys/arch/x86/include/i82489reg.h:1.16	Fri Apr 28 01:23:58 2017
+++ src/sys/arch/x86/include/i82489reg.h	Thu Jun 13 07:44:27 2019
@@ -1,4 +1,4 @@
-/*	$NetBSD: i82489reg.h,v 1.16 2017/04/28 01:23:58 nonaka Exp $	*/
+/*	$NetBSD: i82489reg.h,v 1.17 2019/06/13 07:44:27 msaitoh Exp $	*/
 
 /*-
  * Copyright (c) 1998, 2008 The NetBSD Foundation, Inc.
@@ -79,7 +79,7 @@
 #define LAPIC_IRR	0x200		/* Interrupt Req RO */
 #define LAPIC_ESR	0x280		/* Err status. RW */
 
-#define LAPIC_LVT_CMCI	0x2f0		/* LVT CMCI RW */
+#define LAPIC_LVT_CMCI	0x2f0		/* Loc.vec (CMCI) RW */
 
 #define LAPIC_ICRLO	0x300		/* Int. cmd. (xAPIC: RW, x2APIC: RW64) */
 #	define LAPIC_DLMODE_MASK	0x0700	/* Delivery Mode */



CVS commit: src/sys/arch/x86/include

2019-06-13 Thread SAITOH Masanobu
Module Name:src
Committed By:   msaitoh
Date:   Thu Jun 13 07:44:27 UTC 2019

Modified Files:
src/sys/arch/x86/include: i82489reg.h

Log Message:
 Modify LAPIC_LVT_CMCI's comment to be consistent with other LVT's.
No functional change.


To generate a diff of this commit:
cvs rdiff -u -r1.16 -r1.17 src/sys/arch/x86/include/i82489reg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2019-05-30 Thread Christos Zoulas
Module Name:src
Committed By:   christos
Date:   Thu May 30 21:40:40 UTC 2019

Modified Files:
src/sys/arch/x86/include: cpufunc.h

Log Message:
use __asm


To generate a diff of this commit:
cvs rdiff -u -r1.31 -r1.32 src/sys/arch/x86/include/cpufunc.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/x86/include/cpufunc.h
diff -u src/sys/arch/x86/include/cpufunc.h:1.31 src/sys/arch/x86/include/cpufunc.h:1.32
--- src/sys/arch/x86/include/cpufunc.h:1.31	Wed May 29 12:54:41 2019
+++ src/sys/arch/x86/include/cpufunc.h	Thu May 30 17:40:40 2019
@@ -1,4 +1,4 @@
-/*	$NetBSD: cpufunc.h,v 1.31 2019/05/29 16:54:41 maxv Exp $	*/
+/*	$NetBSD: cpufunc.h,v 1.32 2019/05/30 21:40:40 christos Exp $	*/
 
 /*
  * Copyright (c) 1998, 2007, 2019 The NetBSD Foundation, Inc.
@@ -50,7 +50,7 @@
 static inline void
 x86_pause(void)
 {
-	asm volatile ("pause");
+	__asm volatile ("pause");
 }
 
 void	x86_lfence(void);
@@ -81,7 +81,7 @@ invpcid(register_t op, uint64_t pcid, va
 		.addr = va
 	};
 
-	asm volatile (
+	__asm volatile (
 		"invpcid %[desc],%[op]"
 		:
 		: [desc] "m" (desc), [op] "r" (op)
@@ -94,7 +94,7 @@ rdtsc(void)
 {
 	uint32_t low, high;
 
-	asm volatile (
+	__asm volatile (
 		"rdtsc"
 		: "=a" (low), "=d" (high)
 		:
@@ -127,7 +127,7 @@ x86_getss(void)
 {
 	uint16_t val;
 
-	asm volatile (
+	__asm volatile (
 		"mov	%%ss,%[val]"
 		: [val] "=r" (val)
 		:
@@ -138,7 +138,7 @@ x86_getss(void)
 static inline void
 setds(uint16_t val)
 {
-	asm volatile (
+	__asm volatile (
 		"mov	%[val],%%ds"
 		:
 		: [val] "r" (val)
@@ -148,7 +148,7 @@ setds(uint16_t val)
 static inline void
 setes(uint16_t val)
 {
-	asm volatile (
+	__asm volatile (
 		"mov	%[val],%%es"
 		:
 		: [val] "r" (val)
@@ -158,7 +158,7 @@ setes(uint16_t val)
 static inline void
 setfs(uint16_t val)
 {
-	asm volatile (
+	__asm volatile (
 		"mov	%[val],%%fs"
 		:
 		: [val] "r" (val)
@@ -172,7 +172,7 @@ void	setusergs(int);
 #define FUNC_CR(crnum)	\
 	static inline void lcr##crnum(register_t val)	\
 	{		\
-		asm volatile (\
+		__asm volatile (\
 			"mov	%[val],%%cr" #crnum	\
 			:\
 			: [val] "r" (val)		\
@@ -181,7 +181,7 @@ void	setusergs(int);
 	static inline register_t rcr##crnum(void)	\
 	{		\
 		register_t val;\
-		asm volatile (\
+		__asm volatile (\
 			"mov	%%cr" #crnum ",%[val]"	\
 			: [val] "=r" (val)		\
 			:\
@@ -211,7 +211,7 @@ FUNC_CR(8)
 #define FUNC_DR(drnum)	\
 	static inline void ldr##drnum(register_t val)	\
 	{		\
-		asm volatile (\
+		__asm volatile (\
 			"mov	%[val],%%dr" #drnum	\
 			:\
 			: [val] "r" (val)		\
@@ -220,7 +220,7 @@ FUNC_CR(8)
 	static inline register_t rdr##drnum(void)	\
 	{		\
 		register_t val;\
-		asm volatile (\
+		__asm volatile (\
 			"mov	%%dr" #drnum ",%[val]"	\
 			: [val] "=r" (val)		\
 			:\
@@ -255,13 +255,13 @@ union savefpu;
 static inline void
 fninit(void)
 {
-	asm volatile ("fninit");
+	__asm volatile ("fninit");
 }
 
 static inline void
 fnclex(void)
 {
-	asm volatile ("fnclex");
+	__asm volatile ("fnclex");
 }
 
 void	fnsave(union savefpu *);
@@ -273,7 +273,7 @@ void	frstor(const union savefpu *);
 static inline void
 clts(void)
 {
-	asm volatile ("clts");
+	__asm volatile ("clts");
 }
 
 void	stts(void);
@@ -289,7 +289,7 @@ rdxcr(uint32_t xcr)
 {
 	uint32_t low, high;
 
-	asm volatile (
+	__asm volatile (
 		"xgetbv"
 		: "=a" (low), "=d" (high)
 		: "c" (xcr)
@@ -305,7 +305,7 @@ wrxcr(uint32_t xcr, uint64_t val)
 
 	low = val;
 	high = val >> 32;
-	asm volatile (
+	__asm volatile (
 		"xsetbv"
 		:
 		: "a" (low), "d" (high), "c" (xcr)
@@ -325,13 +325,13 @@ void x86_enable_intr(void);
 static inline void
 x86_disable_intr(void)
 {
-	asm volatile ("cli");
+	__asm volatile ("cli");
 }
 
 static inline void
 x86_enable_intr(void)
 {
-	asm volatile ("sti");
+	__asm volatile ("sti");
 }
 #endif /* XENPV */
 
@@ -358,7 +358,7 @@ rdmsr(u_int msr)
 {
 	uint32_t low, high;
 
-	asm volatile (
+	__asm volatile (
 		"rdmsr"
 		: "=a" (low), "=d" (high)
 		: "c" (msr)
@@ -377,7 +377,7 @@ wrmsr(u_int msr, uint64_t val)
 
 	low = val;
 	high = val >> 32;
-	asm volatile (
+	__asm volatile (
 		"wrmsr"
 		:
 		: "a" (low), "d" (high), "c" (msr)



CVS commit: src/sys/arch/x86/include

2019-05-30 Thread Christos Zoulas
Module Name:src
Committed By:   christos
Date:   Thu May 30 21:40:40 UTC 2019

Modified Files:
src/sys/arch/x86/include: cpufunc.h

Log Message:
use __asm


To generate a diff of this commit:
cvs rdiff -u -r1.31 -r1.32 src/sys/arch/x86/include/cpufunc.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2019-05-18 Thread Maxime Villard
Module Name:src
Committed By:   maxv
Date:   Sat May 18 08:17:39 UTC 2019

Modified Files:
src/sys/arch/x86/include: specialreg.h

Log Message:
Clean up a little, add new XCR0 bits, remove a few unused MSRs, and fix
typos.


To generate a diff of this commit:
cvs rdiff -u -r1.145 -r1.146 src/sys/arch/x86/include/specialreg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/x86/include/specialreg.h
diff -u src/sys/arch/x86/include/specialreg.h:1.145 src/sys/arch/x86/include/specialreg.h:1.146
--- src/sys/arch/x86/include/specialreg.h:1.145	Tue May 14 18:11:34 2019
+++ src/sys/arch/x86/include/specialreg.h	Sat May 18 08:17:39 2019
@@ -1,6 +1,32 @@
-/*	$NetBSD: specialreg.h,v 1.145 2019/05/14 18:11:34 msaitoh Exp $	*/
+/*	$NetBSD: specialreg.h,v 1.146 2019/05/18 08:17:39 maxv Exp $	*/
 
-/*-
+/*
+ * Copyright (c) 2014-2019 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
  * Copyright (c) 1991 The Regents of the University of California.
  * All rights reserved.
  *
@@ -32,28 +58,24 @@
  */
 
 /*
- * Bits in 386 special registers:
+ * CR0
  */
 #define CR0_PE	0x0001	/* Protected mode Enable */
 #define CR0_MP	0x0002	/* "Math" Present (NPX or NPX emulator) */
 #define CR0_EM	0x0004	/* EMulate non-NPX coproc. (trap ESC only) */
 #define CR0_TS	0x0008	/* Task Switched (if MP, trap ESC and WAIT) */
 #define CR0_ET	0x0010	/* Extension Type (387 (if set) vs 287) */
-#define CR0_PG	0x8000	/* PaGing enable */
-
-/*
- * Bits in 486 special registers:
- */
 #define CR0_NE	0x0020	/* Numeric Error enable (EX16 vs IRQ13) */
 #define CR0_WP	0x0001	/* Write Protect (honor PTE_W in all modes) */
 #define CR0_AM	0x0004	/* Alignment Mask (set to enable AC flag) */
 #define CR0_NW	0x2000	/* Not Write-through */
 #define CR0_CD	0x4000	/* Cache Disable */
+#define CR0_PG	0x8000	/* PaGing enable */
 
 /*
- * Cyrix 486 DLC special registers, accessible as IO ports.
+ * Cyrix 486 DLC special registers, accessible as IO ports
  */
-#define CCR0	0xc0		/* configuration control register 0 */
+#define CCR0		0xc0	/* configuration control register 0 */
 #define CCR0_NC0	0x01	/* first 64K of each 1M memory region is non-cacheable */
 #define CCR0_NC1	0x02	/* 640K-1M region is non-cacheable */
 #define CCR0_A20M	0x04	/* enables A20M# input pin */
@@ -62,13 +84,11 @@
 #define CCR0_BARB	0x20	/* flushes internal cache when entering hold state */
 #define CCR0_CO		0x40	/* cache org: 1=direct mapped, 0=2x set assoc */
 #define CCR0_SUSPEND	0x80	/* enables SUSP# and SUSPA# pins */
-
-#define CCR1	0xc1		/* configuration control register 1 */
+#define CCR1		0xc1	/* configuration control register 1 */
 #define CCR1_RPL	0x01	/* enables RPLSET and RPLVAL# pins */
-/* the remaining 7 bits of this register are reserved */
 
 /*
- * bits in the %cr4 control register:
+ * CR4
  */
 #define CR4_VME		0x0001 /* virtual 8086 mode extension enable */
 #define CR4_PVI		0x0002 /* protected mode virtual interrupt enable */
@@ -102,21 +122,22 @@
 #define XCR0_Opmask	0x0020	/* AVX-512 Opmask */
 #define XCR0_ZMM_Hi256	0x0040	/* AVX-512 upper 256 bits low regs */
 #define XCR0_Hi16_ZMM	0x0080	/* AVX-512 512 bits upper registers */
+#define XCR0_PT		0x0100	/* Processor Trace state */
+#define XCR0_PKRU	0x0200	/* Protection Key state */
+#define XCR0_HDC	0x2000	/* Hardware Duty Cycle state */
+
+#define XCR0_FLAGS1	"\20" \
+	"\1" "x87"		"\2" "SSE"		"\3" "AVX"	\
+	"\4" "BNDREGS"		"\5" "BNDCSR"		"\6" "Opmask"	\
+	"\7" "ZMM_Hi256"	"\10" "Hi16_ZMM"	"\11" 

CVS commit: src/sys/arch/x86/include

2019-05-18 Thread Maxime Villard
Module Name:src
Committed By:   maxv
Date:   Sat May 18 08:17:39 UTC 2019

Modified Files:
src/sys/arch/x86/include: specialreg.h

Log Message:
Clean up a little, add new XCR0 bits, remove a few unused MSRs, and fix
typos.


To generate a diff of this commit:
cvs rdiff -u -r1.145 -r1.146 src/sys/arch/x86/include/specialreg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2019-05-14 Thread SAITOH Masanobu
Module Name:src
Committed By:   msaitoh
Date:   Tue May 14 18:11:34 UTC 2019

Modified Files:
src/sys/arch/x86/include: specialreg.h

Log Message:
 Add snprintb's string for cpuid7 edx bit 10 "MD_CLEAR".


To generate a diff of this commit:
cvs rdiff -u -r1.144 -r1.145 src/sys/arch/x86/include/specialreg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2019-05-14 Thread SAITOH Masanobu
Module Name:src
Committed By:   msaitoh
Date:   Tue May 14 18:11:34 UTC 2019

Modified Files:
src/sys/arch/x86/include: specialreg.h

Log Message:
 Add snprintb's string for cpuid7 edx bit 10 "MD_CLEAR".


To generate a diff of this commit:
cvs rdiff -u -r1.144 -r1.145 src/sys/arch/x86/include/specialreg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/x86/include/specialreg.h
diff -u src/sys/arch/x86/include/specialreg.h:1.144 src/sys/arch/x86/include/specialreg.h:1.145
--- src/sys/arch/x86/include/specialreg.h:1.144	Tue May 14 16:59:26 2019
+++ src/sys/arch/x86/include/specialreg.h	Tue May 14 18:11:34 2019
@@ -1,4 +1,4 @@
-/*	$NetBSD: specialreg.h,v 1.144 2019/05/14 16:59:26 maxv Exp $	*/
+/*	$NetBSD: specialreg.h,v 1.145 2019/05/14 18:11:34 msaitoh Exp $	*/
 
 /*-
  * Copyright (c) 1991 The Regents of the University of California.
@@ -437,6 +437,7 @@
 
 #define CPUID_SEF_FLAGS2	"\20" \
 "\3" "AVX512_4VNNIW" "\4" "AVX512_4FMAPS" \
+"\13" "MD_CLEAR"			\
 			"\16" "TSX_FORCE_ABORT"\
 	"\33" "IBRS"	"\34" "STIBP"	\
 	"\35" "L1D_FLUSH" "\36" "ARCH_CAP" "\37CORE_CAP"	"\40" "SSBD"



CVS commit: src/sys/arch/x86/include

2019-05-11 Thread Christos Zoulas
Module Name:src
Committed By:   christos
Date:   Sat May 11 13:40:26 UTC 2019

Modified Files:
src/sys/arch/x86/include: Makefile cpufunc.h

Log Message:
Undo previous, fixed in userland.


To generate a diff of this commit:
cvs rdiff -u -r1.23 -r1.24 src/sys/arch/x86/include/Makefile
cvs rdiff -u -r1.29 -r1.30 src/sys/arch/x86/include/cpufunc.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2019-05-11 Thread Christos Zoulas
Module Name:src
Committed By:   christos
Date:   Sat May 11 13:40:26 UTC 2019

Modified Files:
src/sys/arch/x86/include: Makefile cpufunc.h

Log Message:
Undo previous, fixed in userland.


To generate a diff of this commit:
cvs rdiff -u -r1.23 -r1.24 src/sys/arch/x86/include/Makefile
cvs rdiff -u -r1.29 -r1.30 src/sys/arch/x86/include/cpufunc.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/x86/include/Makefile
diff -u src/sys/arch/x86/include/Makefile:1.23 src/sys/arch/x86/include/Makefile:1.24
--- src/sys/arch/x86/include/Makefile:1.23	Sat May 11 08:58:17 2019
+++ src/sys/arch/x86/include/Makefile	Sat May 11 09:40:26 2019
@@ -1,4 +1,4 @@
-# 	$NetBSD: Makefile,v 1.23 2019/05/11 12:58:17 christos Exp $
+# 	$NetBSD: Makefile,v 1.24 2019/05/11 13:40:26 christos Exp $
 
 INCSDIR=/usr/include/x86
 
@@ -9,7 +9,6 @@ INCS=	aout_machdep.h \
 	cpu_extended_state.h \
 	cpu_rng.h \
 	cpu_ucode.h \
-	cpufunc.h \
 	cputypes.h \
 	cpuvar.h \
 	float.h \

Index: src/sys/arch/x86/include/cpufunc.h
diff -u src/sys/arch/x86/include/cpufunc.h:1.29 src/sys/arch/x86/include/cpufunc.h:1.30
--- src/sys/arch/x86/include/cpufunc.h:1.29	Sat May 11 08:58:17 2019
+++ src/sys/arch/x86/include/cpufunc.h	Sat May 11 09:40:26 2019
@@ -1,4 +1,4 @@
-/*	$NetBSD: cpufunc.h,v 1.29 2019/05/11 12:58:17 christos Exp $	*/
+/*	$NetBSD: cpufunc.h,v 1.30 2019/05/11 13:40:26 christos Exp $	*/
 
 /*
  * Copyright (c) 1998, 2007, 2019 The NetBSD Foundation, Inc.
@@ -329,12 +329,6 @@ void	x86_reset(void);
  */
 #define	OPTERON_MSR_PASSCODE	0x9c5a203aU
 
-uint64_t	rdmsr_locked(u_int);
-int		rdmsr_safe(u_int, uint64_t *);
-void		wrmsr_locked(u_int, uint64_t);
-
-#endif /* _KERNEL */
-
 static inline uint64_t
 rdmsr(u_int msr)
 {
@@ -349,6 +343,9 @@ rdmsr(u_int msr)
 	return (low | ((uint64_t)high << 32));
 }
 
+uint64_t	rdmsr_locked(u_int);
+int		rdmsr_safe(u_int, uint64_t *);
+
 static inline void
 wrmsr(u_int msr, uint64_t val)
 {
@@ -363,4 +360,8 @@ wrmsr(u_int msr, uint64_t val)
 	);
 }
 
+void		wrmsr_locked(u_int, uint64_t);
+
+#endif /* _KERNEL */
+
 #endif /* !_X86_CPUFUNC_H_ */



CVS commit: src/sys/arch/x86/include

2019-05-11 Thread Christos Zoulas
Module Name:src
Committed By:   christos
Date:   Sat May 11 12:58:17 UTC 2019

Modified Files:
src/sys/arch/x86/include: Makefile cpufunc.h

Log Message:
expose the {rd,wr}msr functions to userland and install the header for
the benefit of cpuctl (fix the build).


To generate a diff of this commit:
cvs rdiff -u -r1.22 -r1.23 src/sys/arch/x86/include/Makefile
cvs rdiff -u -r1.28 -r1.29 src/sys/arch/x86/include/cpufunc.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/x86/include/Makefile
diff -u src/sys/arch/x86/include/Makefile:1.22 src/sys/arch/x86/include/Makefile:1.23
--- src/sys/arch/x86/include/Makefile:1.22	Sat Feb 17 08:01:23 2018
+++ src/sys/arch/x86/include/Makefile	Sat May 11 08:58:17 2019
@@ -1,4 +1,4 @@
-# 	$NetBSD: Makefile,v 1.22 2018/02/17 13:01:23 kamil Exp $
+# 	$NetBSD: Makefile,v 1.23 2019/05/11 12:58:17 christos Exp $
 
 INCSDIR=/usr/include/x86
 
@@ -9,6 +9,7 @@ INCS=	aout_machdep.h \
 	cpu_extended_state.h \
 	cpu_rng.h \
 	cpu_ucode.h \
+	cpufunc.h \
 	cputypes.h \
 	cpuvar.h \
 	float.h \

Index: src/sys/arch/x86/include/cpufunc.h
diff -u src/sys/arch/x86/include/cpufunc.h:1.28 src/sys/arch/x86/include/cpufunc.h:1.29
--- src/sys/arch/x86/include/cpufunc.h:1.28	Thu May  9 13:09:50 2019
+++ src/sys/arch/x86/include/cpufunc.h	Sat May 11 08:58:17 2019
@@ -1,4 +1,4 @@
-/*	$NetBSD: cpufunc.h,v 1.28 2019/05/09 17:09:50 bouyer Exp $	*/
+/*	$NetBSD: cpufunc.h,v 1.29 2019/05/11 12:58:17 christos Exp $	*/
 
 /*
  * Copyright (c) 1998, 2007, 2019 The NetBSD Foundation, Inc.
@@ -329,6 +329,12 @@ void	x86_reset(void);
  */
 #define	OPTERON_MSR_PASSCODE	0x9c5a203aU
 
+uint64_t	rdmsr_locked(u_int);
+int		rdmsr_safe(u_int, uint64_t *);
+void		wrmsr_locked(u_int, uint64_t);
+
+#endif /* _KERNEL */
+
 static inline uint64_t
 rdmsr(u_int msr)
 {
@@ -343,9 +349,6 @@ rdmsr(u_int msr)
 	return (low | ((uint64_t)high << 32));
 }
 
-uint64_t	rdmsr_locked(u_int);
-int		rdmsr_safe(u_int, uint64_t *);
-
 static inline void
 wrmsr(u_int msr, uint64_t val)
 {
@@ -360,8 +363,4 @@ wrmsr(u_int msr, uint64_t val)
 	);
 }
 
-void		wrmsr_locked(u_int, uint64_t);
-
-#endif /* _KERNEL */
-
 #endif /* !_X86_CPUFUNC_H_ */



CVS commit: src/sys/arch/x86/include

2019-05-11 Thread Christos Zoulas
Module Name:src
Committed By:   christos
Date:   Sat May 11 12:58:17 UTC 2019

Modified Files:
src/sys/arch/x86/include: Makefile cpufunc.h

Log Message:
expose the {rd,wr}msr functions to userland and install the header for
the benefit of cpuctl (fix the build).


To generate a diff of this commit:
cvs rdiff -u -r1.22 -r1.23 src/sys/arch/x86/include/Makefile
cvs rdiff -u -r1.28 -r1.29 src/sys/arch/x86/include/cpufunc.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



Re: CVS commit: src/sys/arch/x86/include

2018-07-15 Thread Paul Goyette




On Sun, 15 Jul 2018, Paul Goyette wrote:


Any chance that this will fix kern/52919?

If not, can we do some additional re-arrangement of struct cpu_info to 
address the problem?


And in any case, shouldn't this cause a bump in kernel version, since 
you've changed a structure that is shared between kernel and modules?


:)



Modified Files:
src/sys/arch/x86/include: cpu.h

Log Message:
Hum. Move the __HAVE_DIRECT_MAP block a little below, otherwise dynamically
loaded kernel modules use a wrong offset for some ci_* fields. Found when
modloading tprof_amd on an AMD 10h, the read of ci_signature was at a
wrong address, and the cpu family was not detected correctly.


+--+--++
| Paul Goyette | PGP Key fingerprint: | E-mail addresses:  |
| (Retired)| FA29 0E3B 35AF E8AE 6651 | paul at whooppee dot com   |
| Kernel Developer | 0786 F758 55DE 53BA 7731 | pgoyette at netbsd dot org |
+--+--++


Re: CVS commit: src/sys/arch/x86/include

2018-07-15 Thread Paul Goyette

Any chance that this will fix kern/52919?

If not, can we do some additional re-arrangement of struct cpu_info to 
address the problem?




On Sun, 15 Jul 2018, Maxime Villard wrote:


Module Name:src
Committed By:   maxv
Date:   Sun Jul 15 08:47:43 UTC 2018

Modified Files:
src/sys/arch/x86/include: cpu.h

Log Message:
Hum. Move the __HAVE_DIRECT_MAP block a little below, otherwise dynamically
loaded kernel modules use a wrong offset for some ci_* fields. Found when
modloading tprof_amd on an AMD 10h, the read of ci_signature was at a
wrong address, and the cpu family was not detected correctly.


To generate a diff of this commit:
cvs rdiff -u -r1.94 -r1.95 src/sys/arch/x86/include/cpu.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.


!DSPAM:5b4b0a35163311665672011!




+--+--++
| Paul Goyette | PGP Key fingerprint: | E-mail addresses:  |
| (Retired)| FA29 0E3B 35AF E8AE 6651 | paul at whooppee dot com   |
| Kernel Developer | 0786 F758 55DE 53BA 7731 | pgoyette at netbsd dot org |
+--+--++


Re: CVS commit: src/sys/arch/x86/include

2017-09-29 Thread Maxime Villard

Le 29/09/2017 à 05:17, Ryota Ozaki a écrit :

Module Name:src
Committed By:   ozaki-r
Date:   Fri Sep 29 03:17:18 UTC 2017

Modified Files:
src/sys/arch/x86/include: pmap.h

Log Message:
Fix build

sys/arch/x86/x86/cpu.c:920:20: error: 'pmap_largepages' undeclared (first use 
in this function)
   smp_data.large = (pmap_largepages != 0);
 ^


To generate a diff of this commit:
cvs rdiff -u -r1.67 -r1.68 src/sys/arch/x86/include/pmap.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.


mmh yes, I patched my test machine but apparently didn't commit the updated
diff


Re: CVS commit: src/sys/arch/x86/include

2013-11-21 Thread SAITOH Masanobu
(2013/11/21 15:02), matthew green wrote:
 Module Name: src
 Committed By:msaitoh
 Date:Wed Nov 20 17:50:39 UTC 2013

 Modified Files:
  src/sys/arch/x86/include: specialreg.h

 Log Message:
 -  Add some AMD Fn8001 extended features %ecx bits definitions from
   the document (AMD64 Architecture Programmer's Manual Volume 3: 
 General-Purpose and
   System Instructions. Document revision 3.20)

 -  s/MXX/MMXX/ because this bit is MMX eXtention.
 
 i thought it was Multi Media eXtension.

 MMX:
Fn0001 %edx bit 23 (Intel and AMD)
Fn8001 %edx bit 23 (Same as Fn0001 %edx, AMD only)

 AMD MMX Extension:
Fn8001 %edx bit 22 (AMD extensions to MMX instruction, AMD Only)

See Pase 580 in AMD64 Architecture Programmer's manual Volume 3 revision 3.20 :)

-- 
---
SAITOH Masanobu (msai...@execsw.org
 msai...@netbsd.org)


re: CVS commit: src/sys/arch/x86/include

2013-11-20 Thread matthew green

 Module Name:  src
 Committed By: msaitoh
 Date: Wed Nov 20 17:50:39 UTC 2013
 
 Modified Files:
   src/sys/arch/x86/include: specialreg.h
 
 Log Message:
 -  Add some AMD Fn8001 extended features %ecx bits definitions from
   the document (AMD64 Architecture ProgrammerVolume 3: General-Purpose and
   System Instructions. Document revision 3.20)
 
 -  s/MXX/MMXX/ because this bit is MMX eXtention.

i thought it was Multi Media eXtension.


CVS commit: src/sys/arch/x86/include

2010-02-25 Thread David Young
Module Name:src
Committed By:   dyoung
Date:   Thu Feb 25 20:48:35 UTC 2010

Modified Files:
src/sys/arch/x86/include: pci_machdep.h

Log Message:
Change the pci_attach_args definition to allow machine-dependent
code to override the default pci(9) behavior by creating a non-NULL
pci_attach_args_t (on x86, pci_attach_args_t is always NULL) containing
one or more non-NULL function pointers.


To generate a diff of this commit:
cvs rdiff -u -r1.12 -r1.13 src/sys/arch/x86/include/pci_machdep.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/x86/include/pci_machdep.h
diff -u src/sys/arch/x86/include/pci_machdep.h:1.12 src/sys/arch/x86/include/pci_machdep.h:1.13
--- src/sys/arch/x86/include/pci_machdep.h:1.12	Wed Feb 24 21:34:23 2010
+++ src/sys/arch/x86/include/pci_machdep.h	Thu Feb 25 20:48:34 2010
@@ -1,4 +1,4 @@
-/*	$NetBSD: pci_machdep.h,v 1.12 2010/02/24 21:34:23 dyoung Exp $	*/
+/*	$NetBSD: pci_machdep.h,v 1.13 2010/02/25 20:48:34 dyoung Exp $	*/
 
 /*
  * Copyright (c) 1996 Christopher G. Demetriou.  All rights reserved.
@@ -63,9 +63,8 @@
 extern struct x86_bus_dma_tag pci_bus_dma64_tag;
 #endif
 
-struct {
-	int dummy;
-} pci_chipset_tag;
+struct pci_chipset_tag;
+struct pci_attach_args;
 
 /*
  * Types provided to machine-independent PCI code
@@ -74,6 +73,34 @@
 typedef union x86_pci_tag_u pcitag_t;
 typedef int pci_intr_handle_t;
 
+struct pci_chipset_tag {
+	pcireg_t (*pc_conf_read)(pci_chipset_tag_t, pcitag_t, int);
+
+	void (*pc_conf_write)(pci_chipset_tag_t, pcitag_t, int, pcireg_t);
+
+#if 0
+	int (*pc_find_rom)(struct pci_attach_args *, bus_space_tag_t,
+	bus_space_handle_t, int, bus_space_handle_t *, bus_space_size_t *);
+#endif
+
+	int (*pc_intr_map)(struct pci_attach_args *, pci_intr_handle_t *);
+
+	const char *(*pc_intr_string)(pci_chipset_tag_t, pci_intr_handle_t);
+
+	const struct evcnt *(*pc_intr_evcnt)(pci_chipset_tag_t,
+	pci_intr_handle_t);
+
+	void *(*pc_intr_establish)(pci_chipset_tag_t, pci_intr_handle_t, int,
+	int (*)(void *), void *);
+
+	void (*pc_intr_disestablish)(pci_chipset_tag_t, void *);
+
+	pcitag_t (*pc_make_tag)(pci_chipset_tag_t, int, int, int);
+
+	void (*pc_decompose_tag)(pci_chipset_tag_t, pcitag_t,
+	int *, int *, int *);
+};
+
 /*
  * i386-specific PCI variables and functions.
  * NOT TO BE USED DIRECTLY BY MACHINE INDEPENDENT CODE.
@@ -81,7 +108,6 @@
 void		pci_mode_set(int);
 int		pci_mode_detect(void);
 int		pci_bus_flags(void);
-struct		pci_attach_args;
 
 /*
  * Functions provided to machine-independent PCI code.



CVS commit: src/sys/arch/x86/include

2010-02-25 Thread David Young
Module Name:src
Committed By:   dyoung
Date:   Thu Feb 25 20:48:35 UTC 2010

Modified Files:
src/sys/arch/x86/include: pci_machdep.h

Log Message:
Change the pci_attach_args definition to allow machine-dependent
code to override the default pci(9) behavior by creating a non-NULL
pci_attach_args_t (on x86, pci_attach_args_t is always NULL) containing
one or more non-NULL function pointers.


To generate a diff of this commit:
cvs rdiff -u -r1.12 -r1.13 src/sys/arch/x86/include/pci_machdep.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2010-02-24 Thread David Young
Module Name:src
Committed By:   dyoung
Date:   Wed Feb 24 21:24:20 UTC 2010

Modified Files:
src/sys/arch/x86/include: pci_machdep.h

Log Message:
Change 'typedef void *pci_chipset_tag_t' to 'typedef struct
pci_chipset_tag *pci_chipset_tag_t' for an improvement in type safety.
(Back when I did the same for cardbus_chipset_tag_t, it helped to turn
up some bugs!)


To generate a diff of this commit:
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/x86/include/pci_machdep.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2010-02-24 Thread David Young
Module Name:src
Committed By:   dyoung
Date:   Wed Feb 24 21:25:52 UTC 2010

Modified Files:
src/sys/arch/x86/include: pci_machdep.h

Log Message:
Don't bother to #define PCI_PREFER_IOSPACE, nothing uses it.


To generate a diff of this commit:
cvs rdiff -u -r1.10 -r1.11 src/sys/arch/x86/include/pci_machdep.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2010-02-24 Thread David Young
Module Name:src
Committed By:   dyoung
Date:   Wed Feb 24 21:34:23 UTC 2010

Modified Files:
src/sys/arch/x86/include: pci_machdep.h

Log Message:
KNF: change spaces to tabs.


To generate a diff of this commit:
cvs rdiff -u -r1.11 -r1.12 src/sys/arch/x86/include/pci_machdep.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2010-01-13 Thread Christoph Egger
Module Name:src
Committed By:   cegger
Date:   Wed Jan 13 12:54:49 UTC 2010

Modified Files:
src/sys/arch/x86/include: specialreg.h

Log Message:
recognize SVM PauseFilter


To generate a diff of this commit:
cvs rdiff -u -r1.37 -r1.38 src/sys/arch/x86/include/specialreg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/x86/include

2010-01-09 Thread Christoph Egger
Module Name:src
Committed By:   cegger
Date:   Sat Jan  9 20:50:11 UTC 2010

Modified Files:
src/sys/arch/x86/include: i82489reg.h

Log Message:
add LAPIC_MSR_ENABLE_x2 MSR. from mur...@river-styx via port-amd64@
   '...as documented in the Intel 64 and IA32 Architectures Software
   Developers Manual 3A, chapter 10.5.1.'


To generate a diff of this commit:
cvs rdiff -u -r1.8 -r1.9 src/sys/arch/x86/include/i82489reg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.